JPH03196677A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03196677A JPH03196677A JP1339638A JP33963889A JPH03196677A JP H03196677 A JPH03196677 A JP H03196677A JP 1339638 A JP1339638 A JP 1339638A JP 33963889 A JP33963889 A JP 33963889A JP H03196677 A JPH03196677 A JP H03196677A
- Authority
- JP
- Japan
- Prior art keywords
- input
- gate oxide
- oxide film
- circuit
- stage circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特にMOSFETの静電破
壊対策を設けた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device provided with measures against electrostatic damage of MOSFET.
最近、半導体集積回路は、ますます大容量化し、それに
並行して高速化が進んでいる。そして、高速化を図るた
めに、充放電能力を高める必要性から、ゲート酸化膜厚
はますます薄くなってきている。しかしながら、一般に
ゲート酸化膜厚が薄くなることによって、静電破壊が生
じやすくなる。Recently, semiconductor integrated circuits have been increasing in capacity and speed at the same time. In order to achieve higher speeds, the gate oxide film thickness is becoming thinner and thinner due to the need to increase charging and discharging capabilities. However, in general, as the thickness of the gate oxide film becomes thinner, electrostatic discharge damage becomes more likely to occur.
そこで、従来この種の金槁酸化物半導体(MOS)電界
効果トランジスタCFET)を用いた静を破壊対策とし
て、第3図に示す入力初段回路9が用いられていた。第
3図において、ポリシリ抵抗1と、拡散層抵抗2と、拡
散層等の寄生容量3.4と、N型MO8FET 5.6
とが示されている。Therefore, an input first stage circuit 9 shown in FIG. 3 has conventionally been used as a countermeasure against static damage using this type of metal oxide semiconductor (MOS) field effect transistor (CFET). In FIG. 3, a polysilicon resistor 1, a diffusion layer resistor 2, a parasitic capacitance such as a diffusion layer 3.4, and an N-type MO8FET 5.6
is shown.
さらに、ダイオード7を含めて、入力初段回路9となり
、バッド8が接続される。次の入力初段回路10にはC
MO8−FET12.13があり、内部回路11にはC
MO8−FET 14.15がある。Further, including the diode 7, it becomes an input first stage circuit 9, to which the pad 8 is connected. The next input first stage circuit 10 has C.
There is MO8-FET12.13, and the internal circuit 11 has C
There is MO8-FET 14.15.
さて、MOSFET5のドレインは電源電位VK。Now, the drain of MOSFET5 is at power supply potential VK.
ゲートは接地電位Gに、それぞれ接続され、MOSFE
T6のソースとゲートとは接地電位GK接続されている
。抵抗1.2及び寄生容量3.4は、いずれも静電気等
のサージ電圧が入力されたとき忙、ピーク電圧を抑える
ためのものであり、N型MO8FET 5.6はサージ
電圧の電荷をMOSFETのブレイクダウンにより、電
源電位Vまたは接地電位GK逃がすためのものである。The gates are connected to the ground potential G, respectively, and the MOSFE
The source and gate of T6 are connected to ground potential GK. Resistance 1.2 and parasitic capacitance 3.4 are both used to suppress peak voltage when surge voltage such as static electricity is input, and N-type MO8FET 5.6 suppresses the charge of surge voltage to MOSFET. This is to release the power supply potential V or ground potential GK by breakdown.
前述した様に、入力保護回路はサージ電圧のピークを抑
えて電荷の逃げ道を設けることが基本であるから、ゲー
ト酸化膜が薄くなればなるほど、抵抗1.2を大きくし
たり、寄生容量3,4を大きくしなければならない。As mentioned above, the basic idea of an input protection circuit is to suppress the peak of surge voltage and provide an escape route for charges, so the thinner the gate oxide film, the larger the resistance 1.2, the parasitic capacitance 3, 4 must be increased.
前述したように、従来例では、ゲート酸化膜が薄くなる
と入力保護回路9及び入力初段回路100M08FET
のゲート破壊が起こる危険性が高まる。そこで、入力保
:I!#回路9内の寄生容量3.4及び抵抗1.2を増
大させると、#電耐圧は向上できるが、入力初段回路1
0に入力されるべき波形が、寄生容i3.4及び抵抗1
.2によってなまってし1い、入力初段回路9の応答が
悪くなるという欠点がある。As mentioned above, in the conventional example, when the gate oxide film becomes thin, the input protection circuit 9 and the input first stage circuit 100M08FET
The risk of gate destruction will increase. So, input security: I! #If the parasitic capacitance 3.4 and resistance 1.2 in the circuit 9 are increased, #voltage resistance can be improved, but the input first stage circuit 1
The waveform to be input to 0 is parasitic capacitance i3.4 and resistance 1
.. 2, the response of the input first stage circuit 9 becomes worse.
本発明の目的は、入力初段回路の応答特性を低下させず
に、静電耐圧を向上させた半導体装置を提供することに
ある。An object of the present invention is to provide a semiconductor device with improved electrostatic withstand voltage without degrading the response characteristics of the input first stage circuit.
本発明の半導体装置の構成は、半導体基板上のパッドに
接続された入出力回路を構成するMOSFETのゲート
酸化膜が、前記基板上の他のMOSFETのゲート酸化
膜よりも厚く形成されていることを特徴とする。The structure of the semiconductor device of the present invention is such that a gate oxide film of a MOSFET constituting an input/output circuit connected to a pad on a semiconductor substrate is formed thicker than a gate oxide film of other MOSFETs on the substrate. It is characterized by
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の半導体装置を示す回路図で
ある。FIG. 1 is a circuit diagram showing a semiconductor device according to an embodiment of the present invention.
第1図において、本実施例が、第3図の従来例と異なる
点は、入力保護回路9を構成するMO8F E T 5
’、 6’、及び入力初段回路10を構成するMOSF
ET 12’、13’が、他の内部回路11を構成する
MOSFET 14.15等のゲート酸化膜より厚くな
っていることである。第1図では、ゲート酸化膜の厚さ
の違いを(MOSFET) の表記の違いで表わして
いる。第1図では、入力保護回路9゜及び入力初段回路
10を構成するMOSFETのゲート酸化膜を、他より
厚くすることKより、静電気によるゲート酸化膜破壊の
耐性を向上させている。In FIG. 1, the difference between this embodiment and the conventional example shown in FIG.
', 6', and MOSF constituting the input first stage circuit 10
The gate oxide film of the ETs 12' and 13' is thicker than that of the MOSFETs 14, 15, etc. that constitute the other internal circuits 11. In FIG. 1, the difference in the thickness of the gate oxide film is expressed by the difference in the notation of (MOSFET). In FIG. 1, the resistance to gate oxide film breakdown due to static electricity is improved by making the gate oxide films of the MOSFETs constituting the input protection circuit 9° and the input first stage circuit 10 thicker than other MOSFETs.
従って、入力保護回路9の抵抗1.2及び寄生容量3.
4を増大させることなく、静電気耐性が維持でき、また
、他の内部回路11のゲート酸化膜は薄くしているので
、内部回路11の高速性を失うことはない。もちろん、
第1図で入力報護回A!i!I9もしくは入力初段回路
10を構成するMOSFETの一部に限定して、ゲート
酸化膜を厚くしてもかまわない。Therefore, the input protection circuit 9 has a resistance 1.2 and a parasitic capacitance 3.
4, and the gate oxide film of the other internal circuits 11 is made thin, so the high speed performance of the internal circuits 11 is not lost. of course,
In Figure 1, input protection times A! i! The gate oxide film may be thickened only in a part of the MOSFET constituting I9 or the input first stage circuit 10.
ところで、ゲート酸化膜を厚くしたり薄くしたりする製
造法は、最初に入力保護回路9もしくは入力初段回路1
0を構成するMO8FET以外の内部回路に用いるゲー
ト酸化膜の厚さつまり薄い酸化膜を熱成長で規定の厚さ
にし、その後フォトレジストを塗布し、入力保護回路9
もしくは入力初段回路10を構成するMOSFETの部
分のみフォトレジストが除去されるようKL、その時点
で熱成長させると前記フォトレジストが除去された所だ
け、ゲート酸化膜が成長し、厚くなることを利用する。By the way, in the manufacturing method of making the gate oxide film thicker or thinner, first the input protection circuit 9 or the input first stage circuit 1 is
The thickness of the gate oxide film used for internal circuits other than the MO8FET that constitutes the input protection circuit 9 is thermally grown to a specified thickness, and then photoresist is applied.
Alternatively, if the photoresist is removed only from the MOSFET portion that constitutes the input first stage circuit 10, and thermal growth is performed at that point, the gate oxide film will grow and become thicker only where the photoresist is removed. do.
第2図は本発明の他の実施例の半導体装置を示す回路図
である。FIG. 2 is a circuit diagram showing a semiconductor device according to another embodiment of the present invention.
第2図において、本実施例で1ま、内部回@20からの
信号は、出力トランジスタ22.23を通って、出力バ
ッド21から出力される。出力端子に接続される出力ト
ランジスタ19′ta:$I成するMO8FET22.
23のゲート酸化膜は、他の内部MO5FET 24
、25 、26 、27のゲート酸化膜より厚くしであ
る。従って、出力端子に接続される出力トランジスタ1
9に対する静電気によるゲート酸化膜破壊の耐性が向上
できる。In FIG. 2, in this embodiment, the signal from the internal circuit @20 passes through the output transistors 22 and 23 and is output from the output pad 21. The output transistor 19'ta connected to the output terminal: MO8FET22.
The gate oxide film of 23 is the other internal MO5FET 24
, 25, 26, and 27. Therefore, the output transistor 1 connected to the output terminal
9, the resistance to gate oxide film breakdown due to static electricity can be improved.
以上、本発明の実施例の半導体装置は、半流体基板に形
成されたMOSFETを含む半導体装置において、入力
端子に接続される入力保護回路または入力初段回路を構
成するMOSFET 、もしくは出力端子に接続される
出力トランジスタを構成するMOSFETのゲート酸化
膜を、他の内部MO8FETより厚くしているという相
違点を有する。As described above, the semiconductor device of the embodiment of the present invention is a semiconductor device including a MOSFET formed on a semi-fluid substrate, and includes a MOSFET that constitutes an input protection circuit connected to an input terminal or an input first stage circuit, or a MOSFET connected to an output terminal. The difference is that the gate oxide film of the MOSFET that constitutes the output transistor is thicker than that of other internal MOSFETs.
以上説明したように、本発明は、例えば入力端子及び出
力端子に接続される入力保護回路、もしくは入力初段回
路または出力トランジスタを構成するMOSFETのゲ
ート酸化膜を他の内部MO8F、ETのゲート酸化膜よ
り厚くすること釦より、抵抗や容量等を増やすことなく
、静電破壊に対する耐圧を維持できる効果がある。As explained above, the present invention provides a method for replacing the gate oxide film of a MOSFET that constitutes an input protection circuit connected to an input terminal and an output terminal, or an input first stage circuit or an output transistor with a gate oxide film of another internal MO8F or ET. Making the button thicker has the effect of maintaining voltage resistance against electrostatic damage without increasing resistance or capacitance.
もちろん、本発明は、他の内部回路は、ゲート酸化膜を
薄くした捷まなので、高速性は維持できる。Of course, in the present invention, the other internal circuits are made by thinning the gate oxide film, so high speed can be maintained.
ィオード、8・・・・・・入力パッド、21・・・・・
・出力パッド、1・・・・・ポリシリコン抵抗、2・・
・・・拡散層抵抗。Diode, 8... Input pad, 21...
・Output pad, 1...Polysilicon resistor, 2...
...Diffused layer resistance.
Claims (1)
るMOSFETのゲート酸化膜が、前記基板上の他のM
OSFETのゲート酸化膜よりも厚く形成されているこ
とを特徴とする半導体装置。The gate oxide film of the MOSFET constituting the input/output circuit connected to the pad on the semiconductor substrate is connected to the other M on the substrate.
A semiconductor device characterized by being formed thicker than a gate oxide film of an OSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339638A JPH03196677A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339638A JPH03196677A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196677A true JPH03196677A (en) | 1991-08-28 |
Family
ID=18329391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1339638A Pending JPH03196677A (en) | 1989-12-26 | 1989-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196677A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465877A (en) * | 1990-07-06 | 1992-03-02 | Toshiba Corp | Semiconductor device |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| US5349227A (en) * | 1991-10-25 | 1994-09-20 | Nec Corporation | Semiconductor input protective device against external surge voltage |
| JPH09270493A (en) * | 1996-04-03 | 1997-10-14 | Lg Semicon Co Ltd | Active element protection structure and method of forming the structure |
| US6972446B1 (en) * | 1997-02-26 | 2005-12-06 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device and flash EEPROM |
| JP2009283610A (en) * | 2008-05-21 | 2009-12-03 | Elpida Memory Inc | Esd protective circuit |
| US8094846B2 (en) | 2006-12-18 | 2012-01-10 | Epcos Pte Ltd. | Deep sub-micron MOS preamplifier with thick-oxide input stage transistor |
-
1989
- 1989-12-26 JP JP1339638A patent/JPH03196677A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465877A (en) * | 1990-07-06 | 1992-03-02 | Toshiba Corp | Semiconductor device |
| US5349227A (en) * | 1991-10-25 | 1994-09-20 | Nec Corporation | Semiconductor input protective device against external surge voltage |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| JPH09270493A (en) * | 1996-04-03 | 1997-10-14 | Lg Semicon Co Ltd | Active element protection structure and method of forming the structure |
| US6972446B1 (en) * | 1997-02-26 | 2005-12-06 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device and flash EEPROM |
| US8094846B2 (en) | 2006-12-18 | 2012-01-10 | Epcos Pte Ltd. | Deep sub-micron MOS preamplifier with thick-oxide input stage transistor |
| JP2009283610A (en) * | 2008-05-21 | 2009-12-03 | Elpida Memory Inc | Esd protective circuit |
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