JPH0319686B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing mirrored wafers for use in semiconductor devices.

Normally, mirrored wafers are used as silicon substrates for ICs and VLS1. Mirror wafers include silicon substrates that are sliced, lapped, chamfered, and etched from silicon single crystal rods and then polished, and silicon substrates that are sliced, lapped, chamfered, and etched from silicon single crystal rods. Recently, silicon substrates are often subjected to gettering treatment. One of the gettering processes is intrinsic gettering (hereinafter referred to as IG). The methods proposed include low-temperature heat treatment, two-step heat treatment at low and high temperatures, and two-step heat treatment at high and low temperatures.
These can be fixed by two-step heat treatment at high and low temperatures, as described in the electronic materials supplementary volume P20 to P28 (micro defects) published on September 10, 1980.
It is stated that the lifetime of MOS diodes is improved.

This lifetime improvement is due to the MOS memory IC
It is thought that this will improve the hold time and yield rate of non-defective products.

However, although the inventors of the present invention created mirror-finished wafers with IG by heat treatment, they were unable to achieve the expected improvements in IC hold time and yield rate, and as a result, the results could not be applied to commercial products. Ta.

As a result of various experiments regarding the hold time and non-defective rate of semiconductor devices, the inventors found that
For mirror-finished wafers obtained by processing CZ single crystals,
It has been found that a great effect can be obtained by re-finishing the surface layer of the mirror-finished wafer by 0.5 to 20 microns after a two-step heat treatment at a high temperature of 1100°C or higher and then at a low temperature of 600 to 800°C.

That is, in a method of manufacturing a silicon substrate from a semiconductor silicon rod obtained by the CZ pulling method using a quartz crucible, the semiconductor silicon rod is sliced into wafers, and after mirror polishing, the wafer is heated at 1100°C or higher. A two-step heat treatment is performed at a high temperature of
A significant effect was obtained by removing ~20μ.

This will be explained below for each embodiment.

Example 1 P ^type (100 )7~10Ω-cm,
A 100φ, 525μ wafer was heated at 1150℃ in an Ar atmosphere.
for 2 hours, followed by heat treatment at 700°C for 8 hours. The surface layer of these wafers is etched to 0.5
~3μ removed.

FIG. 1 shows a comparison of the hold times when 0.5 to 3 μm is removed by the etching described above (curve A) and when it is not removed (curve B).

The horizontal axis in Figure 1 is the hold time (unit: ms),
The vertical axis shows the number of samples. As you can see from this, the hold time of the silicon substrate is curve A and curve B.
It was longer than the curve, and the hold time failure could be significantly reduced. From this, 1150℃ and
This shows that removing the 0.5-3μ surface layer after heat treatment at 700°C is important for improving hold time.

Example 2 P- ^type (100 )7~10Ω-cm,
A 100φ, 525μ wafer was heated at 1150℃ in an Ar atmosphere.
for 2 hours, followed by heat treatment at 700°C for 8 hours. The surface layer of these wafers is mirror polished to
5μ was removed.

After processing these wafers into MOS memory ICs,
As a result of measuring the hold time, the improvement was the same as in Example 1 described above, and the hold time failure was significantly reduced.

Example 3 A P-type (100) 7-10Ω-cm, 100φ wafer cut from a CZ dislocation-free single crystal containing an oxygen concentration of 14-18×10 ¹⁷ atoms/cc (ASTM display) was subjected to a chamfering process and a wrapping process. , then by etching
Finished as a mirror-finished wafer with a thickness of 550μ. Ar
Heat treatment was performed in the same atmosphere at 1200°C for 16 hours, and subsequently at 700°C for 8 hours.

The surface layer of the wafer was removed by 5-15μ mirror polishing.

After processing these wafers into MOS memory ICs,
As a result of measuring the hold time, the improvement was almost the same as the result of Example 1 described above, and the hold time failure was significantly reduced.

Example 4 A P-type (100) 7-10Ω-cm, 100φ wafer cut from a CZ dislocation-free single crystal containing an oxygen concentration of 14-18×10 ¹⁷ atoms/cc (ASTM display) was subjected to a chamfering process and a wrapping process. , by etching
Finished as a mirror-finished wafer with a thickness of 550μ.

These were heat-treated in an Ar atmosphere at 1200°C for 16 hours and then at 700°C for 8 hours in the same atmosphere.
The surface layer of the wafer was removed by 15-20μ mirror polishing.

After processing these wafers into MOS memory ICs,
As a result of measuring the hold time, the improvement was almost the same as the result of Example 1 described above, and the hold time failure was significantly reduced.

Example 5 A P-type (100) 7-10Ω-cm, 100φ wafer cut from a CZ dislocation-free single crystal containing an oxygen concentration of 14-18×10 ¹⁷ atoms/cc (ASTM display) was subjected to a chamfering process and a wrapping process. After that, by etching
Finished as a mirror-finished wafer with a thickness of 550μ.

These were heat treated in an Ar atmosphere at 1200°C for 16 hours, and subsequently at 700°C for 8 hours in the same atmosphere.
The surface layer of the wafer was removed by 25-30μ mirror polishing.

After processing these wafers into MOS memory ICs,
As a result of measuring the hold time, no improvement was observed.

The two-step heat treatment atmosphere in each of the above examples was Ar.
Atmospheric gas was used, but nitrogen or nitrogen with 1 oxygen added was used.
Similar results were obtained when adding %.

As described in each of the Examples and FIG. 1 above, the wafer produced by the method of the present invention
When fabricated into MOS memory ICs, the hold time was significantly improved, and the number of defects caused by hold time was significantly reduced, resulting in an improved yield rate.

[Brief explanation of the drawing]

Figure 1 shows the relationship between hold time and number of samples. A curve...When 0.5 to 3μ is removed from the surface,
B curve...if not removed.

Claims (1)

[Claims] 1 Mirrored wafers used for semiconductor devices are
In the manufacturing method, wafers processed from CZ single crystal to have a mirror finish are subjected to high temperatures of over 1100℃,
A method for producing a silicon substrate for a semiconductor device, which comprises performing a two-step heat treatment at a low temperature of 600° C. to 800° C. to remove 0.5 μm to 20 μm of the surface layer of the mirror-finished wafer.