JPH0319972U - - Google Patents
Info
- Publication number
- JPH0319972U JPH0319972U JP7938689U JP7938689U JPH0319972U JP H0319972 U JPH0319972 U JP H0319972U JP 7938689 U JP7938689 U JP 7938689U JP 7938689 U JP7938689 U JP 7938689U JP H0319972 U JPH0319972 U JP H0319972U
- Authority
- JP
- Japan
- Prior art keywords
- bits
- microcontroller
- clock
- audio data
- output level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Indicating Measured Values (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第１図及び第２図は本考案の実施例を示し、第
１図は回路ブロツク図、第２図は各部のタイムチ
ヤート図である。
１……４ビツトシフトレジスタ（遅延手段）、
３……８ビツトシフトレジスタ（シリアル−パラ
レル変換手段）、４……マイコン。
1 and 2 show an embodiment of the present invention, with FIG. 1 being a circuit block diagram and FIG. 2 being a time chart of each part. 1...4-bit shift register (delay means),
3... 8-bit shift register (serial-parallel conversion means), 4... microcomputer.
Claims (1)
データクロツクを所定時間だけ遅延させて遅延ワ
ードデータクロツクを出力する遅延手段と、 オーデイオ用のマスタークロツクをデータシフ
トクロツクとして用い、上位ビツトから下位ビツ
トの順にシリアルに送られてくるオーデイオデー
タを取込むシリアル−パラレル変換手段と、 前記遅延ワードデータクロツクの立上り又は立
下りで前記シリアル−パラレル変換手段に取込ま
れたオーデイオデータの上位複数ビツト分を入力
するマイコンとを備え、 このマイコンに取込まれた上位複数ビツトのオ
ーデイオデータに基づいて出力レベル表示を行う
よう構成したことを特徴とするオーデイオ再生装
置の出力レベル表示回路。[Claims for Utility Model Registration] Delay means for outputting a delayed word data clock by delaying a word data clock obtained by doubling the frequency of the LR clock by a predetermined time; Serial-to-parallel conversion means used as a shift clock to take in audio data sent serially in the order of upper bits to lower bits; An audio playback device comprising: a microcontroller for inputting upper plurality of bits of audio data taken into the microcontroller; and configured to display an output level based on the upper plurality of bits of audio data taken into the microcontroller. Device output level display circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7938689U JPH0319972U (en) | 1989-07-05 | 1989-07-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7938689U JPH0319972U (en) | 1989-07-05 | 1989-07-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319972U true JPH0319972U (en) | 1991-02-27 |
Family
ID=31623502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7938689U Pending JPH0319972U (en) | 1989-07-05 | 1989-07-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319972U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008286485A (en) * | 2007-05-18 | 2008-11-27 | Kanto Kogyo Kk | Storage and goods transportation system |
-
1989
- 1989-07-05 JP JP7938689U patent/JPH0319972U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008286485A (en) * | 2007-05-18 | 2008-11-27 | Kanto Kogyo Kk | Storage and goods transportation system |
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