JPH03200079A - Carrier and handler for semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the structure of a carrier and to improve accuracy for a test of electrical characteristic by providing a planar square-shaped frame body which substantially houses the entire semiconductor device including the package and outside pins. CONSTITUTION:The planar square-shaped frame body 10 which substantially houses the entire semiconductor device including the package and outside pins is provided on a carrier 1. At the time of characteristic inspection using a tester, recessed reference parts 12A, 12B as the reference surfaces are provided on the outer peripheral surface along one side of square of this frame body 10, and a recessed inserting/holding part 12c inserting and holding the frame body 10 together with the reference parts 12A, 12B is provided on the outer peripheral surface of frame body 10 which is faced oppositely to these reference parts 12A, 12B. A V-shaped reference part 12D is provided in either one of outer peripheral surfaces along each side of square of the frame body 10. Then, the positioning and fixing in the Y-direction are made by the inserting/holding part 12C and reference parts 12A, 12B when the carrier 1 is held on a tester part, and the positioning and fixing in the X-direction of carrier 1 are made by the V-shape of reference part 12D.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a carrier and a handler that transports the same, and in particular, a technique that is effective when applied to a carrier that stores a thin semiconductor device and a handler that transports the carrier. It is related to.

[Conventional technology] DRAM (Dynamic Random Access
s Memory), SRAM (Static RAM)
) and the like are constructed of resin-sealed semiconductor devices that are inexpensive to manufacture. This type of resin-sealed semiconductor device is a SOJ (Small○u) suitable for high packaging density.
t 1ine Jbend), Z I P (Zigza
g In 1ine Package) etc. are the mainstream. The basic structure of a resin-molded semiconductor device is that two rectangular opposed resin packages (mold resin) each have a rectangular planar shape.
A plurality of external leads are arranged on one side or on the outer surface along one side. The DRAM and SRAM are inside the resin package.
The semiconductor pellet loaded with etc. is sealed. The external terminals (ponding pads) and internal leads of this semiconductor pellet are electrically connected within the resin package.

Recently, TSOP (Small
A resin-sealed semiconductor device that employs an Out 1ine Package structure has been developed. A resin-sealed semiconductor device that adopts this TSOP structure has a thickness that is approximately one-third to one-third that of a resin-sealed semiconductor device that uses an S0J structure, for example, when mounting a DRAM with the same storage capacity.
1/4, approximately 1/4 to 1.5 in plane size
It is composed of a relatively small size.

The resin-sealed semiconductor device adopting the TSOP structure is
After the product is completed and before being shipped to the user, electrical characteristics tests are conducted under high and low temperature conditions. A handler with a built-in tester (contact driver) section is usually used for this electrical characteristic test. The handler is mainly composed of a loader section, a tester section, and an unloader section, and automatically transports the resin-sealed semiconductor device from the loader section to the tester section and from the tester section to the unloader section based on predetermined setting conditions.

The handler used by the inventor includes a loader section, a tester section,
The resin-sealed semiconductor device is transported by sliding down by gravity through the inclined guide rails disposed between the respective unloader sections.

The handler used by the present inventor is an SOJ structure or a Z
Compatible with resin-sealed semiconductor devices that adopt IP structure,
It is not compatible with resin-sealed semiconductor devices that adopt the TSOP structure. Further, at present, no handler compatible with resin-sealed semiconductor devices employing the TSOP structure is available on the market.

When a handler compatible with a resin-sealed semiconductor device that employs the SOJ structure or the like is used to conduct an electrical characteristic test of a resin-sealed semiconductor device that employs a TSOP structure, the following defects occur.

(1) A resin-sealed semiconductor device employing a TSOP structure is considerably smaller in size than a resin-sealed semiconductor device employing an SOJ structure, and therefore has a lighter weight. Therefore, the resin-sealed semiconductor device cannot be transported due to natural fall on the guide rail of the handler, resulting in transportation failure.

(2) Since the resin-sealed semiconductor device employing the TSOPm construction is small in size as described above, it is likely to rotate within the guide rail of the handler during transportation. If the diagonal size of the planar shape of the resin package of the resin-sealed semiconductor device is larger than the width of the guide rail, the resin-sealed semiconductor device may become clogged within the guide rail due to rotation during transportation, resulting in transportation problems. Causes defects.

(3) If the resin-sealed semiconductor device employing the TSOP structure comes into contact with the guide rail due to rotation during transportation, damage such as bending occurs to the external leads. Also, T.S.O.
When the protruding direction of the external leads of a resin-sealed semiconductor device that adopts the P structure matches the transport direction on the guide rail, the external leads come into contact with a stopper arranged in the transport path of the handler, and the external leads Damage may occur. If this external lead is damaged, the resin-sealed semiconductor device becomes a defective product.

In order to prevent such defects, it is optimal to use a technique in which a resin-sealed semiconductor device employing a TSOP structure is housed in a carrier, and the carrier is transported by a handler. for example,
Q F P (Quacl F fat Packag)
e) As a carrier for storing a resin-sealed semiconductor device that adopts the structure, see the Wells Electronic catalog, pages 32 and 33 (WELLS ELECT
RONIC, INC, USA, Pρ32-33).

The carriers described in this catalog have a square planar frame that houses a resin-sealed semiconductor device, and a standard slit shape that partitions the external leads at positions corresponding to between the external leads of the resin-sealed semiconductor device. A section will be established. This slit-shaped reference portion is used as a reference surface for positioning when housing the resin-sealed semiconductor device in the carrier in the arrangement direction of the external leads. Further, a U-shaped recess is provided in a side surface along one side of the rectangular shape of the carrier frame and a side surface along the other side facing the rectangular side. The U-shaped concave portion of the carrier abuts on a guide rail that is slightly smaller than the U-shaped concave portion and has the same cross-sectional shape as the U-shape, and is used as a conveyed portion during conveyance by a handler.

Further, the U-shaped concave portion of the carrier is used for positioning and fixing the carrier, with one side serving as a reference surface and the other side serving as a clamping surface during an electrical property test in the tester section. The U-shaped recesses, which serve as the reference surface and the clamping surface of the carrier, are brought into contact with the reference portion and the clamped portion, respectively, of the tester portion having the same cross-sectional shape as the guide rail.

Note that currently, there is no commercially available carrier that accommodates a resin-sealed semiconductor device employing a TSOP structure.

[Problem to be solved by the invention]

The present inventor discovered the following problems prior to developing a carrier for housing a resin-sealed semiconductor device employing a TSOP structure.

In the above-described electrical property test, the carrier is positioned and fixed to the tester section by the contact between the reference surface and the clamping surface of the carrier and the reference section and the clamped section of the tester section. The reference surface and clamping surface of the carrier are in contact with the reference part and clamped part of the tester part because they are both formed in U-shapes of different sizes, so they are point contact or line contact, and the carrier can be clamped. Positioning and fixing in the directions can be performed with high precision. However, there are clearances between the reference surface of the carrier and the reference portion of the tester section and between the clamping section and the clamped section due to their different sizes. In other words.

When positioning and fixing the carrier to the tester section,
Positioning accuracy in a direction orthogonal to the clamping direction in a plane direction is low. For this reason, the contact position between the external lead of the resin-sealed semiconductor device housed in the carrier and the test contact of the tester section is shifted, resulting in a contact failure, resulting in a failure in electrical characteristic testing. Further, erroneous judgments occur in electrical characteristic tests. In particular, in a resin-sealed semiconductor device employing a TSOP structure, the external leads have a fine pitch, so the above-mentioned problems occur significantly.

Furthermore, since the carrier accommodates the resin-sealed semiconductor device with reference to the external leads, a slit-shaped reference portion is required in the frame. Since the slit-shaped reference portion of this carrier is disposed on the external lead opening, it is difficult to process in manufacturing. especially.

Since the resin-sealed semiconductor device employing the TSOP structure has a fine pitch, the size of the slit-shaped reference portions of the carrier and the interval between the reference portions become fine, and the above-mentioned problems occur conspicuously.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can reduce electrical characteristic test defects in a carrier that houses a semiconductor device.

Another object of the present invention is to provide a technique that can reduce erroneous determinations in electrical characteristic tests in the carrier.

Another object of the present invention is to provide a technique capable of simplifying the structure of the carrier.

Another object of the present invention is to provide a technique that allows fine-pitch semiconductor devices to be accommodated in the carrier.

Another object of the invention is in the carrier.

An object of the present invention is to provide a technology that can improve the accuracy of housing semiconductor devices.

Another object of the present invention is to provide a technique that can improve the accuracy of electrical property testing in a handler that transports the carrier to a tester.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a carrier that houses a semiconductor device with external pins protruding from a package that is transported to a tester by a handler, a frame body having a rectangular planar shape that houses substantially the entire semiconductor device including the package and external pins is provided. A concave first reference part is provided on the outer surface along one side of the rectangular shape of the frame body, and a concave first reference part is provided on the outer surface of the frame body along one side of the rectangular shape. A concave-shaped clamping part that clamps the frame together with the first reference part on the side surface, and an outer surface along each side of the rectangular shape of the frame in the same plane as the direction in which the frame is clamped. Concave second reference portions serving as reference surfaces in orthogonal directions are provided. The carrier accommodates a resin-sealed semiconductor device employing a TSOP structure.

(2) The second reference part of the means (1) is the first reference part of the frame body.
It is provided on the outer surface of the reference portion or on the outer surface opposite thereto, and has a shape that makes two-point or two-line contact with the reference portion of the tester.

(3) The second reference portion of the means (1) has a V-shaped planar shape.

(4) In a carrier that stores a semiconductor device in which a plurality of external pins are arranged on one of the outer surfaces along each side of a planar rectangular package that is transported to a tester by a handler, the package and the external pins are a frame body for accommodating substantially the entire semiconductor device including the semiconductor device, and the inner surface of the frame body abuts on another outer surface perpendicular to the outer surface on which the external pins of the package of the semiconductor device are arranged. A third reference portion is provided to serve as a reference surface when storing the semiconductor device.

(5) The semiconductor device of the means (4) is a resin-sealed (resin mold) semiconductor device, and the third
The reference portion is provided on the inner surface of the frame, avoiding the resin gate portion of the package of the semiconductor device.

(6) In the handler for transporting each of the carriers of the means (1), (2), and (3) to the tester, a first reference portion that contacts the first reference portion of the carrier;
A clamped part that contacts the clamping part and a second reference part that contacts the second reference part are provided.

[For production]

According to the above-mentioned means (1), when testing the characteristics of the semiconductor device, the carrier can be positioned in the direction in which it is held between the first reference part and the holding part, and in the direction orthogonal thereto. It is possible to prevent poor contact with the testing contact of the tester, and to prevent faulty characteristic testing of semiconductor devices.

Furthermore, erroneous determinations during characteristic testing can be reduced. .

According to the above-mentioned means (2), the second reference part can be used as a reference surface and a clamping surface in a direction perpendicular to the clamping direction, so that the structure of the carrier is reduced by an amount corresponding to the portion serving as the clamping surface. can be simplified.

According to the above-mentioned means (3), the second reference part can be configured with a simple shape (a shape that is easy to process and can be produced with high precision).

According to the above-mentioned means (4), when storing a semiconductor device in the carrier, the third reference portion on the inner surface of the carrier and the outer surface where the external pins of the package of the semiconductor device are not arranged are connected to the carrier. Since the positioning of the external pins of the semiconductor device is performed in the arrangement direction, the slit-shaped reference portion formed at the position corresponding to the external pins and used for positioning the external pins in the arrangement direction is eliminated from the carrier. The structure of the carrier can be simplified in the arranged portion.

Furthermore, since the slit-shaped reference portion can be eliminated from the carrier, processing of the carrier can be simplified.

Furthermore, since the slit-shaped reference portion can be eliminated from the carrier, a semiconductor device having fine-pitch external pins can be stored in the carrier.

According to the above-mentioned means (5), since the outer surface of the package of the semiconductor device avoiding the part where flashing occurs is used as the reference surface, the positioning accuracy in the direction in which the external pins of the semiconductor device are arranged with respect to the carrier is improved. can be improved.

According to the above-mentioned means (6), when testing the characteristics of the semiconductor device, the carrier can be positioned in the direction in which the carrier is held between the first reference part and the holding part and in the direction perpendicular thereto. It is possible to prevent poor contact with the testing contact of the tester, and to prevent faulty characteristic testing of semiconductor devices.

Furthermore, erroneous determinations during characteristic testing can be reduced.

Hereinafter, the configuration of the present invention will be described using an example in which the present invention is applied to a carrier that accommodates a resin-sealed semiconductor device employing a TSOP structure, and a handler that transports the carrier and tests its characteristics.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 1 (cross-sectional view), FIG. 2 (top view), and FIG. 3 (side view) show the structure of a carrier that accommodates a resin-sealed semiconductor device that employs a TSOP structure, which is an embodiment of the present invention. show. Figure 1 is a sectional view taken along the line I-I in Figure 2;
The figure is a sectional view taken along the section line ``--'' in FIG.

As shown in FIGS. 1 to 3, the carrier is composed of a frame 10 that is rectangular in plan view. A cavity 11 is formed in the center of the frame 10 in which a resin-sealed semiconductor device 13 employing TSOPQ construction can be freely housed, fixed, and removed.

Resin-sealed semiconductor device 13 adopting the TSOP structure
As shown in FIG. 5 (side view), a plurality of external leads 13B are arranged around a resin package 13A in which a semiconductor pellet (not shown) is sealed.

The semiconductor pellet is composed of, for example, a single-crystal silicon substrate, and a DRAM is mounted on the element formation surface of this single-crystal silicon substrate. The resin package 13A is made of, for example, a phenol-curable epoxy resin. When mounting a DRAM of the same storage capacity, the resin package 13A of the resin-sealed semiconductor device 13 adopting the Tsop structure is the same as that of the resin-sealed semiconductor device 14 adopting the SOJ structure shown in FIG. 4 (side view). It is made up of a smaller size than the . For example, T.S.
The resin package 13A of the resin-sealed semiconductor device 13 adopting the OP structure has a thickness of 1 [mm], a width dimension (dimension in the arrangement direction of external leads) of 6 to 8 [mm], and a width of 14 to 19 mm.
It consists of a length of [mm]. In other words, the resin package 13A has a planar rectangular shape. External lead 13B
are arranged on each side of the resin package 13A along the opposite short sides of the rectangular shape.

For example, a total of 20 to 32 external leads 13B are arranged. In other words, the resin-sealed semiconductor device 13 employing the TSOP structure has a bidirectional flat lead structure in which the external leads 13B are arranged in two rows.

Although not shown, the external lead 13B is electrically connected to an external terminal (bonding pad) of the semiconductor pellet through an internal lead and a bonding wire.

In the cavity 11 of the frame 1o of the carrier 1, as shown in FIGS. 1 to 3, there are mainly a support part 11A, an external lead arrangement part 11B, a relief part 11C, an external lead arrangement direction reference surface 11D, and a presser foot. A section 11E is configured.

The support portion 11A is provided on the bottom portion of the frame 1o of the carrier 1. The cavity 11 is formed of a through hole having a planar rectangular shape, and four supporting parts 11A are arranged at each corner of the rectangular shape of the cavity 11. This support portion 11A is TS
When the resin-sealed semiconductor device 11f13 employing the OP structure is stored, the resin package 13A is brought into contact with each rectangular corner portion of the upper surface of the resin package 13A. In other words.

The support portion 11A can stably support the resin-sealed semiconductor device 13 by supporting at four locations. The support portion 11A is configured as a reference surface for positioning the resin-sealed semiconductor device 13 with respect to the carrier 1, and also prevents penetration from inside the cavity 11. Further, when the support portion 11A is stored in the carrier 1, most of the upper surface of the resin package 13A of the resin-sealed semiconductor device 13 is exposed, and the mark itself marked on the upper surface of the resin package 13A is exposed. In other words, the resin-sealed semiconductor device 13 adopting the TSOP structure, when housed in the carrier 1,
You can check the product type, serial number, index position, etc.

The external lead arrangement direction reference plane 11D is the frame 1 of the carrier 1.
0 along opposite long sides of the rectangular shape. That is, the external lead arrangement direction reference plane 11D is the external lead 13 of the resin package 13A of the resin-sealed semiconductor device 13.
It is provided on the frame body 10 of the carrier 1 at a position corresponding to a side surface perpendicular to the side surface on which B is arranged. This external lead arrangement direction reference surface 11D is configured as a reference surface for positioning the external leads 13B of the resin-sealed semiconductor device 13 with respect to the carrier 1 in the arrangement direction.

The relief portion 11C is provided in a concave planar shape at the center of the rectangular opposing long sides of the frame 10 of the carrier 1. That is, the relief portion 11G is provided in the same portion as the external lead array direction reference plane 11D of the frame 10, and is configured in the region of the center IIAS shown in FIGS. 1 and 2.

A resin gate (resin injection port during resin sealing) is provided in the center of the side surface along the long side of the resin package 13A of the resin-sealed semiconductor device 13 (corresponding to the area of the center line S). Since paris occurs, the relief portion 11G is configured as a relief for this paris. In other words, the resin-sealed semiconductor device 13 uses the side surface along the long side of the resin package 13 as a reference surface, excluding the area where the flash occurs, and this reference surface and the reference surface 11 of the carrier 1 in the external lead arrangement direction.
By making contact with D, positioning accuracy with respect to the carrier 1 can be improved.

The holding portion 11E is provided within the one relief portion 11C. This holding portion 11E includes an arm portion 11Ea and a contact portion 11.
Consists of Eb. The arm portion 11Ea has one end molded integrally with the frame 10, the other end integrally molded with the contact portion 11Eb, and has appropriate elasticity. The contact portion 11Eb directly contacts the side surface of the resin package 13A of the resin-sealed semiconductor device 13. The holding portion 11E presses the resin package 13A against the external lead array direction reference surface 11D and the support portion 11A of the carrier 1, and also fixes the resin package 13A.

Further, in this embodiment, only one presser portion 11E is provided at one location on the carrier 1, but two presser portions 11E may be provided, one at each of two opposing locations. In addition, presser part 1
1E is slightly more complicated to manufacture, but the frame 10 and a different material (
The material of the carrier 1 will be described later). For example, the carrier 1 may be made of a metal material.

The external lead array portions 11B are provided on each of the opposite short sides of the rectangular frame 10 of the carrier.

In other words, the external lead arrangement section 11B is attached to the frame 10 of the carrier 1 at a position where the tips (mounting parts) of the external leads 13B are arranged when the resin-sealed semiconductor device 13 is housed in the carrier 1. provided.

As shown in FIG. 1, the external lead arrangement section 11B is formed on the surface of a stepped section formed on the side surface inside the cavity 11 of the frame 10, and is in contact with the opposite surface facing the mounting surface of the external lead 13B. , is configured as a reference surface for vertical positioning of the resin-sealed semiconductor device 13 with respect to the carrier 1. The positioning of the external leads 13B of the resin-sealed semiconductor device 13 with respect to the carrier 1 in the arrangement direction (vertical direction in FIG. 2) is performed using the aforementioned external lead arrangement direction reference plane 11D and the side surface on which the external leads 13B of the resin package 13A are not arranged. Since this is carried out by contacting each of the (reference target surfaces), the external lead arrangement section 11B does not have a reference surface for positioning the external leads 13B in the arrangement direction. That is, the external lead arrangement section 11B does not include the conventional slit-shaped reference section described above.

The carrier 1 configured in this manner mainly uses the external lead arrangement section 11B as a reference plane in the vertical direction of the resin-sealed semiconductor device 13, and uses the external lead arrangement direction reference surface 11D as a reference plane in the arrangement direction of the external leads 13B. As a surface, a resin-sealed semiconductor device 13 is housed. In other words, the resin-sealed semiconductor device 13 is housed in the carrier 1 with the tips of the external leads 13B and the outer surface of the resin package 13A where the external leads 13B are not arranged as reference surfaces.

Further, on the outer periphery 12 of the frame 10 of the carrier 1, reference parts 12A, 12B, a holding part 12C1, a reference part 12D, and indexes 12E and 12F are provided.

Each of the reference portions 12A and 12B is provided on a side surface along one long side (lower side in FIG. 2) of the rectangular outer periphery 12 of the carrier 1. Each of the reference portions 12A and 12B is configured as a reference surface that comes into contact with the reference portion of the tester portion and positions the carrier 1 with respect to the tester portion during an electrical characteristic test. In this embodiment, two reference parts 12A and 12B are provided at positions separated from each other to improve stability during the above-mentioned positioning. That is, when stability is high, it is sufficient to provide one reference portion 12A or 12B in the carrier 1. Each of the reference portions 12A and 12B has a concave planar shape that does not reduce the accuracy as a reference surface even when the outer periphery 12 of the frame 10 of the carrier 1 is worn out due to an increase in the number of times it is transported by a handler, which will be described later. be done. That is, each of the reference portions 12A and 12B is configured to be lower than the surface of the outer periphery 12 of the frame 10 (concave toward the cavity 11 side). Further, each of the reference parts 12A and 12B is also configured as a holding surface when the carrier 1 is held between the tester part during an electrical characteristic test in the same direction as the arrangement direction of the external leads 13B.

The holding portion 12C is provided on a side surface of the outer periphery 12 of the carrier 1 along the other long side (the upper side in FIG. 2) opposite to the rectangular long side. The clamping part 12C comes into contact with the clamped part of the tester part during the electrical characteristic test, and the reference part 12A
and 12B, it is configured as a clamping surface when the carrier 1 is clamped in the tester section. The holding portion 12C has a concave planar shape similar to each of the reference portions 12A and 12B. In other words, the holding portions 12C1 reference portions 12A, 12
Each of B positions and fixes the carrier 1 in the Y direction shown in FIG. 2 when holding the carrier 1 in the tester section.

The reference portion 12D is provided on the side surface along the other long side (the upper side in FIG. 2) of the rectangular shape of the outer periphery 12 of the carrier 1, on the same long side as the holding portion 12C and spaced apart therefrom. Reference part 1
2D is configured as a reference surface that comes into contact with the reference portion of the tester section and positions the carrier 1 with respect to the tester section during an electrical characteristic test.

The reference part 12D, like the reference parts 12A and 12B, increases the number of times it is transported by a handler, which will be described later.
Even if the outer periphery 12 of the frame 10 is worn out, the accuracy as a reference surface is not reduced, and the frame body 10 has a concave planar shape. Specifically, as shown in FIG. 2, it is configured in a V-shape in plan view. The reference portion 12D is configured as a reference surface for positioning the carrier 1 on the tester portion during an electrical characteristic test in a direction orthogonal to the arrangement direction of the external leads 13B in the plane direction, that is, in the X direction. In addition, the reference part 12D
is also configured as a fixing surface for fixing the carrier 1 to the tester section in the X direction. That is, when the cross-sectional shape of the reference part of the tester part is formed in a circular shape (cylindrical shape or spherical shape) described later, the V-shape of the reference part 12D is in two-line contact or two-point contact with this reference part. This makes it possible to position the carrier 1 in the X direction and to fix the carrier 1.

Further, the reference portion 12D may be provided on the same side surface of the frame body 10 as the reference portions 12A and 12B, or on a side surface along the short side of the frame body 10. Further, the reference portion 12D has a contact surface with each of the reference portions having a V-shape in plan view by 2RIA contact or 2
It may also be composed of a curved surface that makes point contact.

As shown in FIG. 2, the index 12E is provided on the side surface of the frame 10 of the carrier 1 along the rectangular short side. In this embodiment, the index 12E has a planar semicircular shape, but is not limited to this shape.

This index 12E is configured for the purpose of confirming the storage direction when the resin-sealed semiconductor device 13 is stored in the carrier 1. Resin-encapsulated semiconductor device I! The index 13C on the 13 side is provided on the upper surface side of the resin package 13A, as shown in FIG. 9, which will be described later.

As shown in FIG. 3, the index 12F is provided in a shape in which the bottom corners of the frame 10 of the carrier 1 are chamfered along the long sides of the rectangular shape. The index 12E is configured for the purpose of unifying the transport direction when the carrier 1 is transported by a handler to be described later.

As shown in FIGS. 3 and 4, the carrier 1 configured in this way has an outer diameter including width, length, and thickness of SO.
It has substantially the same dimensions as the resin-sealed semiconductor device 14 that employs the J structure. In other words, since a handler compatible with the resin-sealed semiconductor device 14 that adopts the SOJ structure is used and the carrier 1 is transported by this handler, the carrier 1 is the same size as the resin-sealed semiconductor device 14 that uses the SOJ structure. It is matched. In order to allow the handler's guide rail to naturally fall under the same conditions as the resin-sealed semiconductor device 14 that adopts the SOJ structure, the carrier 1 is basically constructed using similar conditions such as its own weight and coefficient of friction. Formed with material. For example, the carrier 1 is made of a phenol-curable epoxy resin.6 The carrier 1 made of a resin material is easy to integrally mold even if it has a somewhat complicated shape. Further, the carrier 1 may be formed of a resin having a hardness different from that of the resin-sealed semiconductor device 13 or other materials.

The resin-sealed semiconductor device 13 adopting the TSOP structure housed in the carrier 1 described above is subjected to an electrical characteristic test by the handler 20 shown in FIG. 6 (schematic configuration diagram).

The handler 20 shown in FIG. 6 mainly includes a magazine stocker section 21A, a loader section 21, a transport section 22, a tester (contact driver) section 23, a transport section 24, and an unloader section 25.
and a magazine stocker section 25A.

The magazine stocker section 21A sequentially supplies magazines storing a plurality of carriers 1 to the loader section 21. A resin-sealed semiconductor device 13 employing a TSOP structure is housed in a carrier 1 housed in a magazine.

The loader section 21 sequentially transports the carriers 1 stored in the magazines supplied from the magazine stocker section 21 to a transport section 22.
supply to.

The transport section 22 transports the carrier 1 supplied from the loader section 21 to the tester section 23 . The transport section 22 is a loader section 21
From the side toward the tester section 23 side, the input rail 22
A, an escape rail 22B, an automatic check lead rail 22C, a distributor 22D, a storage track 22E, and a transfer 22F are sequentially arranged and configured. This conveyance section 22 is mainly composed of a conveyance mechanism that allows the carrier 1 to slide by falling naturally.

In the automatic check lead rail 22C of the conveyance section 22, as shown in FIG. 7 (a cross-sectional view of the main part),
Limit gauge 220 for checking the conveyance direction of carrier 1
will be placed. The limit gauge 220 is mainly used for the lower rail 2
22, an upper rail 221, a guide cavity 223 formed by these, and a gauge part 224 formed within this guide cavity 223. The limit gauge 220 passes through the guide cavity 223 when the carrier 1 is conveyed in the normal conveyance direction, and stops the conveyance when the carrier 1 is conveyed in any other conveyance direction. The normal conveyance direction is when the position of the gauge part 224 of the limit gauge 220 and the position of the index 12F of the carrier 1 match, and in the case of any other conveyance direction, the conveyance of the carrier 1 is stopped at the gauge part 224. .

The carrier 1 transported by the transport section 22 shown in FIG. 6 is subjected to an electrical characteristic test at the tester section 23.

The tester section 23, as shown in FIG. 8 (enlarged view of main parts),
The carrier 1 transported by the guide rail 23B is transferred to the measuring section 2.
3A, and the carrier 1 is stopped at this measuring section 23A.
The electrical characteristics of the resin-sealed semiconductor device 13 housed in the semiconductor device are inspected. Stopping the conveyance of the carrier 1
The fiber sensor 23F detects whether or not the carrier 1 is being transported through the sensor slit hole 23C arranged in the transport path of the carrier 1.
Based on this detection signal, the stopper drive shaft 23E is driven to project the stopper portion 23D into the transport path.

As shown in FIGS. 8 and 9 (enlarged perspective view of main parts), the measuring section 23A of the tester section 23 has a measuring socket 23.
0 and a socket board 236.

The measurement socket 230 has four socket guide parts 231
234 and an IC socket part 235.

As shown in FIG. 9, the socket guide portion 231 is configured as a reference portion that comes into contact with the reference portion 12A of the frame 10 of the carrier 1 and serves as a reference surface during an electrical characteristic test.

Similarly, the socket guide portion 232 is configured as a reference portion that comes into contact with the reference portion 12B of the frame 10 of the carrier 1 and becomes a reference surface. The socket guide part 233 is configured as a clamped part that comes into contact with the clamping part 12C of the frame 10 of the carrier 1 and becomes a clamped surface. By inserting the carrier 1 into each of these socket guide parts 231 to 233, the carrier 1 can be positioned and held in the Y direction with respect to the tester part 23. The socket guide portion 234 is configured as a reference portion that comes into contact with the reference portion 12D of the frame 10 of the carrier 1 and becomes a reference surface. The reference surface of this socket guide portion 234 is configured in a half-column shape that makes two-line contact with the V-shape of the reference portion 12D of the carrier 1. By inserting the carrier 1 into this socket guide section 234, the carrier 1 is inserted into the tester section 23.
can be positioned and held in the X direction. In this way, when the carrier 1 is positioned and fixed to the measuring section 23A of the tester section 23, each of the test contacts of the IC socket section 235 and the external leads 13B of the resin-sealed semiconductor device 13 adopting the TSOP structure are connected to each other. are brought into contact with each other, and the electrical characteristics of this resin-sealed semiconductor device 13 are tested.

IC socket section 23 of the measuring section 23A of the tester section 23
Insertion of the carrier 1 into the carrier 5 is automatically performed by the unit pushing shaft 23G shown in FIG.

The carrier 1 containing the resin-sealed semiconductor device 13 subjected to the electrical characteristic test in the tester section 23 is transported to the unloader section 25 by the transport section 24 shown in FIG. 6.

The transport section 24 transports the unloader section 2 from the tester section 23 side.
Mainly, an orienter 24A, a sort storage 24B, a sorter 24C, and a sorter track 24D are sequentially arranged and configured toward the 5 side. The conveyance section 24, like the conveyance section 22 described above, is mainly composed of a conveyance mechanism that allows the carrier 1 to slide by falling naturally.

The carrier 1 transported to the unloader section 25 is stored in a magazine, and this magazine is supplied to and stored in the magazine stocker section 25A.

In this way, in the carrier 1 that accommodates the resin-sealed semiconductor device 13 having the external leads 13B protruding from the resin package 13A, which is transported to the tester section 23 by the handler 20, the resin package 13A and the external leads 13B are
A frame body 10 having a rectangular planar shape for housing substantially the entire resin-sealed semiconductor device 13 including At the time of the electrical characteristic test, concave reference portions 12A and 12B that serve as reference surfaces, and the reference portions 12A and 12B are placed on the outer periphery 12 of the frame 10 facing the reference portions 12A and 12B.
and a concave-shaped holding portion 12C1 that holds the frame 10 together.
Concave reference portions 12D are provided on either of the outer peripheries 12 along each side of the rectangular shape of the frame 10 to serve as reference surfaces in a direction perpendicular to the direction in which the frame 10 is held in the same plane. .

The carrier 1 accommodates a resin-sealed semiconductor device 13 that employs a TSOP structure. With this configuration, when testing the characteristics of the resin-sealed semiconductor device [13], the reference portion 12A
, 12B, 12D, the holding portions 12C, and the socket guide portions 231 to 234, and the direction perpendicular thereto.
It is possible to prevent a poor contact between the test contact and the test contact of the C socket part 235 of the tester part 23, thereby preventing a faulty test of the electrical characteristics of the resin-sealed semiconductor device 13. Furthermore, it is possible to reduce erroneous determinations during electrical characteristic testing.

Further, the reference portion 12D of the frame body 10
The measuring section 2 of the tester section 23 is provided on the outer periphery 12 where A and 12B are provided or on the outer periphery 12 at a position opposite thereto.
2 for the reference part (socket guide part 234) of 3A
It is configured with a point contact or two line contact shape.

With this configuration, the reference part 12D can be used as a reference surface and a clamping surface in the X direction perpendicular to the clamping direction, so there is no need to newly provide a clamping surface in the X direction, and the part that becomes the clamping surface The structure of the carrier 1 can be simplified by a corresponding amount.

Further, the reference portion 12D has a V-shaped planar shape. With this configuration, the reference portion 12D has a simple shape that is easier to process or has higher processing accuracy than a curved surface, etc., so the structure of the carrier I can be further simplified and defects in electrical property tests can be reduced.

Further, the handler 20 transports it to the tester section 23 .

In a carrier 1 that accommodates a resin-sealed semiconductor device 13 in which a plurality of external leads 13B are arranged on one of the outer surfaces along each side of a resin package 13A having a rectangular planar shape, the resin package 13A and the outer A frame body 10 is provided which houses substantially the entire resin-sealed semiconductor device 13 including the leads 13B, and an outer surface on which the external leads 13B of the resin packages 1 and 3A of the resin-sealed semiconductor device 13 are arranged. Contacting another orthogonal outer surface (reference surface),
An external lead arrangement direction reference surface 11D is provided on the side surface of the cavity 11 of the frame 10, which serves as a reference surface when housing the resin-sealed semiconductor device 13. With this configuration, when housing the resin-sealed semiconductor device 13 in the carrier 1,
The outer lead arrangement direction reference surface 11D on the inner surface of the cavity 11 of the carrier 1, and the outer surface (reference surface) on which the outer leads 13B of the resin package 13A of the resin-sealed semiconductor device 13 are not arranged, respectively. The arrangement direction of the external leads 13B of the sealed semiconductor device 13 (
Since positioning is performed in the Y direction, a slit-shaped reference portion for positioning in the arrangement direction of the external leads 13B formed at positions corresponding to between the external leads 13B is placed on the carrier 1.
The structure of the carrier 1 can be simplified in the external lead arrangement section 11B where the external leads 13B are arranged. Further, since the slit-shaped reference portion can be eliminated from the carrier 1, processing of the carrier 1 can be simplified.

Further, since the slit-shaped reference portion can be eliminated from the carrier 1, the resin-sealed semiconductor device 13 whose external leads 13B have a fine pitch can be stored in the carrier 1. In other words, eliminating the slit-shaped reference part from the carrier 1 means that the resin-sealed semiconductor device adopts the TSOP structure for the carrier 1! ! This is an important technology in terms of storing 13.

Further, the outer lead arrangement direction reference surface 11 of the carrier 1
D is a resin package 1 of the resin-sealed semiconductor device 13
It is provided on the inner surface of the cavity 11 of the frame 1°, avoiding the resin gate part of 3A. In other words, the frame 10 of cavity 1
A relief portion 11C is provided. With this configuration, the outer surface of the resin package 13A of the resin-sealed semiconductor device 13, avoiding the part where flashing occurs, is used as the reference surface, so that the external lead 13B of the resin-sealed semiconductor device 13 with respect to the carrier 1 is set as the reference surface. It is possible to improve positioning accuracy in the direction in which the elements are arranged.

In addition, in the handler 20 that transports the carrier l to the tester section 23, the measurement section 23A of the tester section 23 has a
Socket guide parts 231 and 232 (reference target parts) that come into contact with the reference parts 12A and 12B of the carrier 1, respectively
, a socket guide portion 233 that comes into contact with the holding portion 12C;
(held portion) and a socket guide portion 234 (reference portion) that abuts the reference portion 12D. With this configuration, when inspecting the electrical characteristics of the resin-sealed semiconductor device 13, it is held between the reference parts 12A, 12B, 12D and the holding part 12C of the carrier 1 and the socket guide parts 231 to 234. Since the carrier 1 can be positioned in the direction and in the direction orthogonal to the direction, the external leads 13B of the resin-sealed semiconductor device 13 and the IC of the tester section 23 can be aligned.
It is possible to prevent poor contact between the socket portion 235 and the testing contact, and to prevent faulty electrical characteristic testing of the resin-sealed semiconductor device 13.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to a resin-sealed semiconductor device that employs a TSOP structure, but is applicable to other ZIP structures, SO
The J structure can be applied to a resin-sealed semiconductor device employing a QFP structure.

Further, the present invention is not limited to a two-way lead structure, but can be applied to a resin-sealed semiconductor device that employs a four-way lead structure.

Furthermore, the present invention is not limited to resin-sealed semiconductor devices;
Applicable to ceramic sealed semiconductor devices.

Further, the present invention can be applied to a resin-sealed semiconductor device for sealing a semiconductor pellet on which an SRAM is mounted, other semiconductor storage devices, and semiconductor logic devices.

Further, the present invention provides reference portions 12A and 12 of the carrier 1.
B and the holding portion 12C may each have a U-shape in plan view.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a carrier that houses a semiconductor device, defects in electrical property inspection can be reduced.

In the carrier, erroneous determinations in electrical characteristic testing can be reduced.

The structure of the carrier can be simplified.

In the carrier, fine-pitch semiconductor devices can be accommodated.

In the carrier, it is possible to improve the precision with which semiconductor devices are accommodated.

In the handler that transports the carrier to the tester, the electrical characteristic testing accuracy can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a carrier that accommodates a resin-sealed semiconductor device employing a TSOP structure, which is an embodiment of the present invention. FIG. 2 is a plan view of the carrier. FIG. 3 is a cross-sectional view of the carrier. 4 is a side view of a resin-sealed semiconductor device employing the SOJ structure. FIG. 5 is a side view of a resin-sealed semiconductor device employing the TSOP structure. FIG. 7 is a schematic configuration diagram of a handler that transports the carrier; FIG. 7 is a cross-sectional view of a main part of a transport section of the handler; FIG. 8 is an enlarged view of the main parts of the tester section of the handler, and FIG. 9 is an enlarged perspective view of the main parts of the tester section of the handler. In the figure, 1... carrier, 10... frame body, 11...
Cavity, IIB...external lead arrangement section, IIC.
...Relief part, 11D...External lead arrangement direction reference plane,
IIE... Presser part, 12... Outer periphery, 12A, 12
B, 12D... reference part, 12C... clamping part, 1
3...Resin-sealed semiconductor device, 13A...Resin package, 13B...External lead, 20...Handler, 21...Loader section, 22.24...Transportation section, 2
3...Tester part, 23A...Measurement part, 231-23
4...Socket guide section, 235...IC socket section, 25...Unloader section. Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. In a carrier that stores a semiconductor device with external pins protruding from a package, which is transported to a tester by a handler, a planar surface that stores substantially the entire semiconductor device including the package and external pins; A shaped frame is provided, and a concave-shaped first reference portion that serves as a reference surface during characteristic testing using the tester is provided on the outer surface of the frame along one side of the rectangular shape;
Either a concave-shaped holding part that holds the frame together with the first reference part on the outer surface of the frame facing the first reference part, or an outer face along each side of the rectangular shape of the frame. A carrier characterized in that a concave second reference portion is provided, each of which serves as a reference surface in a direction orthogonal to the direction in which the frame is held within the same plane. 2. The second reference portion is provided on the outer surface of the first reference portion of the frame body or on the outer surface opposite thereto, and has a shape that makes two-point or two-line contact with the reference portion of the tester. The carrier according to claim 1, characterized in that: 3. The carrier according to claim 2, wherein the second reference portion has a V-shaped planar shape. 4. In a carrier that stores a semiconductor device in which a plurality of external pins are arranged on one of the outer surfaces along each side of a planar rectangular package that is transported to a tester by a handler, the package and external pins are A frame body for housing substantially the entire semiconductor device including the semiconductor device is provided on an inner surface of the frame body that is in contact with another outer surface perpendicular to the outer surface on which the external pins of the package of the semiconductor device are arranged. A carrier characterized by being provided with a third reference portion that serves as a reference surface when storing a device. 5. The semiconductor device is a resin mold type semiconductor device, and the third reference portion of the carrier is provided on an inner surface of a frame body avoiding a resin gate portion of a package of the semiconductor device. The carrier according to item 4. 6. The carrier according to claim 1, wherein the carrier accommodates a semiconductor device employing a thin small outline package structure. 7. In the handler for conveying the carrier to the tester according to each of claims 1, 2, 3, and 6, the tester is provided with a first cover that comes into contact with the first reference part of the carrier. a reference part, a clamped part that comes into contact with the clamping part;
A handler characterized in that a second reference portion is provided, each of which comes into contact with a second reference portion.