JPH03200319A - Formation of poly-crystalline silicon - Google Patents
Formation of poly-crystalline siliconInfo
- Publication number
- JPH03200319A JPH03200319A JP34011789A JP34011789A JPH03200319A JP H03200319 A JPH03200319 A JP H03200319A JP 34011789 A JP34011789 A JP 34011789A JP 34011789 A JP34011789 A JP 34011789A JP H03200319 A JPH03200319 A JP H03200319A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- insulating film
- forming
- amorphous silicon
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 76
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 239000002344 surface layer Substances 0.000 claims abstract description 13
- 239000007790 solid phase Substances 0.000 claims abstract description 6
- 238000002425 crystallisation Methods 0.000 claims abstract description 4
- 230000008025 crystallization Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 23
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000010894 electron beam technology Methods 0.000 claims 1
- 238000005240 physical vapour deposition Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 62
- 239000010409 thin film Substances 0.000 abstract description 19
- 239000007789 gas Substances 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000009841 combustion method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- -1 silicon ions Chemical class 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910007264 Si2H6 Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 244000201986 Cassia tora Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- NCAIGTHBQTXTLR-UHFFFAOYSA-N phentermine hydrochloride Chemical compound [Cl-].CC(C)([NH3+])CC1=CC=CC=C1 NCAIGTHBQTXTLR-UHFFFAOYSA-N 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- XUIMIQQOPSSXEZ-OUBTZVSYSA-N silicon-29 atom Chemical compound [29Si] XUIMIQQOPSSXEZ-OUBTZVSYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路の製造方法に関し、特に電極
材料や抵抗体などの他、絶縁膜上での薄膜デバイス形成
に用いられる多結晶シリコン膜の形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semiconductor integrated circuit, and in particular, the present invention relates to a method for manufacturing a semiconductor integrated circuit. This invention relates to a method for forming a film.
従来のこの種の多結晶シリコン膜形成方法においては、
シリコン酸化膜又はシリコン窒化膜上、又はそれに替わ
る絶縁膜の上に減圧化学気相成長装置で原料ガスに５ｉ
Ｈｉを用いて、成長温度５８０℃以上の温度で多結晶シ
リコン膜を成長していた。In the conventional method of forming this type of polycrystalline silicon film,
5i is added to the source gas on a silicon oxide film or silicon nitride film, or on an insulating film to replace it, using a low pressure chemical vapor deposition apparatus.
A polycrystalline silicon film was grown using Hi at a growth temperature of 580° C. or higher.
上述した従来の多結晶シリコン膜形成方法では、シリコ
ン結晶粒はランダムな配向性をもち、例えば減圧下で成
長温度６２０〜６５０℃程度の温度で堆積した多結晶シ
リコン結晶粒は、約１００〜２０００人程度の結晶粒サ
イズをもち、多結晶シリコン膜表面の凹、凸も大きく、
膜垂直方向に約１００Å以上の粗れた表面をもっている
。このため、微細なデバイスや高集積度・高品質なデバ
イスを形成する場合、デバイス特性の低下（例えば、多
結晶シリコン上酸化膜耐圧低下や薄膜デバイスのリーク
特性悪化など）を招く欠点がある。In the conventional polycrystalline silicon film forming method described above, silicon crystal grains have a random orientation, and for example, polycrystalline silicon crystal grains deposited under reduced pressure at a growth temperature of about 620 to 650°C have a diameter of about 100 to 2000. It has a crystal grain size comparable to that of a human, and the surface of the polycrystalline silicon film has large concavities and convexities.
The film has a rough surface of about 100 Å or more in the vertical direction. For this reason, when forming minute devices or highly integrated/high quality devices, there is a drawback that device characteristics deteriorate (for example, a reduction in breakdown voltage of an oxide film on polycrystalline silicon and deterioration of leakage characteristics in thin film devices).
本発明の結晶の形成方法は絶縁膜基板上（一部単結晶シ
リコン表面があってもよい）にアモルファス・シリコン
を堆積し、アモルファス・シリコンの固相成長により結
晶化させて、多結晶シリコンを形成する方法において、
アモルファス・シリコンを結晶化させる前までにアモル
ファス・シリコンと絶縁膜基板界面の絶縁膜極表面層を
シリコンリッチな組成にする工程を有している。The crystal formation method of the present invention involves depositing amorphous silicon on an insulating film substrate (which may include a portion of the single crystal silicon surface), crystallizing the amorphous silicon by solid phase growth, and forming polycrystalline silicon. In the method of forming,
Before crystallizing the amorphous silicon, there is a step of making the extreme surface layer of the insulating film at the interface between the amorphous silicon and the insulating film substrate silicon-rich.
上述した従来の多結晶シリコンの形成方法に対し、本発
明では絶縁膜基板上（一部単結晶シリコン表面カアって
もよい）にアモルファスシリコンを堆積し、結晶化させ
て多結晶シリコンを形成すル方法において、アモルファ
ス・シリコンを結晶化させる前までに、アモルファス・
シリコンとの界面の絶縁膜極表面層をシリコン・リッチ
な組成をもつ状態にした後アモルファス・シリコンを結
晶化させて、シリコン膜の固相成長を行うことにより、
絶縁膜とアモルファス・シリコン膜界面の結晶化がスム
ースに行われ、従来の多結晶シリコンよりもシリコン結
晶粒が大きく、多結晶シリコン表面平坦性が良い多結晶
シリコンが形成できる。In contrast to the conventional method for forming polycrystalline silicon described above, the present invention involves depositing amorphous silicon on an insulating film substrate (a portion of the single crystal silicon surface may be removed) and crystallizing it to form polycrystalline silicon. In this method, before the amorphous silicon is crystallized, the amorphous
By making the extreme surface layer of the insulating film at the interface with silicon have a silicon-rich composition, and then crystallizing the amorphous silicon and performing solid phase growth of the silicon film,
Crystallization at the interface between the insulating film and the amorphous silicon film occurs smoothly, forming polycrystalline silicon with larger silicon crystal grains and better polycrystalline silicon surface flatness than conventional polycrystalline silicon.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の多結晶シリコン形成方法の一実施例の
縦断面図フローである。FIG. 1 is a longitudinal sectional view showing an embodiment of the method for forming polycrystalline silicon according to the present invention.
図（ａ）にはシリコン基板１１の上にシリコン酸化膜１
２を形成し、このシリコン酸化膜の極表面層にシリコン
のイオン注入を行った領域１３を示す。次に図（ｂ）に
は図（ａ）に示した基板の上に減圧化学気相成長装置で
原料ガスにＳｉＨ４又はＳｉ２Ｈ６ガスを用いて、成長
温度５００℃でアモルファスシリコン１４を膜厚０．２
μｍ堆積したところを示す。In Figure (a), a silicon oxide film 1 is formed on a silicon substrate 11.
2 is formed and silicon ions are implanted into the extreme surface layer of this silicon oxide film. Next, in Figure (b), amorphous silicon 14 is deposited on the substrate shown in Figure (a) with a film thickness of 0.5 mm at a growth temperature of 500°C using a low-pressure chemical vapor deposition apparatus using SiH4 or Si2H6 gas as the raw material gas. 2
The figure shows the amount of μm deposited.
次に図（ｃ）は上述した図（ｂ）に示した基板を窒素雰
囲気中で６００℃、２４時間の熱処理を行ったところを
示す。前記の極表面層にシリコンのイオン注入したシリ
コン酸化膜の熱処理後のシリコン酸化膜を１５に示す。Next, Figure (c) shows the substrate shown in Figure (b) described above subjected to heat treatment at 600° C. for 24 hours in a nitrogen atmosphere. 15 shows the silicon oxide film after heat treatment of the silicon oxide film in which silicon ions were implanted into the extreme surface layer.
またアモルファス・シリコンから結晶化した多結晶シリ
コン１６を示す。Also shown is polycrystalline silicon 16 crystallized from amorphous silicon.
多結晶シリコン１６は、アモルファス・シリコンとの界
面のシリコン酸化膜極表面層がシリコン・リッチな組成
をもつためアモルファス・シリコンの結晶化の際にアモ
ルファス・シリコンとシリコン酸化膜界面の横方向の結
晶化がスムースに行われ、従来の多結晶シリコンよりも
シリコン結晶粒が大きくて、多結晶シリコン表面平坦性
が非常に良い多結晶シリコンが得られている。Polycrystalline silicon 16 has a silicon-rich composition in the extreme surface layer of the silicon oxide film at the interface with the amorphous silicon, so when the amorphous silicon is crystallized, lateral crystals at the interface between the amorphous silicon and the silicon oxide film are formed. Polycrystalline silicon has been obtained which has larger silicon crystal grains than conventional polycrystalline silicon and has very good polycrystalline silicon surface flatness.
第２図には、本発明の他の実施例の縦断面図を、従来例
とあわせて示す。第２図（ａ）には従来の多結晶シリコ
ンを用いた薄膜ＭＯＳトランジスタの模式図を、（ｂ）
には本発明の多結晶シリコンを用いた薄膜ＭＯ３）ラン
ジスタの模式図を示す。FIG. 2 shows a longitudinal sectional view of another embodiment of the present invention together with a conventional example. Figure 2 (a) shows a schematic diagram of a conventional thin film MOS transistor using polycrystalline silicon, and (b)
2 shows a schematic diagram of a thin film MO3) transistor using polycrystalline silicon according to the present invention.
最初に第２図（ａ）の従来の多結晶シリコンを用いた薄
膜ＭＯ８）ランジスタ模式図から説明する。First, a schematic diagram of a conventional thin film MO8) transistor using polycrystalline silicon shown in FIG. 2(a) will be explained.
シリコン基板２１の上にシリコン酸化膜２２を９００℃
、水素−酸素燃焼法により膜厚０．２μｍ形成する。そ
の後、減圧化学気相成長装置で多結晶シリコン２３を成
長温度６５０℃で原料ガスにＳ ｉ Ｈ４を用いて堆積
する。さらに前記多結晶シリコンを９５０℃水素−酸素
燃焼法によりゲート酸化膜となるシリコン酸化膜２４を
膜厚０．０５μｍ形成する。次にゲート電極用多結晶シ
リコンを減圧化学気相成長装置で成長温度６５０℃、原
料ガスにＳ ｉ Ｈ４を用いて膜厚０．４μｍ堆積する
。次に、ゲート電極用多結晶シリコンに拡散法を用いて
不純物のＰを拡散する。さらにリソグラフィ技術、エツ
チング技術を用いて、ゲート電極用多結晶シリコン２５
を形成する。この後薄膜トランジスタ活性領域のチャネ
ル形成のためのＢＦ２イオン注入を加速電圧７０ＫｅＶ
、 ドース１．０Ｘ１０”ｃｍ−”の条件で行う。さら
に不純物活性化の熱処理を窒素雰囲気中、９００℃、３
０分の条件で行い、多結晶シリコン薄膜を用いた薄膜Ｍ
Ｏ３）ランジスタを形成している。A silicon oxide film 22 is formed on a silicon substrate 21 at 900°C.
, a film thickness of 0.2 μm is formed by a hydrogen-oxygen combustion method. Thereafter, polycrystalline silicon 23 is deposited using a low-pressure chemical vapor deposition apparatus at a growth temperature of 650° C. using S i H4 as a source gas. Furthermore, a silicon oxide film 24, which will become a gate oxide film, is formed to a thickness of 0.05 μm using the polycrystalline silicon at 950° C. using a hydrogen-oxygen combustion method. Next, polycrystalline silicon for the gate electrode is deposited to a thickness of 0.4 μm using a low-pressure chemical vapor deposition apparatus at a growth temperature of 650° C. and using SiH4 as a source gas. Next, impurity P is diffused into the polycrystalline silicon for the gate electrode using a diffusion method. Furthermore, using lithography technology and etching technology, polycrystalline silicon 25 for the gate electrode was formed.
form. After this, BF2 ion implantation for channel formation in the thin film transistor active region was performed at an acceleration voltage of 70KeV.
, at a dose of 1.0 x 10"cm-". Furthermore, heat treatment for impurity activation was performed at 900℃ for 3 days in a nitrogen atmosphere.
Thin film M using polycrystalline silicon thin film
O3) Forms a transistor.
次に第２図（ｂ）に本発明の多結晶シリコンを用いた薄
膜ＭＯＳトランジスタ模式図について示す。Next, FIG. 2(b) shows a schematic diagram of a thin film MOS transistor using polycrystalline silicon of the present invention.
シリコン基板２１の上にシリコン酸化膜を９００℃の水
素−酸素燃焼法により膜厚０．２μｍ形成し、さらにＳ
ｉイオン注入をシリコン酸化膜極表面層に行う。この後
、減圧化学気相成長装置でアモルファス・シリコンを成
長温度５００℃で原料ガスに８１２Ｈ６を用いて堆積す
る。次に前記アモルファス・シリコンにさらにＳｉイオ
ン注入を加速電圧１００ＫｅＶ、ドース１． ＯＸ １
０ ”ａｍ−２の条件で行った後、６００℃の窒素雰囲
気中で２４時間の熱処理を行いアモルファス・シリコン
を結晶化させて多結晶シリコン２７を形成する。次に、
前記の多結晶シリコンを９５０℃、水素−酸素燃焼法に
よりゲート酸化膜となるシリコン酸化膜２８を膜厚０．
０５μｍ形成する。さらに、減圧化学気相成長装置で成
長温度５００℃、原料ガスにＳｉ２Ｈ６を用いてアモル
ファス・シリコンを０．４μｍ堆積する。次に、ゲート
電極用多結晶シリコン形成前のアモルファス・シリコン
に拡散法を用いて不純物のＰを拡散する。Ｐ拡散条件は
原料ガスにｐｏｃρ３．温度９２０℃で１８分のＰ拡散
を行う。Ｐ拡散工程を終ることによって、前記アモルフ
ァス・シリコンは結晶化し、多結晶シリコンとなる。次
に、リングラフィ技術、エツチング技術を用いてゲート
電極用多結晶シリコン２９を形成する。この後、薄膜ト
ランジスタ活性領域のチャネル形成のためのＢＦ２イオ
ン注入を加速電圧７０ＫｅＶ、ドース１． ＯＸ １０
１５ｃｍ−２の条件で行う。さらに不純物活性化の熱処
理を窒素雰囲気中、９００℃、３０分の条件で行い多結
晶シリコン薄膜を用いた薄膜ＭＯ８）ランジスタを形成
している。A silicon oxide film with a thickness of 0.2 μm is formed on the silicon substrate 21 by a hydrogen-oxygen combustion method at 900°C, and then S
i ion implantation into the extreme surface layer of the silicon oxide film. Thereafter, amorphous silicon is deposited using a low pressure chemical vapor deposition apparatus at a growth temperature of 500° C. using 812H6 as a source gas. Next, Si ions are further implanted into the amorphous silicon at an acceleration voltage of 100 KeV and a dose of 1. OX1
After performing the process under the condition of 0" am-2, heat treatment is performed for 24 hours in a nitrogen atmosphere at 600° C. to crystallize the amorphous silicon and form polycrystalline silicon 27. Next,
The polycrystalline silicon was heated to 950° C. and the silicon oxide film 28, which will become the gate oxide film, was formed into a film with a thickness of 0.0° by a hydrogen-oxygen combustion method.
05 μm is formed. Furthermore, amorphous silicon is deposited to a thickness of 0.4 μm using a low-pressure chemical vapor deposition apparatus at a growth temperature of 500° C. and using Si2H6 as a source gas. Next, impurity P is diffused into the amorphous silicon before forming the polycrystalline silicon for the gate electrode using a diffusion method. The P diffusion conditions are pocρ3. P diffusion is performed for 18 minutes at a temperature of 920°C. By completing the P diffusion step, the amorphous silicon is crystallized and becomes polycrystalline silicon. Next, polycrystalline silicon 29 for the gate electrode is formed using phosphorography and etching techniques. After this, BF2 ion implantation for forming a channel in the thin film transistor active region was performed at an acceleration voltage of 70 KeV and a dose of 1. OX10
It is carried out under the condition of 15 cm-2. Furthermore, a heat treatment for impurity activation was performed at 900° C. for 30 minutes in a nitrogen atmosphere to form a thin film MO8) transistor using a polycrystalline silicon thin film.
第２図（ａ）に示した様に、従来の多結晶シリコンを用
いた場合、シリコン結晶粒サイズが小さく、多結晶シリ
コン表面の粗れが大きいため良質な多結晶シリコン上の
ゲート酸化膜が形成できない。As shown in Figure 2 (a), when conventional polycrystalline silicon is used, the silicon crystal grain size is small and the polycrystalline silicon surface is rough, so the gate oxide film on high-quality polycrystalline silicon is Cannot be formed.
ＭＯＳ）ランジスタのソース・ドレイン間のリーク電流
が大きい、キャリアの移動度が小さい。MOS) The leakage current between the source and drain of the transistor is large, and the mobility of carriers is small.
ホット・エレクトロンに対して弱いなどの問題点が生じ
ている。Problems such as vulnerability to hot electrons have arisen.
これに対し、第２図（ｂ）に示した本発明の多結晶シリ
コンを用いることにより、シリコン結晶粒は非常に大き
く （従来の多結晶シリコ、ンはシリコン結晶粒サイズ
は約１００〜２００Å以上度であるのに対して本発明の
多結晶シリコンは１〜５μｍ程度である。）、多結晶シ
リコン表面平坦性も非常に良い（従来の多結晶シリコン
では、膜縦方向の粗れは約１００〜２００Å以上である
のに対し、本発明の多結晶シリコンでは約５０Å以下と
なっている。）ため、良質な多結晶シリコン上酸化膜の
形成が可能である（例えば、多結晶シリコン上酸化膜厚
が３５０Å以下でも酸化膜の絶縁破壊耐圧は９ Ｍ Ｖ
／ ａｍ以上を示す。）ことや、薄膜多結晶シリコン
ＭＯ８）ランジスタの電気特性が向上（例えば、通常の
減圧化学気相成長で形成した多結晶シリコンよりも電子
の移動度が５倍以上高く、０Ｎ１０ＦＦ電流比は２桁以
上向上）するなどの効果がある。In contrast, by using the polycrystalline silicon of the present invention shown in FIG. The roughness of the polycrystalline silicon of the present invention is about 1 to 5 μm, whereas the roughness of the polycrystalline silicon surface is very good (conventional polycrystalline silicon has a roughness of about 100 μm in the longitudinal direction 200 Å or more, whereas the polycrystalline silicon of the present invention has a thickness of about 50 Å or less.) Therefore, it is possible to form a high-quality oxide film on polycrystalline silicon (for example, an oxide film on polycrystalline silicon). Even if the thickness is less than 350 Å, the dielectric breakdown voltage of the oxide film is 9 MV.
/am or more. ) and thin film polycrystalline silicon MO8) improved electrical properties of transistors (for example, electron mobility is more than 5 times higher than polycrystalline silicon formed by normal low pressure chemical vapor deposition, and 0N10FF current ratio is 2 digits) This has the effect of improving
以上説明したように本発明は、絶縁膜基板上（一部単結
晶シリコン表面があってもよい。）にアモルファス・シ
リコンを堆積し、結晶化させて、多結晶シリコンを形成
する。このとき、アモルファス・シリコンを結晶化させ
る前までに、アモルファス・シリコンとの界面の絶縁膜
極表面層をシリコン・リッチな組成をもつ状態に形成し
、この後アモルファス・シリコンを結晶化させて、シリ
コン膜の固相成長を行うことにより、絶縁膜とアモルフ
ァス・シリコン膜界面の結晶化がスムースに行われ、従
来の多結晶シリコンよりもシリコン結晶粒が大きく多結
晶シリコン表面平坦性が非常に良い多結晶シリコンが形
成できる効果があり、さらに上記した本発明の多結晶シ
リコンを半導体集積回路に応用することにより、例えば
多結晶シリコン上酸化膜の耐圧向上や薄膜多結晶シリコ
ントランジスタの電気特性の向上、多結晶シリコン抵抗
の温度特性改善などができ、半導体デバイスの高性能化
、高集積化に効果がある。As explained above, in the present invention, amorphous silicon is deposited on an insulating film substrate (a portion of which may be a single crystal silicon surface) and crystallized to form polycrystalline silicon. At this time, before crystallizing the amorphous silicon, the extreme surface layer of the insulating film at the interface with the amorphous silicon is formed to have a silicon-rich composition, and then the amorphous silicon is crystallized. By performing solid-phase growth of the silicon film, crystallization at the interface between the insulating film and the amorphous silicon film occurs smoothly, and the silicon crystal grains are larger than that of conventional polycrystalline silicon and the surface flatness of the polycrystalline silicon is very good. It has the effect of forming polycrystalline silicon, and furthermore, by applying the polycrystalline silicon of the present invention described above to semiconductor integrated circuits, it is possible to improve, for example, the withstand voltage of an oxide film on polycrystalline silicon and the electrical characteristics of thin-film polycrystalline silicon transistors. , it is possible to improve the temperature characteristics of polycrystalline silicon resistors, and it is effective in increasing the performance and integration of semiconductor devices.
第１図（ａ）〜（ｃ）は本発明の一実旅例の多結晶シリ
コン膜形成方法の一フロセス実施例の縦断面図、第２図
（ａ）、 （ｂ）は本発明の他の実施例の多結晶シリコ
ンを用いた薄膜ＭＯ３）ランジスタ模式図を従来の多結
晶シリコンを用いた場合と合わせて示した図である。
第１図
１１・・・・・・シリコン基Ｌ１２・・・・・・シリコ
ン酸化膜、１３・・・・・・シリコン・イオン注入され
たシリコンＭ化膜、１４・・・・・・アモルファス・シ
リコン、１５・・・・・・極表面層にシリコン・イオン
注入されたシリコン酸化膜を熱処理した後のシリコン酸
化膜、１６・・・・・・アモルファス・シリコンから結
晶化シタ多結晶シリコン
第２図
２１・・・・・・シリコン基板、２２・・・・・・シリ
コン酸化膜、２３・・・・・・従来の多結晶シリコン、
２３Ａ・・・・・・２３の多結晶シリコン薄膜中に形成
したチャネル（’／−ス）、２３Ｂ・・・・・・２３の
多結晶シリコン薄膜中に形成したチャネル（ドレイン）
、２４・・・・・・シリコン酸化膜、２５・・・・・・
ゲート電極用多結晶シリコン、２６・・・・・・極表面
層にシリコン・イオン注入したシリコン酸化膜を熱処理
した後のシリコン酸化膜、２７・・・・・・シリコン・
イオン注入したアモルファス・シリコンから結晶化した
多結晶シリコン、２７Ａ・・・・・・２７の多結晶シリ
コン薄膜中に形成したチャネル（ソース）、２７Ｂ・・
・・・・２７の多結晶シリコン薄膜中に形成したチャネ
ル（ドレイン）、２８・・・・・・シリコン酸化膜、２
９・・・・・・ゲート電極用多結晶シリコン。
卒１個
寅１／１FIGS. 1(a) to 1(c) are longitudinal cross-sectional views of an embodiment of a polycrystalline silicon film forming method according to the present invention, and FIGS. FIG. 3 is a diagram showing a schematic diagram of a thin film MO3) transistor using polycrystalline silicon according to the embodiment, together with a conventional case using polycrystalline silicon. Fig. 1 11...Silicon base L12...Silicon oxide film, 13...Silicon ion-implanted silicon M film, 14...Amorphous... Silicon, 15... Silicon oxide film after heat treatment of silicon oxide film with silicon ions implanted in the extreme surface layer, 16... Second polycrystalline silicon crystallized from amorphous silicon 21...Silicon substrate, 22...Silicon oxide film, 23...Conventional polycrystalline silicon,
23A...Channel ('/-s) formed in the polycrystalline silicon thin film of 23, 23B...Channel (drain) formed in the polycrystalline silicon thin film of 23
, 24... silicon oxide film, 25...
Polycrystalline silicon for gate electrode, 26...Silicon oxide film after heat treatment of silicon oxide film with silicon ions implanted into the extreme surface layer, 27...Silicon oxide film
Polycrystalline silicon crystallized from ion-implanted amorphous silicon, 27A... Channel (source) formed in the polycrystalline silicon thin film of 27, 27B...
... Channel (drain) formed in the polycrystalline silicon thin film of 27, 28 ... Silicon oxide film, 2
9... Polycrystalline silicon for gate electrode. Graduation 1 Tora 1/1
Claims (6)
た後、該アモルファス・シリコンにエネルギーを与えて
結晶化させて、多結晶シリコン膜を形成する方法におい
て、前記アモルファス・シリコンを結晶化させる前の絶
縁膜基板極表面層がシリコン・リッチな組成をもつこと
を特徴とする多結晶シリコンの形成方法。(1) In a method of forming a polycrystalline silicon film by depositing amorphous silicon on an insulating film substrate and then crystallizing the amorphous silicon by applying energy to the amorphous silicon, A method for forming polycrystalline silicon, characterized in that the extreme surface layer of an insulating film substrate has a silicon-rich composition.
ン表面が露出している基板を用いることを特徴とする結
晶の形成方法。(2) A method for forming a crystal, characterized in that the insulating film substrate according to claim 1 uses a substrate in which a single crystal silicon surface is partially exposed.
の形成は、絶縁膜形成時又はアモルファス・シリコン堆
積前、又はアモルファス・シリコン堆積後に行うことを
特徴とする結晶の形成方法。(3) A method for forming a crystal, wherein the formation of the silicon-rich layer on the extreme surface of the insulating film according to claim 1 is performed at the time of forming the insulating film, before depositing amorphous silicon, or after depositing amorphous silicon.
リコン窒化膜、又はシリコン酸化膜とシリコン窒化膜の
双方を用いることを特徴とする結晶の形成方法。(4) A method for forming a crystal, wherein the insulating film according to claim 1 is a silicon oxide film, a silicon nitride film, or both a silicon oxide film and a silicon nitride film.
の形成は、シリコンのイオン注入法又はシリコンのプラ
ズマドープ法又はシリコンのレーザ・ドープ法又は化学
気相成長法又は物理気相成長法のいづれか、又は各形成
法を組み合せて行う形成方法。(5) The formation of the silicon-rich layer on the extreme surface of the insulating film according to claim 1 is carried out by a silicon ion implantation method, a silicon plasma doping method, a silicon laser doping method, a chemical vapor deposition method, or a physical vapor deposition method. A forming method performed by any one of the following or a combination of each forming method.
は、７００℃以下の低温の熱処理による固相成長又はＸ
線や電子線を用いた固相成長による結晶の形成方法。(6) The crystallization of the amorphous silicon according to claim 1 is carried out by solid phase growth by heat treatment at a low temperature of 700°C or less or by
A method of forming crystals by solid phase growth using beams or electron beams.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34011789A JPH03200319A (en) | 1989-12-27 | 1989-12-27 | Formation of poly-crystalline silicon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34011789A JPH03200319A (en) | 1989-12-27 | 1989-12-27 | Formation of poly-crystalline silicon |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03200319A true JPH03200319A (en) | 1991-09-02 |
Family
ID=18333884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34011789A Pending JPH03200319A (en) | 1989-12-27 | 1989-12-27 | Formation of poly-crystalline silicon |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03200319A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466617A (en) * | 1992-03-20 | 1995-11-14 | U.S. Philips Corporation | Manufacturing electronic devices comprising TFTs and MIMs |
| KR100267145B1 (en) * | 1993-02-03 | 2000-10-16 | 야마자끼 순페이 | A method of manufacturing a thin film transistor |
| KR20120082800A (en) * | 2010-07-26 | 2012-07-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
-
1989
- 1989-12-27 JP JP34011789A patent/JPH03200319A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5466617A (en) * | 1992-03-20 | 1995-11-14 | U.S. Philips Corporation | Manufacturing electronic devices comprising TFTs and MIMs |
| KR100267145B1 (en) * | 1993-02-03 | 2000-10-16 | 야마자끼 순페이 | A method of manufacturing a thin film transistor |
| US6610142B1 (en) | 1993-02-03 | 2003-08-26 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor and process for fabricating semiconductor device |
| KR20120082800A (en) * | 2010-07-26 | 2012-07-24 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
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