JPH03201135A - Microprocessor - Google Patents

Abstract

PURPOSE:To attain debugging in a state close to a real time operation by forming a circuit capable of generating an interruption based upon a brake point to an optional instruction on the outside of a processor. CONSTITUTION:When addresses in a prescribed range are outputted from an operand address calculating circuit 4, a decision circuit 7 outputs a coincidence signal to a control circuit 1, which stops the operation of an instruction execut ing circuit 5 at the time of completing the operation of the circuit 5. The circuit 1 monitors an operand signal outputted from an address circuit 6 from the external, and in the case of generating an interruption based upon the brake point, the circuit 6 is interrupted at the time of ending the access. When the generation of an interruption is unnecessary, the circuit 5 automatically starts the execution of the succeeding instruction at the time of ending the access of the circuit 6. Consequently, the debugging can be attained in the state close to the real time operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor that performs pipeline control, and particularly to improvements that are effective in debugging programs in such a microprocessor.

Programs that have just been directly developed usually contain many errors, which must be removed. This work is called debugging, and a technique for debugging a program is disclosed in Japanese Patent Application Laid-Open No. 179033/1983.

This is a method in which, in order to debug a program, a register is provided inside the processor to store an address that causes an interrupt due to a breakpoint related to operand access, and the interrupt due to the breakpoint is generated within the processor.

(°5 By the way, as the program being developed becomes more complex, it becomes necessary to increase the number of breakpoints for debugging, but if you set many breakpoints, there is a possibility that the behavior will differ greatly from the behavior in real time.) , which may prevent effective debugging, and
As the number of functions implemented in processors increases in recent years, a problem arises in that it becomes difficult to provide a large number of registers for generating interrupts due to breakpoints inside the processor.

To solve this problem, it may be possible to add a circuit outside the processor that generates an interrupt due to a breakpoint for operand access, but in a microprocessor that uses pipeline control to increase data processing capacity, operand Since reading or writing is performed independently of instruction execution, there is a problem in that it is not possible to cause an interrupt by a breakpoint to any instruction from an external circuit.

In view of the above points, the present invention enables a microprocessor that performs pipeline control to construct a circuit outside the processor that can generate an interrupt using a breakpoint in response to an arbitrary instruction, and also enables real-time operation. The purpose is to enable depacking in similar situations.

! In order to achieve the above-mentioned object, the present invention provides a microprocessor that performs pipeline control, which comprises address calculation means for calculating the address of an operand to be accessed, and instruction execution means for executing an instruction corresponding to the operand. , determination means for determining whether the operand address output from the address calculation means is an address within a predetermined range;
If the operand address is within a predetermined range as a result of this determination, stopping means stops the operation of the instruction execution means at the time when the execution of the instruction that accesses the operand is completed; and when the operand access by the instruction is completed. and starting means for restarting the operation of the instruction execution means and starting execution of the next instruction.

According to the above configuration, when the operand address is within a predetermined range, the operation of the instruction execution means is stopped when the execution of the instruction corresponding to the operand address is completed, and the operation of the next instruction is stopped. Wait without processing. At this time, operand accesses related to instructions that have already been processed are continuing, so this can be monitored externally and an external interrupt request can be made when an access is made to an operand that causes an interrupt due to a breakpoint. It is possible to generate an interrupt at the end of an instruction that accesses an operand. On the other hand, in the case of an access to an operand that does not require an interrupt due to a breakpoint, by not issuing an external interrupt, the instruction execution means automatically resumes operation when the operand access is completed, and the next instruction is executed. Execute processing.

Figure 1 shows the configuration of a microprocessor in an embodiment of the present invention. In FIG. 1, 1 is a pipeline control circuit that controls the pipeline, 2 is an instruction fetch circuit that fetches instructions (from operation codes and operands), and 3 is an instruction fetch circuit 2. 4 is a decoding circuit that decodes the instruction fetched in the decoding circuit 4; 4 is an operand address calculation circuit that calculates the address and address of the operand to be accessed based on the result of decoding the instruction in the decoding circuit 4; 5 is an operand address calculation circuit that decodes the instruction in the decoding circuit 4; 6, an operand write circuit that stores the execution result of the instruction execution circuit 5 in a memory (not shown); 7, the operand address output from the address calculation circuit 4 is a break point. 101103.105.107.109 is a pipeline that determines whether the address is within the desired range (predetermined range) to be set. Stage status signal to notify control circuit 1, 102.1
04.106.108.110 is a hold signal used by the pipeline control circuit 1 to stop each circuit from executing the next instruction, and 200 is a store request signal.

The determination means 7 includes a register (hereinafter referred to as AR) 11 that stores a reference address, a register (hereinafter referred to as MR) 12 that stores mask information, a mask circuit 13, and a comparison circuit 14. ARll stores the reference address of the range in which it is desired to set a breakpoint. For example, if the operand address is represented by 5 bits, the range in which you want to set a breakpoint is from r10000J to "10111" of the operand address.
”, the reference address to be stored in the AR is rlooooJ.

On the other hand, the mask information stored in MR12 is r as information for masking the lower 3 bits of the operand address.
llooOJ is used. The mask circuit 13 is a circuit that performs a logical product for each bit of the operand address output from the operand address calculation circuit 4 and the mask information output from the MR 12, and the mask information consists of only the upper two bits as described above. In the case of rlJ, mask circuit 1
From 3 onwards, only the upper 2 bits of the operand address are output as they are. The comparison circuit 14 compares the reference address stored in the ARII with the output data of the mask circuit 13, and if the two match, generates a match signal. In the above example, the reference address is rloo.

Therefore, when the same data is output from the mask circuit 13, the comparison circuit 14 issues a match signal. Here, the mask circuit 13 outputs rl 0000J because the operand address is "10000" to r10111.
J, during which a match signal will be issued.

Reference numeral 15 denotes a register (hereinafter referred to as CR) that holds an enable pin (hereinafter referred to as E bit) that instructs to enable the -defeat signal.

Figure 2 shows the operation when the enable bit of CR15 is set to O in the above microprocessor, or the operation when the operand address is outside the predetermined range and no match signal is output from the determining means even if the enable bit is 1. This is equivalent to the pipeline control operation of a general microprocessor without the determining means 7.

In Figure 2, IF is the instruction fetch stage, DEC is the decode stage, OA is the operand address calculation stage, EXloF is the instruction execution stage and operand fetch stage, OW is the operand write stage, and N-N+3 is the processing stage. Hail each instruction that is given. IF, DEC,
The OA, EXloF, and OW stages correspond to the processing performed by the instruction fetch circuit 2, decode circuit 3, operand address calculation circuit 4, instruction execution circuit 5, and operand write circuit 6, respectively, in FIG.

In this embodiment, fetching of operands and execution of instructions are carried out exclusively in the EX10F stage.

The pipeline control operation will be explained based on FIG. First, when an instruction is fetched at the instruction fetch stage IF, the instruction is sent to the decode stage DEC and decoded. The decode stage DEC controls the operand address calculation circuit 4, instruction execution circuit 5, and operand write circuit 6 based on the decode result. That is, the operand address is calculated in the operand address calculation stage OA, the operand is fetched based on the address, and the fetched operand is sent to the instruction execution stage E.
Processed in X. When writing the execution result to the memory, the execution result is sent to the operand write stage OW, and writing to the non-illustrated memory is executed.

When each stage finishes processing based on instruction N and sends it to the next stage, it immediately starts processing based on the next instruction N+1. In this way, processing based on different instructions is performed for each stage in each cycle, making it possible to process data at high speed.

By the way, the above explanation is a general operation of pipeline control, but if the enable bit of CR15 is set to 1 and an operand address within a predetermined range is output from the operand address calculation circuit 4, Unlike the above, since the match signal 114 is applied from the determining means 7 to the pipeline control circuit 1, execution of the next instruction after the instruction that has accessed the operand is made to wait until the operand access is completed.

Next, this operation will be explained in detail. First, the pipeline control circuit 1 receives information from the decode circuit 3 through the store request signal 200 at the time of intra-frame decoding that there is a store of the processing result of the instruction processed in the instruction execution circuit 5, and the pipeline control circuit 1 receives this information from the store request signal 200. The instruction is held until it reaches the instruction execution circuit 5. And with this information, CR
15 enable bit and match signal 1 from determination means 7
14, the pipeline control circuit enables the hold signal 108. The instruction execution circuit 5 stops executing the next instruction in response to this hold signal 108. This stop continues until the operand write circuit 6 finishes writing the operand to the memory not shown, the operand write circuit 6 becomes empty, and the stage state signal 109 changes from invalid to valid. At this time, the operand write circuit 6
If the operand signal output from the microprocessor is monitored from outside the microprocessor and an interrupt is generated by a breakpoint, an external interrupt request is made to the microprocessor, and the operand access of the operand write circuit 6 is completed. Interrupt at that point.

On the other hand, if no interrupt is caused by a breakpoint, the operand write circuit 6 completes writing the operand and the stage state signal 109 becomes valid, so that the instruction execution circuit 5 starts executing the next instruction.

FIG. 3 shows a timing chart of the above operation example.

In FIG. 3, t1 to t7 are machine cycles, N-N
The operand address calculated in the OAX stage in instruction N is output in cycle t3, the address is masked according to the contents of MR12, and this mask result is compared with the contents of ARII. , a matching result 114 is output in cycle t4. CR1
5 is set, the EX stage hold signal 10B is output in cycle t5, and the EX stage processing that executed the instruction based on instruction N in t4 continues to instruction N+1 until the OW stage ends. The execution of the instruction based on the instruction (hereinafter referred to as the N+1 instruction) is stopped, and the N+1
Instructions are held at the OAX stage. In cycle t6, the staged Li signal 109 indicating that the OW stage is empty becomes valid, so that EX
Cycle t when the stage hold signal 10B becomes invalid
7, processing for the N+1 instruction starts at the EX stage. Operand write is performed while the execution of the N+1 instruction is awaited in cycles t5 to t6.

At this time, it is determined whether or not to cause an interrupt due to the breakpoint external to the microprocessor, and if an interrupt due to the breakpoint is generated, an external interrupt request is made to the microprocessor by cycle t6, so that the microprocessor Instruction processing is interrupted when the operand write is completed.

As described above, according to the microprocessor with this configuration, it is possible to make the execution of the next instruction wait until operand access within a predetermined address range is completed.
An external interrupt request can be made until the execution of the instruction that accesses a predetermined operand is completed.

Therefore, it is possible to construct a circuit that generates interrupts due to breakpoints outside the processor, and
Unlike inside a microprocessor sensor, it is possible to realize a circuit that generates interrupts due to many breakpoints without being limited by size.

Furthermore, if the execution of the instruction following the instruction that accessed the operand cannot be started until the operand access is finished, there is a possibility that the operation will be very different from the operation in real time, and effective debugging will not be possible. However, in this example, if an operand access outside the specified range is performed, the next instruction can be started without waiting for the end of the operand access, and debugging can be performed in a situation close to real-time operation. becomes.

Note that in the embodiment, the conditions for the instruction execution circuit to stop are limited to only when an operand is written, but it is also possible to execute the instruction following the instruction that performs an operand write, or the instruction that follows the instruction that performs either an operand write or an operand fetch. It may be stopped.

As described above, according to the present invention, the determination means detects that the operand access is within a predetermined range, and the operand access is executed after the instruction that accesses the operand. Since the instruction must wait until the instruction completes, the operand access is monitored outside the processor, and when the operand that causes an interrupt by a breakpoint is accessed, an external interrupt request is made and the instruction that accesses the operand is completed. Processing can be interrupted at any point. Therefore, compared to conventional means in which a register for generating breakpoint interrupts is provided inside a microprocessor, breakpoint interrupts can be generated in an external circuit for more operand accesses.

In addition, since the range in which instruction execution is stopped is limited to a predetermined range, programs can be debugged in conditions close to real-time operation without significantly disrupting the pipeline control flow. It contributes to improving efficiency in development, and its practical effects are significant.

[Brief explanation of drawings]

Fig. 1 shows the constituent countries of a microprocessor according to an embodiment of the present invention, Fig. 2 is a timing diagram showing the basic pipeline operation of the embodiment, and Fig. 3 shows a case where an interrupt occurs due to a breakpoint in the embodiment. FIG. 3 is a timing diagram showing an example of the operation of FIG. Fig. 1 1... Pipeline control circuit, 2... Instruction fetch circuit, 3... Decoding circuit, 4...
Operand address calculation circuit, 5... instruction execution circuit,
6... Operand address circuit, 7... Judgment means,
ll...AR, 12...MR, 13...mask circuit, 14...comparison circuit, 15...CR

Claims (1)

[Claims] (1) A microprocessor that performs pipeline control, which includes address calculation means for calculating the address of an operand to be accessed, instruction execution means for executing an instruction corresponding to the operand, and operand address output from the address calculation means. determination means for determining whether the address is within a predetermined range; and if the result of this determination indicates that the operand address is within the predetermined range, the operation of the instruction execution means is stopped upon completion of execution of the instruction that accesses the operand; and starting means for restarting the operation of the instruction execution means and starting execution of the next instruction when operand access by the instruction is completed.