JPH03201698A - Time division speech path - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

(Industrial Field of Application) The present invention relates to a time-division communication path, particularly the configuration of a time switch in a time-division automatic exchange and its control system. (Conventional technology) For example, the “Digital Switching System” published by the Telecommunications Mutual Aid Association

[]Basics of Hahard Sea Urchin J, pages 36-47 (Showa 6
1) describes the conventional technology for time division communication path equipment (TDNWI).As shown here, the three-stage TST configuration is typical as a configuration example of time division communication path equipment. In other words, the time-division channel device has a three-stage switch configuration including components such as a -secondary time switch, a highway switch, and a secondary time switch. Each of these components performs switching processing, etc. , the output information always has a delay with respect to the input information6
That is, the manual phase of the -year time switch is φI, and the manual phase of the highway switch is φ2. If the manual phase of the secondary time switch is φ3, these phases are different,
φl<φ2 × φ3. Therefore, in a 6-time division channel system where there is a phase difference of φ3 − φ1 between the -year time switch and the secondary time switch, information is multiplexed and the information is identified in the time slot in a fixed length frame. be done. Therefore, the multiplexed information input to each component is controlled so that the frame phases match. (Problems to be Solved by the Invention) In time division exchange, increasing the degree of multiplicity is more efficient and generally economical. However, in the conventional technology,
Changing the multiplicity for each stage requires a circuit for that purpose, so the multiplicity is often passed through at the same multiplicity. In this case, the capacity of the -order and quadratic time switches also increases as the degree of multiplicity increases. On the other hand, since each switch is a group with a predetermined purpose, in some cases, the amount of input information that can be accommodated may be smaller than the switch capacity. When there is little input information in this way, it is desirable to merge the time switches into primary time switches and secondary time switches, for example, instead of dividing them into primary time switches and secondary time switches. In the prior art, in such a case, the input phase to the switch had to be adjusted for one hour. That is, when adjusting the input phase to φ1, the input used for the secondary time switch is delayed by 1-(φ3-φl), and its output is further delayed by (φ3-φI). In addition, when matching the phase to φ3, the input used for the −year time switch is delayed by (φ3−φl), and the output is l−(φ3−φ1).
l) Delay. In any of these cases, a circuit for synchronizing the frames is required, and the conventional technology has a problem in that the amount of hardware increases significantly. The present invention eliminates the drawbacks of the prior art, and allows information that has a phase difference at the time of inputting to each time switch to
Even if these time switches are merged and accommodated simultaneously,
It is an object of the present invention to provide a time-division communication channel in which the amount of hardware necessary for performing frame synchronization does not increase. The present invention also provides the ability to preserve the time order of information even when time switches are configured with tuple buffers in multi-way information exchange.
An object of the present invention is to provide a time division multiplexing device that prevents disturbance of the T.411 (TSSI) and guarantees the law of preserving time order within a frame. (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention connects to highways having a phase difference and performs time-division exchange of information transmitted by the highways using exchange information stored in a control memory. The time-division communication path carried out in accordance with the above-mentioned communication channel includes timing signal generation means for outputting a timing signal that is a reference for time-division exchange, and phase correction means for correcting the phase of information transmitted using a phase different from that of the timing signal. The phase correction means performs time slot position correction on information input and output via the highway to be phase corrected, and then sends exchange information to the control memory. The invention also provides a time-division channel connected to a highway having a phase difference and configured with a double buffer for time-division exchange of information transmitted by the highway in accordance with exchange information stored in a control memory. The time-division multiplex information exchange device includes a timing signal generating means for outputting a timing signal serving as a reference in time-division exchange, and a means for correcting the designated position of a time slot for information transmitted by a highway having a phase different from that of the timing signal. and a control means for allocating a time slot for accommodating a high-speed call to a portion that overlaps with a frame based on a timing signal. (Function) According to the present invention, information sent via a highway having a phase different from that of a reference timing signal is time-division exchanged according to the control memory in which the position of the time slot is corrected by the phase correction means and stored. According to the present invention, a time slot for accommodating a high-speed call is allocated to a portion that overlaps with a frame defined by a reference timing signal to perform one-time division switching processing. (Example) Next, an example of a time division communication path according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, a six-time-division channel device l in which a functional block diagram of an embodiment of a time-division channel according to the present invention is shown includes, for example, a temporary time switch and a two-time time switch in a three-film configuration tTsTl. It is a combined communication path device and is used as a switch in time division exchanges, etc. The communication path device l is connected to a highway switch (H) as shown in the figure.
2N) 10, time switch 20, correction circuit 12, control memory write circuit 14, timing circuit TTIM) 16
and a control circuit (CC) 18. The time switch 20 is a switch that performs switching processing by changing the time position of information input from the highway, and corrects inputs that differ by one phase by correcting the position of time slots. The time switch 20 is
Connected to input highway (IHWI 100 and output highway (OHWl) 102, as well as highway (SIHII) 110 i5 and highway tsO
It is connected to the highway switch IO via HWl 112. Time switch 20O and highway switch 1O are connected to timing circuit 16 via clock signal line 160 or 162, respectively. The time switch 20 receives the reference timing φ3 from the timing circuit 16 via an input 160, and the highway switch IO receives the reference timing φ2 via an input 162. The time switch 20 is a circuit that performs time slot exchange using the input reference timing φ3 as a reference signal, and in addition to the time switch memory 22 and the control memory 24 that controls it,
Inside it, a control memory write circuit 14 and a phase correction circuit 12 are provided.
has. The time switch memory 22 is a memory switch that performs switching by converting an input time slot l in a frame into an output time slot j according to a control output 240 of the control memory 24. The time switch memory 22 multiplexes and switches signals input from a plurality of highways, separates the signals again, and outputs the signals to an output highway. The correction circuit 12 is a circuit that corrects the phase difference between a highway group different from the reference timing system. The correction circuit 12 is connected to the control memory 24 via a signal line 120, and outputs time slot correction information thereto. The control memory write circuit 14 is connected to the control circuit 18 via a bus 180 and outputs an output 140 to the correction circuit 12 in accordance with the control information received therefrom. The control circuit 18 is a control circuit that controls the plurality of time division time switches 20i5 and the highway switch 10 via the bus 180. Although one time switch 2o is shown in the figure to avoid complication of the diagram, in reality, a plurality of such switches 2o exist. Functionally, the time switch 2o converts the input time slot 1 in the frame into the output time slot j, so this conversion is denoted as T(i, jl in this embodiment. In order to realize this, the control memory 24 and time switch memory 22
The following control is performed between. Regarding the time switch, in principle, the sequential write/random read type and the random write/sequential read type are the same, so the latter will be explained here. The multiple input highways are multiplexed as shown in FIG. That is, if there are four input highways of 8 time slots in one frame, this is converted to one highway of 32 time slots. Also, if the number of output highways is the same as the input, the inverse transformation, that is, the separation is performed and the output highways are assigned according to the order of the time slots of the multiplexed highways6. Focusing on this, each time slot can be unconditionally associated with the time slot of each input/output highway. When sequential reading is performed, the multiplexed highway information unconditionally corresponds to each time slot of the output highway. The address of the multiplexed highway information is written to the time switch memory 22 by the network control memory 24. The control memory 24 is synchronized with the time switch memory 22 and executes Tfi, , i). In order to write the information of time slot i to the address indicating time slot j, write address j is output at the input timing of time slot i. That is, the control circuit 18 writes the information to address i of the control memory 24 through the control memory write circuit 14.
] The switching process of Tfi and jl is realized by instructing to write . As shown in the figure, when converting input highway time slot b to output highway time slot d in multiplexing of four highways, 1=4Xb+
a, j=4xd+c (here, a and C
indicates highway numbers 0 to 3). Therefore, as shown in Figure 3, there are two highways, HWO and HWI, and the phase difference between them is two timeslots.
The correction in the case will be explained. In the case of no correction, since the number of highways is two in the figure, 1=2Xb+a and j=2Xd+c. If the input highway and the output highway are HWI in 6, it is the same as the previous example and there is no problem. However, when both the human power highway and the output highway are HWO, the conversion is shifted by a phase difference, that is, by two time slots, so the result is T(i+4°j+41 [MOD 16], which is an incorrect conversion. In the figure, T( An example of incorrect conversion when executing 0, 21 is shown.Similarly, human-powered highway is HWO
If the output highway is )[1 then T(i+4.jl, if the input highway is H old and the output highway is HWO then T
(i, j+4). For this reason, on the actual flow side, the correction circuit 12 is provided with the following functions. That is, the input highway is H3N2
(7) If i□ 2X (b-21+a [MOo
16]. If the output highway is l-1w0, then j・2X (d-
2) +a[MOD16]. As a result, the address to be written into the control memory 24 is converted to the value i of this formula, and the information to be written is similarly converted to . By substituting this result into the incorrect conversion example mentioned above, it is clear that the correct T(i, jl can be obtained. In this example, the reference phase of the time switch is adjusted to HWI, but if it is adjusted to HWO, it becomes as follows. In other words, if the input highway is Hllll, l=2×
Ib+2)+a [MOD 161. If the output highway is HWI, j・2X fd+21+a [MOD
16]. Generalizing, if the total number of input highways (total number of output highways) is N and the number of time slots per highway is M, the phase difference from the reference timing is X at full input.
For the combination of time slots and X time slots on the output side, i:Nx 1b-xl+a [MOD NxM]j:
It may be converted to Nx 1d-y)+c [MOD NxM]. Note that x and y indicate the phase advance relative to the reference timing. In reality, there is a delay time of the time switch itself, so there are two reference timings: one for human power and one for output. Here, X is the normalized phase difference at the input example, and y is the normalized phase difference at the output side. The phase correction means need not be located after the control memory writing circuit, but may be located before or within the control circuit, and may be implemented in either hardware or software. In addition, although the number of input highways and output highways of the time switch are the same here, each time slot on one multiplexed highway corresponds to an input or output highway and a time slot within it. There is no restriction on the number of input/output highways as long as the number of input/output highways is the same.According to this embodiment, since information with four phase differences is directly input and the correction circuit 12 corrects the time slot position, a large amount of information can be used. An economical communication path can be formed without using frame memory. Note that the time switch used here may of course be either a single buffer or a double buffer. FIG. 4 shows an example in which this embodiment is applied to a multiple information exchange device that performs multiple information exchange1. In this case, as described above, time slot conversion is performed correctly, but the For example, when dealing with a triple call as shown in the figure,
If only the position of the time slot is corrected, the law of preserving the time order within the frame will be broken. When the time switch 20 is a tuple buffer, the time switch memory 22 has two sides, and writing and reading are performed alternately (F shown in the figure indicates the beginning of a frame). That is, regardless of the phase of the human power highway and the output highway, the information input to the frame position TI defined at the reference timing is written, for example, on side A, and is read from side A at T2. At T2, information for the next frame is written on the B side. Gatte, fAO, BO, cOl, IAI
. B1. The output information that is supposed to be C11, ., is +A1. which was written on the A side by TI in T2. BO, CO1, continued (A2.B1.C11, (A3.B2.C2
1, . . . Information is transmitted, but the law of preserving time order is broken. Similarly, the exchange of x, y, and z whose phases are delayed is lxl, yO, zO) and time order preservation I1 in T2.
1 collapses. When dealing with basic elements, there is no problem because the bus frame delay amount simply changes for each call, but in the case of high-speed calls, the information has meaning in blocks such as fA, B, C), so This results in the transmission of incorrect information. Therefore,
The positions of time slots that accommodate high-speed calls are determined as follows. In other words, in the overlap between the frame defined by the reference timing and the highway frame that handles high-speed calls,
Allocate time slots to accommodate high-speed calls. An example is shown in FIG. Highway 0 has a phase of +α with respect to the reference timing. Highway 1 is a reference timing, and highway 2 has a phase of 1 β with respect to the reference timing. The time slots that can accommodate high-speed calls at this time are the shaded areas. That is, regardless of whether it is within a highway or between highways, it is sufficient that one multi-block information does not straddle the shaded area and the shaded area before and after switching. Note that since this process is logical and variable, it is performed by the control circuit 18. In the configuration described above, the point to be particularly focused on is the time switch 20, and the present embodiment can be applied to any process that involves a delay. For example, a device such as a T1 stage concentrator has a two-panel configuration with time switches for up-highway and down-highway, respectively. In addition, although the phase difference between the human-powered highways is assumed to be l time slots, that is, an integer multiple of the fundamental element, in reality it is a fraction multiple of the fundamental element. Even if it is, it can be easily multiplied by an integer with a small capacity elastic store. (Effects of the Invention) As described above in detail, according to the present invention, even if there is a phase difference between the input and output highways of the time switch, a reference timing system for the time switch is provided, and the phase difference between the input and output highways is different from that of the reference timing system. Since a means for correcting is provided, it is possible to construct the time switch economically. In addition, when this method is applied to a time switch using a double buffer to perform multiple information exchange, the time slot accommodating a high-speed call is set at the portion where the frame according to the above reference timing system and the frame of each input/output highway overlap. Since a means for allocating information is provided, it is economical, and it becomes possible to exchange multiple information that can guarantee the preservation of time order within a frame.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing one embodiment of a time-division communication path according to the present invention. FIG. 2 is an explanatory diagram showing the operation when four input highways in the time switch are multiplexed. Fig. 3 is an explanatory diagram of the operation when two highways with a phase difference are multiplexed; Fig. 4 is an explanatory diagram of the operation showing write and read operations in multiple information exchange; , is an operation explanatory diagram of write and read operations in the present embodiment in multi-dimensional information exchange. Explanation of Main Parts ``'''' Time and Minute Open Channel Device Highway Switch Correction Circuit Control Memory Write Circuit Timing Circuit Control Circuit Time Switch Time Switch Memory Control Memory Embodiment of Time Division Channel FIG.

Claims (1)

[Claims] 1. In a time-division communication path connected to a highway having a phase difference and in which time-division exchange of information transmitted by the highway is performed in accordance with exchange information stored in a control memory, the communication The channel includes a timing signal generating means for outputting a timing signal serving as a reference in the time division exchange, and a phase correcting means for information transmitted with a phase different from the timing signal, and the phase correcting means is configured to adjust the time slot. A time division communication channel characterized in that the exchange information is sent to the control memory after the position correction is performed. 2. Time-division multiplexing in a time-division communication path connected to a highway having a phase difference and configured with a double buffer that performs time-division exchange of information transmitted by the highway in accordance with exchange information stored in a control memory. The information exchange device includes: a timing signal generating means for outputting a reference timing signal in the time division exchange; and a timing signal generating means for outputting a reference timing signal in the time division exchange; 1. A time division multiplex information exchange apparatus comprising: correction means for performing phase correction by performing phase correction; and control means for allocating a time slot accommodating a high-speed call to a portion that overlaps with a frame based on the timing signal.