JPH03203355A - Ultraviolet-erasable semiconductor device - Google Patents
Ultraviolet-erasable semiconductor deviceInfo
- Publication number
- JPH03203355A JPH03203355A JP1342822A JP34282289A JPH03203355A JP H03203355 A JPH03203355 A JP H03203355A JP 1342822 A JP1342822 A JP 1342822A JP 34282289 A JP34282289 A JP 34282289A JP H03203355 A JPH03203355 A JP H03203355A
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- chip
- resin
- transparent substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は紫外線消去型半導体装置（ＵＶＰＲＯＭ）に関
し、特に表面実装のできるＵＶＰＲＯＭの構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ultraviolet erasable semiconductor device (UVPROM), and more particularly to a structure of a UVPROM that can be surface mounted.
従来、この種のＵＶＰＲＯＭは、第３図に示すように放
熱板としてのアイランド３６上に固着されたＵＶＰＲＯ
Ｍチップ３２と金属外部リード３３とから或つ、チップ
３２のボンディングバットト金属リード３３をボンディ
ングワイヤ３４で接続し、これら全体を主にセラミック
により成形したパッケージにより封止していた。そして
、セラミックパッケージ３５には紫外線照射用の透過窓
３１が設けられている。Conventionally, this type of UV PROM has a UV PRO fixed on an island 36 as a heat sink, as shown in FIG.
The M chip 32 and the metal external leads 33 and the bonding butt metal leads 33 of the chip 32 were connected by bonding wires 34, and the whole was sealed with a package mainly made of ceramic. The ceramic package 35 is provided with a transmission window 31 for irradiating ultraviolet rays.
上述した従来のセラミックパッケージ型の半導体装置は
、厚さを決定する要因としてチップの厚さ、放熱板とな
るアイランドの厚さ、ポンティングワイヤのループの高
さ、セラミックパッケージの厚さがある。仮に樹脂封止
パッケージを用いれば、チップ厚さは０．４閣、アイラ
ンド厚さ０．４１、樹脂の厚さ１．ｏｍｍ（チップ上）
及び０．５ ｍｍ （チップ下）程度必要となり、全体
の厚さは２．３ ｍとなる（ボンディングワイヤのルー
プ高さを０．５−として樹脂厚さを１．０ｍｍとする）
セラミックパッケージの場合には、これ以上の厚さが必
要となる。さらに従来のパッケージは、デュアル・イン
・ライン型を採用しており、その外部リードはプリント
基板に垂直に伸延され、実装時には、パッケージ底面と
プリント基板間に隙が生じる構造となっていた。もし従
来以上に実装高さを減らすには、パッケージの厚さを減
小させねばならず、樹脂の場合には、吸湿によりチップ
表面への水分の侵入が起こりやすくなる。セラミックの
場合には成形限界１強度等の問題がある。従って耐湿性
強度が悪化するので厚さを減らすにも限度がある。The thickness of the conventional ceramic package type semiconductor device described above is determined by the thickness of the chip, the thickness of the island serving as a heat sink, the height of the loop of the ponting wire, and the thickness of the ceramic package. If a resin-sealed package is used, the chip thickness would be 0.4 mm, the island thickness would be 0.41 mm, and the resin thickness would be 1.5 mm. omm (on chip)
and 0.5 mm (under the chip), and the total thickness is 2.3 m (assuming the bonding wire loop height is 0.5-mm and the resin thickness is 1.0 mm).
In the case of a ceramic package, a thickness greater than this is required. Furthermore, conventional packages have adopted a dual-in-line type, with the external leads extending perpendicularly to the printed circuit board, creating a structure that creates a gap between the bottom of the package and the printed circuit board during mounting. If the mounting height is to be reduced more than before, the thickness of the package must be reduced, and in the case of resin, moisture tends to enter the chip surface due to moisture absorption. In the case of ceramics, there are problems such as a forming limit of 1 strength. Therefore, since the moisture resistance strength deteriorates, there is a limit to how much the thickness can be reduced.
本発明の目的は、装置の小型化に伴う、プリント基板等
への表面実装の要望を満たし、半導体装置自体の厚さも
低減したＵＶＰＲＯＭを提供することにある。An object of the present invention is to provide a UV PROM that satisfies the demand for surface mounting on a printed circuit board or the like as devices become smaller, and also reduces the thickness of the semiconductor device itself.
５課題を解決するための手段〕
本発明のＵＶＰＲＯＭは金属外部リードとメタライズを
備えた絶縁性透明基板と５この外部リードに続くメタラ
イズのボンディング部とバンプを介して接続される半導
体チップとを有し、透明基板のチップ接続側が樹脂によ
り封止されている。5. Means for Solving the Problems] The UVPROM of the present invention includes an insulating transparent substrate provided with metal external leads and metallization, and 5 a semiconductor chip connected to the bonding portion of the metallization following the external leads via bumps. However, the chip connection side of the transparent substrate is sealed with resin.
このような構成により、パッケージの厚さを透明基板の
チップ側封止樹脂の厚さだけで決定することができると
共に、外部リードをＳ字型に加工して樹脂底面にそろえ
ることにより、面実装が可能となる。With this configuration, the thickness of the package can be determined only by the thickness of the sealing resin on the chip side of the transparent substrate, and by processing the external leads into an S-shape and aligning them with the bottom of the resin, surface mounting is possible. becomes possible.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
第２図は本発明で用いるリードフレームである。FIG. 2 shows a lead frame used in the present invention.
絶縁性透明基板１主面には、ボンディング部２４を有す
るメタライズ（金属）層６が形成されており、このメタ
ライズ６の一端とリードフレーム２３の一端とはあらか
じめ固着させておく。A metallized (metal) layer 6 having a bonding portion 24 is formed on the main surface of the insulating transparent substrate 1, and one end of the metallized layer 6 and one end of the lead frame 23 are fixed in advance.
ＵＶＰＲＯＭチップ２のバンプ４とメタライズ層６のボ
ンディング部分２４を位置合せし熱圧着によって接着す
る。その後、封入金型内て透明基板１及びチップ２．リ
ードフレーム２３の一端を樹脂封止し、樹脂５をキュア
した後、リードフレーム２３を切り離し、外部リード３
部をＳ字状に成形加工する。The bumps 4 of the UVPROM chip 2 and the bonding portions 24 of the metallized layer 6 are aligned and bonded by thermocompression bonding. Thereafter, the transparent substrate 1 and the chip 2. After sealing one end of the lead frame 23 with resin and curing the resin 5, the lead frame 23 is separated and the external lead 3 is sealed.
The part is formed into an S-shape.
本実施例では基板厚さ０．４ｍｍ、チップ厚さ０．４ｍ
ｍ。In this example, the substrate thickness is 0.4 mm and the chip thickness is 0.4 m.
m.
バンプ高さ０．１ｍｍ、 リード厚さ０．４ ｍｍ
、樹脂厚さ０．５ｍｍで全体の厚さは１．８皿となり、
従来に比べ０．５Ｂ薄くなる。さらに、外部リードによ
る半導体装置とプリント基板間の隙をほとんどなくすこ
とができ、実装高さを大幅に低減することができる。Bump height 0.1mm, lead thickness 0.4mm
, with a resin thickness of 0.5 mm, the total thickness is 1.8 plates,
0.5B thinner than before. Furthermore, the gap between the semiconductor device and the printed circuit board due to external leads can be almost eliminated, and the mounting height can be significantly reduced.
二のような本実施例では、ＵＶＰＲＯＭにプログラムを
書き込んだ後、透明基板を通してチップに紫外線を照射
することにより、プログラムを消去することができる。In the second embodiment, after a program is written in the UV PROM, the program can be erased by irradiating the chip with ultraviolet light through the transparent substrate.
なお、本実施例では、半導体チップのバンプと外部リー
ドとの接続にメタライズ層を介在させたが、これは、透
明基板とチップ間に樹脂が介入することを防止するため
の一手段であって、他の方策が施されていれば、外部リ
ードとチップは直接接続してもよい。Note that in this example, a metallized layer was interposed between the bumps of the semiconductor chip and the external leads, but this is a means to prevent resin from intervening between the transparent substrate and the chip. , external leads and chips may be directly connected if other measures are taken.
また、本発明を通常の樹脂封止型半導体装置に適用する
こともでき、この場合には、透明基板は単に絶縁性基板
であればよく、さらにチップと外部リードも直接接続さ
れていても良いことは明らかである。Furthermore, the present invention can also be applied to ordinary resin-sealed semiconductor devices; in this case, the transparent substrate may simply be an insulating substrate, and the chip and external leads may also be directly connected. That is clear.
以上説明した様に本発明は、ボンディングワイヤを用い
ないことによりパッケージ厚さを従来より著しく薄くす
ることができると共に面実装が可能なＵ Ｖ Ｐ −Ｒ
ＯＭを実現できるものである。従って、実装体積を従来
より減小させ、セットの薄形化に役立つ。又従来ＵＶＰ
ＲＯＭは紫外線照射用の窓を持つため、セラミックパッ
ケージが主流であったが、本発明によれば、紫外線に透
過する基板を用いることにより、薄型樹脂封止ＵＶＰＲ
ＯＭを実現できる。As explained above, the present invention allows the package thickness to be made significantly thinner than the conventional one by not using bonding wires, and also enables surface mounting of the UVP-R.
It is possible to realize OM. Therefore, the mounting volume can be reduced compared to the conventional one, which helps in making the set thinner. Also conventional UVP
Since ROM has a window for ultraviolet irradiation, ceramic packages have been mainstream, but according to the present invention, by using a substrate that transmits ultraviolet rays, thin resin-sealed UVPR
OM can be realized.
第１図は本発明のＵＶＰＲＯＭ、第２図は本発明に用い
るリードフレーム、第３図は従来のセラミックパッケー
ジ型ＵＶＰＲＯＭである。
１・・・・・・絶縁性透過基板、２，３２・・曲ＵＶＰ
ＲＯＭチップ、３，３３・・・・・・外部リード、４・
・・・・・バンプ、５・・・・・・樹脂、６・・・・・
・メタライズ層、２３・・・・・・リードフレーム、２
４・・・・・・ボンディング部分、３１・・・・・・透
過窓、３４・・・・・・ボンディングワイヤ、３５・・
・・・・セラミックパッケージ。FIG. 1 shows a UVPROM of the present invention, FIG. 2 shows a lead frame used in the invention, and FIG. 3 shows a conventional ceramic package type UVPROM. 1... Insulating transparent substrate, 2, 32... Curved UVP
ROM chip, 3, 33...External lead, 4.
...Bump, 5...Resin, 6...
・Metallization layer, 23...Lead frame, 2
4...Bonding part, 31...Transmission window, 34...Bonding wire, 35...
...Ceramic package.
Claims (1)
部を有する金属層と、前記金属層が一主面に設けられた
透明基板と、前記透明基板の一主面に前記金属層のボン
ディング部を介して接続されたバンプを前記所定の位置
に配置した半導体チップと、前記透明基板の一主面の少
なくとも前記金属層と前記半導体チップとを被う樹脂と
を有し、前記金属外部リードが前記樹脂表面と略平行に
成形されていることを特徴とする紫外線消去型半導体装
置。a metal layer connected to a metal external lead and having a bonding portion at a predetermined position; a transparent substrate with the metal layer provided on one main surface; and a metal layer provided on one main surface of the transparent substrate through the bonding portion of the metal layer. a semiconductor chip having a bump connected thereto disposed at the predetermined position; and a resin covering at least the metal layer and the semiconductor chip on one main surface of the transparent substrate, and the metal external lead is connected to the resin. An ultraviolet ray erasable semiconductor device characterized by being formed substantially parallel to the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1342822A JPH03203355A (en) | 1989-12-29 | 1989-12-29 | Ultraviolet-erasable semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1342822A JPH03203355A (en) | 1989-12-29 | 1989-12-29 | Ultraviolet-erasable semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03203355A true JPH03203355A (en) | 1991-09-05 |
Family
ID=18356760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1342822A Pending JPH03203355A (en) | 1989-12-29 | 1989-12-29 | Ultraviolet-erasable semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03203355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100326834B1 (en) * | 1997-12-26 | 2002-05-09 | 가네꼬 히사시 | Wire-bonded semiconductor device and semiconductor package |
-
1989
- 1989-12-29 JP JP1342822A patent/JPH03203355A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100326834B1 (en) * | 1997-12-26 | 2002-05-09 | 가네꼬 히사시 | Wire-bonded semiconductor device and semiconductor package |
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