JPH03204219A - Cmos latch circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption of a latch by providing 2nd one- conduction and opposite conduction MOSFETs whose gates are connected to the output of a clocked inverter. CONSTITUTION:The latch circuit consists of a clocked inverter 13, an inverter 14 receiving the output of a latch, a P-channel MOSFET 15, an N-channel MOSFET 16 receiving the output of the inverter 14, and an N-channel and P-channel MOSFETs 17, 18 feeding back outputs of the MOSFETs 15, 16 to the output of the clocked inverter 13. Then the output of the clocked inverter 13 is connected to the gate of the MOSFETs 17, 18. Thus, the generation of collision of data inside of the latch is prevented at a change in the input data, and the current consumption is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a latch circuit for a large-scale integrated circuit.
In particular, it relates to a technique that is effective for shift registers and the like where data is frequently rewritten.

[Conventional technology]

An example of a conventional CMOS latch circuit is shown in FIG.

31 is an input data signal, 32 is a passage control signal, and 33 is a P
34 is an inverter that inverts the output of the clocked inverter and uses it as a latch output, 35 is the output of the clocked inverter from the output of the latch. This is an inverter that inverts and feeds back data to and holds it.

In this latch, when the signal 32 is high level, the input data signal 31 becomes the output of the latch via the clocked inverter 34 of 33, and when the pass control signal 32 becomes low level, the output of 33 is in a high impedance state. However, the data holding operation is performed by 34 to 35 inverters.

[Problem to be solved by the invention]

The conventional CMOS latch circuit described above has the following drawbacks when used in a place where the input data signal frequently changes from high level to low level or from low level to high level. When the input data signal 31 in FIG. 3 is held at a low level and the pass control signal 32 is set to a high level, the clocked inverter 33 outputs a high level. At this point, the 35 inverters are outputting the low level of the held value. Therefore, at the node 33, high level and low level data collide. At this time, if the input of the inverter 34 is at an intermediate potential, it will not operate as a latch, so the output impedance of the inverter 35 is set large. Due to this data collision, a through current flows between the clocked inverter 33 and the inverter 35. This through current flows until the output of the inverter 34 changes from high level to low level and the pressure of inverter 35 changes from low level to high level. Even if the held value and the input value are reversed, a through current is generated, resulting in an increase in current consumption.

[Means to solve the problem]

The CMOS latch circuit of the present invention includes a clocked inverter, an inverter whose input is the pressure of the clocked inverter, a gate of a first P-ch MOSFET whose source is connected to the output of the inverter, and a source thereof. input to the gate of the first N-ch MOSFET connected to GND, and the second N-ch MOSFET whose gate and drain are shorted to the drain terminal of the first P-ch MOSFET.
Connect the source terminal of ET to the first N-chM.

Connect the drain terminal of the 5FET and the source terminal of the second P-ch MOSFET whose gate and drain are shorted,
Second P-ch MOSFET and second N-ch MOSF
The drain of each ET is connected to the output of the clocked inverter.

Thus, in the circuit of the present invention, when input data changes, data collision does not occur inside the latch, and current consumption is small.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

11 is an input data signal to the latch, 12 is a pass control signal for the latch, 13 is a clocked inverter, 14 is an inverter that serves as the output of the latch, 15° and 16 are P-channels that receive the output of the 14 inverters as input, N-chMOSFE
T, 17.18 is the output of 15°16 MOSFET.
N-ch feedback to the output of clocked inverter 3
, P-ch MOSFET. 17.18 MOSF
The outputs of 13 clocked inverters are connected to the gates of the ETs.

12 passage control signal is high level (hereinafter abbreviated as "1")
When the input data signal 11 is at a low level (hereinafter abbreviated as 101), the clocked inverter 13 outputs 1'. The 14 inverters with this 1" input are °
Outputs 0'.

In this state, MOSFETs 17 and 15 become conductive, and output the °1' level, although it is one stage. In this state, when the signal of 12 is set to 0', the output of 13 becomes a high impedance state, but MOSFET17.15
Since 1' is outputted through , the output of 14 becomes "0" and the latch output "0" is held. At this time, 11
When the input data of 1 changes to the state of 111 and 12 becomes Ill, the clocked inverter of 13 outputs "Ol". This 0' makes the 170M08FET non-conducting. At this point, the 160M0 S FET becomes non-conducting. Due to conduction, no through current occurs.

In response to 13's 0'', 14 inverter outputs 1',
MOSFET 16 becomes conductive, and M of 16 and 18
The OSFET outputs 0' to 13 nodes. Here, we have explained the case where the input data signal changes from 0゛→11+, but even when the input data signal changes from 1゛→“O1, 18 MOS
Since the FET immediately becomes non-conductive due to a change in the output of the clocked inverter 13, no through current occurs. The problem here is that the potential for data retention by the MO5FET of 17.18 is one level lower. The 13 clocked inverters output high level and low level power supply voltage and GND voltage respectively, but 1
7.18 MOSFET's output drops by one step, so a small leak occurs, but in applications where input data changes frequently due to high speed or locking, there is no through current due to data collision inside the latch as in the conventional example. is larger, so it is not a problem.

FIG. 2 shows another embodiment, in which the initialization MOSFE
T is added.

〔Effect of the invention〕

As described above, the CMOS latch circuit of the present invention can prevent through current due to data collision inside the latch caused by changes in input data, and therefore has the effect of reducing current consumption of the latch.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention. 11...Input data signal, 12...Latch passage control signal, 13...Clocked inverter output, 14...Inverter serving as latch output, 15゜18-P-ch MOSFET, 16.1
7-----.N-ch MOSFET FIG. 2 shows a second embodiment of the present invention. 21...Input data signal, 22...Latch passage control signal, 23...Clocked inverter output, 24...Inverter serving as latch output, 25゜28-P-ch MOSFET, 26,2
7,2A...N-ch MOSFET, 29...
...Latch initialization signal FIG. 3 shows a conventional example of a CMOS latch circuit. 31...Input data signal, 32...Latch passing control signal, 33...Clocked inverter output, 34.35...Inverter.

Claims (1)

[Claims] A clocked inverter, an inverter that receives the output of the clocked inverter as an input, a first one conductivity type MOSFET whose gate receives the output of the same inverter, a first opposite conductivity type MOSFET, and a connection between these MOSFETs. a second monoconductivity type MOSFET and a second opposite conductivity type MOSFET whose gates and drains are short-circuited and whose gates are connected to the output of the clocked inverter; A CMOS latch circuit having.