JPH0320517U - - Google Patents
Info
- Publication number
- JPH0320517U JPH0320517U JP3972389U JP3972389U JPH0320517U JP H0320517 U JPH0320517 U JP H0320517U JP 3972389 U JP3972389 U JP 3972389U JP 3972389 U JP3972389 U JP 3972389U JP H0320517 U JPH0320517 U JP H0320517U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- arbitrary waveform
- input terminal
- generator
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tests Of Electronic Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案で用いる任意波形発生装置の一
実施例を示すブロツク図、第２図は本考案の一実
施例を示す接続図、第３図は従来の装置の一例を
示すブロツク図、第４図は第３図の装置を並列運
転する場合の一例を示す接続図である。
１，２……パターン発生器、３，４……Ｄ／Ａ
変換器、５……クロツク発生器、６……スイツチ
、７……クロツク制御回路、８，１２……入力端
子、９，１１……出力端子、１３……分配器、１
４〜１６……ケーブル、Ｍ……マスタ装置、Ｓ…
…スレーブ装置。
FIG. 1 is a block diagram showing an embodiment of an arbitrary waveform generator used in the present invention, FIG. 2 is a connection diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional device. FIG. 4 is a connection diagram showing an example of parallel operation of the apparatus shown in FIG. 3. 1, 2...Pattern generator, 3, 4...D/A
Converter, 5...Clock generator, 6...Switch, 7...Clock control circuit, 8, 12...Input terminal, 9, 11...Output terminal, 13...Distributor, 1
4 to 16...cable, M...master device, S...
...Slave device.
Claims (1)
る任意波形データをＤ／Ａ変換器に加えてアナロ
グ信号に変換する波形発生系統と、この波形発生
系統に加えられるクロツクが入力される入力端子
と、内部で発生されるクロツクまたは外部から加
えられるクロツクをスタート信号とストツプ信号
により設定される一定の期間だけ出力するクロツ
ク制御回路と、このクロツク制御回路から出力さ
れるクロツクを外部に取り出す出力端子を具備す
る複数の任意波形発生装置で構成され、 マスタ任意波形発生装置のクロツク出力端子と
マスタ任意波形発生装置のクロツク入力端子およ
びスレーブ任意波形発生装置のクロツク入力端子
がそれぞれ長さの等しいケーブルで接続されたこ
とを特徴とする任意波形発生装置の並列運転接続
構造。[Claims for Utility Model Registration] A waveform generation system that converts arbitrary waveform data output from a pattern generator into an analog signal by adding it to a D/A converter according to a clock, and a clock added to this waveform generation system. An input terminal, a clock control circuit that outputs an internally generated clock or an externally applied clock for a certain period of time set by a start signal and a stop signal, and a clock output from this clock control circuit. The clock output terminal of the master arbitrary waveform generator, the clock input terminal of the master arbitrary waveform generator, and the clock input terminal of the slave arbitrary waveform generator are each long. A parallel operation connection structure for arbitrary waveform generators, characterized in that they are connected by cables of equal length.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3972389U JPH0320517U (en) | 1989-04-04 | 1989-04-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3972389U JPH0320517U (en) | 1989-04-04 | 1989-04-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320517U true JPH0320517U (en) | 1991-02-28 |
Family
ID=31548885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3972389U Pending JPH0320517U (en) | 1989-04-04 | 1989-04-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320517U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61246684A (en) * | 1985-04-24 | 1986-11-01 | Furuno Electric Co Ltd | Generator for desired frequency signal |
-
1989
- 1989-04-04 JP JP3972389U patent/JPH0320517U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61246684A (en) * | 1985-04-24 | 1986-11-01 | Furuno Electric Co Ltd | Generator for desired frequency signal |
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