JPH0320539U - - Google Patents
Info
- Publication number
- JPH0320539U JPH0320539U JP7900189U JP7900189U JPH0320539U JP H0320539 U JPH0320539 U JP H0320539U JP 7900189 U JP7900189 U JP 7900189U JP 7900189 U JP7900189 U JP 7900189U JP H0320539 U JPH0320539 U JP H0320539U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- mos
- clock signals
- fets
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の同期式フリツプフロツプ回路
の一実施例の回路図、第２図は第１図の論理回路
の真理値の説明図、第３図は第１図の同期式フリ
ツプフロツプ回路の動作図、第４図は本考案の同
期式フリツプフロツプ回路の別の実施例の回路図
、第５図は従来の同期式フリツプフロツプ回路の
一例の回路図、第６図は第５図の同期式フリツプ
フロツプ回路の動作図である。
４０……論理回路、５１，５２……ＭＯＳ・Ｆ
ＥＴ、ＣＬＫＯ，……クロツク信号、Ｃ
ＬＫＩ，……ゲート制御信号、Ｉ……入
力信号、Ｏ……出力信号（出力状態）。
Fig. 1 is a circuit diagram of an embodiment of the synchronous flip-flop circuit of the present invention, Fig. 2 is an explanatory diagram of the truth value of the logic circuit of Fig. 1, and Fig. 3 is the operation of the synchronous flip-flop circuit of Fig. 1. 4 is a circuit diagram of another embodiment of the synchronous flip-flop circuit of the present invention, FIG. 5 is a circuit diagram of an example of the conventional synchronous flip-flop circuit, and FIG. 6 is the synchronous flip-flop circuit of FIG. FIG. 40...Logic circuit, 51, 52...MOS/F
ET, CLKO, ... clock signal, C
LKI,...Gate control signal, I...Input signal, O...Output signal (output state).
Claims (1)
、これらＭＯＳ・ＦＥＴが入力信号とは別に加え
られる互いに補なる論理状態の一対のクロツク信
号によりスイツチング動作をし、それらの開閉に
同期して出力状態が切り換わる同期式フリツブフ
ロツプ回路において、 前記一対のクロツク信号と一対のＭＯＳ・ＦＥ
Ｔのゲートとの間に、これら一対のクロツク信号
を受け、それらに基づいて一対のゲート制御信号
を作つて、前記一対のＭＯＳ・ＦＥＴのゲートに
それぞれ与える論理回路を設け、前記一対のクロ
ツク信号が互いに補なる論理状態をとる期間はこ
れらのクロツク信号の論理状態にそれぞれ応じた
一対のゲート制御信号を、一対のクロツク信号が
その論理状態の変化のずれによつて、共に同じ論
理状態をとる期間は前記一対のＭＯＳ・ＦＥＴを
双方とも開制御する一対のゲート制御信号をそれ
ぞれ作るように前記論理回路が構成されたことを
特徴とする同期式フリツプフロツプ回路。[Claims for Utility Model Registration] A pair of MOS/FETs connected in series is provided, and these MOS/FETs perform a switching operation by a pair of clock signals with mutually complementary logic states that are added separately from the input signal. In a synchronous flip-flop circuit whose output state is switched in synchronization with the opening and closing of the clock signal, the pair of clock signals and the pair of MOS/FE
A logic circuit is provided between the gate of the transistor T and the gate of the MOS/FET, which receives the pair of clock signals, generates a pair of gate control signals based on them, and applies them to the gates of the pair of MOS/FETs, respectively. During the period in which the clock signals take complementary logic states, a pair of gate control signals corresponding to the logic states of these clock signals are activated. A synchronous flip-flop circuit characterized in that the logic circuit is configured to generate a pair of gate control signals for controlling both of the pair of MOS/FETs to open during a period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7900189U JPH0320539U (en) | 1989-07-04 | 1989-07-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7900189U JPH0320539U (en) | 1989-07-04 | 1989-07-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0320539U true JPH0320539U (en) | 1991-02-28 |
Family
ID=31622773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7900189U Pending JPH0320539U (en) | 1989-07-04 | 1989-07-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0320539U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07127510A (en) * | 1993-10-29 | 1995-05-16 | Hanshin Electric Co Ltd | Fuel cut-off device for diesel engine |
| JP2006165687A (en) * | 2004-12-02 | 2006-06-22 | Onkyo Corp | Switching amplifier |
-
1989
- 1989-07-04 JP JP7900189U patent/JPH0320539U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07127510A (en) * | 1993-10-29 | 1995-05-16 | Hanshin Electric Co Ltd | Fuel cut-off device for diesel engine |
| JP2006165687A (en) * | 2004-12-02 | 2006-06-22 | Onkyo Corp | Switching amplifier |
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