JPH03205661A - Alternative processing method and data recording/reproducing device - Google Patents

Abstract

PURPOSE:To rationally discriminate a defective area and to improve the reliability of data by discriminating a defect of a recording area with the presence or absence of error correction by an error correcting code. CONSTITUTION:At the time of reproducing a data, a data error in the lateral direction is corrected with a C1 code in a sector format and a data error in the logitudinal direction with a C2 code respectively by an ECC control circuit 2, and if a data error by the C2 code is present even in one frame, a C2 error detecting signal is outputted to a control processor 5. Then, when there is an error in a sector data after error correction, a CRC error detecting signal is outputted to the control processor 5. The data after recording this data is reproduced by the control processor 5, and when an error is detected by the CRC error detecting signal or the C2 error detecting signal, the recorded data in its sector is transferred and recorded to an alternate sector. By this method, the defect is discriminated at a low error rate, thus improving the reliability of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION [J1 Field of Application] The present invention relates to an alternate sector processing method in a recording medium K such as a disk, and a data recording/reproducing device using the method.
Take a bite. [Jubei technology] For example, a data recording and reproducing iron equipment that records and reproduces data using a recording medium such as an optical disk, uses four types of data.
In order to improve the 1i reliability '4I:pl, the following two methods have been considered.

One method is to correct errors using error correction codes (ECC) depending on the situation, and to suppress the occurrence of errors, and the other method is to find defective regions of the Ik rope body. , If there is a defect, data is recorded in place of another defective area, which is a so-called replacement block method.

Among these, regarding the replacement processing method, for example, special 1! Showa 6
Publication No. 2-46468, JP-A-62-154
Publication No. 572, Publication No. 58764, etc. are exaggerated. Replacement by these conventional techniques @I! The 7F method compares the recorded data with the reproduced data after error correction and refilling, and if a discrepancy occurs, the data is replayed! jLll! This method re-compares the recorded data with the reproduced data after error correction processing, determines whether the error is in the data at the same myyr, and determines that it is defective if the error is in the data at the same location. ．． In addition, other replacement processing methods based on conventional technology compare recorded data with reproduced data without error correction. This is a method that determines a defect when the number of discrepant data is greater than or equal to a constant. [A problem that MFj is trying to solve] However, in the conventional technology, since the determination of defects in the recording medium during replacement processing is based on the comparison of recorded data and reproduced data one by one, it requires a large number of processing steps. There was a problem that it took W time.

In addition, in the above conventional technology, when comparing recorded data and reproduced data, since the reproduced data is the data that has been corrected by a powerful error correction function, there are many defects that can be corrected, such as ECC. Defects caused by the eel work will have to be overlooked, and the recording section will deteriorate due to changes in the eel season, etc., and the classification of the Shin area, where the Homare tomb is a must, cannot be done correctly, and the data will be lost. am
It was a contributing factor to the decline in sexuality.

The purpose of the present invention is to solve the above-mentioned problems and to
With κ, it is easy to identify defects in the recording medium, and there are no defects in the recording medium. It is an object of the present invention to provide a data recording and reproducing device and an alternating storage system that improves the IN-axis property of data by making a judgment on a case-by-case basis.

(Measures for deciding whether or not to make a decision)
One of the plurality of divided recording areas provided is St', and at least data with an error correction code added to the recording area used as a reserve area is recorded in the St' recording area, and data recorded at the station is recorded. Play it. In Matabetsu Rebuild method #C, defects in the recording area where the data is recorded are classified into 4ItI, and when it is determined that a defect exists, the grade data is transferred and recorded in the upper grade storage area. Defects in the record submission are determined based on the presence or absence of error correction using the correction code.

In other words, if there is a correction using the above-mentioned 9 correction code, the above-mentioned
I try to do Kaede.

To do this, for example, if there is an error correction using the above-mentioned error correction code, an error 41I output g1 indicating the error Ii' is outputted, and thereby the defect can be determined in the above-mentioned recording area. I'm going to do a 5K.

Furthermore, the present invention provides a method for recording and reproducing data in a recording medium in which one of a plurality of divided recording areas, which is determined based on the recording strategy, is used as a backup area. and an error correction means that generates at least an error correction code and adds it to the station data when recording data, and uses the error correction code when playing back the data to correct errors in the data; At the time of data creation, the missing M in the Ie record area of the sales data record is sorted, and if it is determined that there is a defect, the above reserve area K station data is transferred and the correspondence processing is carried out. Data recording and reproducing device 1lIL equipped with Kaede
In #c, the determination of defects in the recording area by the Joki Matabetsu Kofuntehi is performed based on the presence or absence of error correction by the error correction code of the error correction code.

If the upper era error correction code is a horizontal code formed from the two signs -jjK, then the error correction code of the person who performs the correction will be able to correct the defects in the recording area by publication. It is preferable to do so. The error correction means outputs information tl--indicating whether or not errors have been corrected by the error correction code. It is preferable to have &.

[Effect]

The distributed data is reproduced to determine whether or not there is a defect in the recording area where the data is recorded, and if it is determined that there is a defect, a predetermined reserve for the data recording area is determined. In the honor process of transferring and recording sales data in the area, the recorded data is played back wPK. The presence or absence of error correction using W49 correction code is determined by publication, and if there is % error correction, it is 4ll.
If IJ is separated, the data recording reserve area is assumed to be defective, and the recording data is rewritten and recorded in the reserve area.

As a result, the replacement processing time is shortened, and defects in the recording area can also be determined at a lower execution rate than when the ratio of recorded data and reproduced data after error correction is IRK. can.

[Actual example]

Embodiments of the present invention will be described below with reference to the drawings.

First, we will discuss an example of the overall structure of a data recording and reproducing device that is widely used in all types of data recording and reproducing devices.

Figure lI2 shows the overall structure of the data recording/reproducing arrangement used in the optical disc of this embodiment. In the IL2 diagram, 1 is the outer interface 7 ace control circuit that handles data exchange with the rear external combiator, and 2 is the data error allocation I111-row 5ECC@@curve %5 is the data RIIIll and return leg. 4 is a synchronized reproduction (auto) path that reproduces IWi period signals such as Kukuk from the pre-recorded synchronization patterns on the Yu disk 10K,
5 is dry 1 system ▲The whole sacred control control Ω
Setsuna, 6 is the try king I4l Goichiro who controls the yun disk 10015y king, 7 is the mome that turns the yun disk 10? Seigeki Ochoru servo circuit, 8 is the data access road, 9 is the motor, and 1Ω is the optical disk.
l! FIG. 5 shows the 1Ω sector structure of the disk used in the data recording/reproducing system shown in &2-.

In the S diagram, the sector for 1 tract of 9 disks 1Ω and the fit of the honorary sector area for sector defects are shown.
The indicated *1}-yy/K is provided with 52 sectors, and for every 4 sectors (128 sectors), 7 sectors of %1 are allocated as an alternate sector area.

4 is a conceptual diagram showing an example of the sector format of data recorded on the disc 10. FIG.

In the 41st KN, for 1 sector (524 bytes) of data, 4 bytes of CRC (Cy
clic Redundancy Check) and
E C C (Erro
r (:orrgctixg Cods) or matrix-like KtI? ．． Allocated in rows. here,
In the ECC, 4 bytes of C1 code are arranged for 44 bytes of data in the horizontal direction, and 2 fins of C2 codes are arranged for 12 lines of data in the vertical direction. The arrows in the diagram indicate the order of the wishes of both Iken and Haichi for data transfer and recording/reproduction.

Using these drawings, we will briefly explain the data recording device of this example. I will explain. When recording data on the F4 screen 1, the data to be recorded must be divided into am sectors and transferred to the external interface 7 ace. Transfer to 1. The external interface IIIl@circuit 1 performs data bypassing in order to match the data transferred from the external combination island to the access speed of the 1Ω disk, and performs data bypassing to match the access speed of the 1Ω disk. The sector unit K% data is output as ECC@control M2K.

ECCml times N2kg, external fib{yjl7z-st
For the data in sector units output from lmll-ro 1, as shown in the sector format in Figure 4, CR
Generate and append C and ECC, CRC and ECC
The added sector data is output to the variable mu path SK.

The variable S is rewarded with the data output from the ECC control path 2, the optical task 10K memorization bit pattern, and the data access circuit 8Km power regeneration Prl period reproduction 1i [4 is, From the synchronization pattern etc. recorded in advance on the disk 10, the data transfer query/'! 'Sector synchronization gI, etc. Nishikan Yugo holy regeneration, external ink 7
z - ,X (j7ro1, ACCI11laJ
After the times Wft2-J6 YohiR, output those synchronization value numbers to wa and route 5. In addition, the control circuit c1 controller 5 controls data transfer, access to a specified track, etc., and the trying control circuit 6 controls access to a specific track according to instructions from the control 7a set t5. Like, tracking 1! The signal is output to the servo mt+iit+path 7. The servo control w17 controls the rotation fE of the motor 9 so that the finger/toe track of the 1Ω disk can be accessed by this tracking number gI. Therefore, the data access path 8 loads the bit pattern changed in the i path path ink onto the accessed end track of the optical disc 1o.

On the other hand, when reproducing data V from the disk 10, F
The IJ91 reproducing circuit 4, tracking control circuit 6, and servo control circuit 817 perform the same operations as when recording data, and access the main tracks of the nine disks.

Data access excitation path 8 is connected to the accessed disk 1Ω.
From the track of t'wr. and output to modulation/demodulation circuit 5.
The modulation/decoding m circuit S demodulates the bit pattern consisting of this sector unit {II, reproduces the data before Hendo, and outputs it to ECC@Misonoji 2. Ru.

The ECCmiie circuit 2 performs the CRC with the sector rate Kff21El as shown in the sector 7 format of Tame 4-.
and ECC, it corrects the error in the sector data K, detects the error, and when transmitting the Sotsuru interface control 111K sector data, the error compensation error is detected in the K% control C sensor 5 at the time of fjJ. Output. The external ink 7 ace control excitation path 1 transfers the data transferred from the ECCM route 2 to @IIC,
Bad 7 ring. @') If the detected decoding code is transmitted and the sector/KWA is not present, control a-loop a-senna 5 is set, the foreign cooperation combination island is heard, and the escape 3! ! Transfer data according to the distribution. Also, if the error detection W signal is transferred and there is an error in the sector data, the control Q
If Sedena 5 is established, in addition to transferring the data, we will send a message to the Sotome Combi Bokuichita about the #cPk specific work 21 occurrence. The above is the outline of the operation of the data recording and reproducing Rikjiji shown in Figure 2. Next, the detailed configuration and operation of the WIP for E C C @174 1 route 2κ shown in Fig. 312 will be explained using Fig. 1.

Figure 1 is a diagram showing the kite structure of the ECC Liu control circuit 2. tIi&1 r/jACJa ite, 201 G:! ,
ECC calculation EQfl) (1) ECC that generates a
This is the path to the occurrence of arithmetic blocks. 202 is a sector memory 421! that records sector data. and an address kakunta that generates the address (XM) of the sector 7 format horizontally to be supplied to the sector memory B214, and is a 2D
J! is sector 7 format vertical address CYNk
llA). 204 counts the data transfer clock 21 and supplies address CX-Ylkm) and sector period J! to sector memory j21M and sector memory B 214K. This is a data transfer kakunta that generates No. III. 2Ω5 is EC
C operation switching m@circuit, 206 is address interary 1
It is a circuit.

Reference numeral 207 denotes a 7-1-7 input which inputs the sector cycle signal output from the data transfer circuit 2-4 and outputs a sector switching polarization code that changes by toggle for each sector. 208 16 and 20? is an address switching circuit. 21Ω is a data buffer circuit, and 211 and 212 are data switching circuits. These are sector memory A and sector memory B, which store the coming sector data. 215 is the data p bus
'& le. Reference numeral 216 denotes an ECCyL nose circuit which takes in 7-ray data transferred in 7-ray units #C and generates error correction data by ECCM or ECCIIC by calculation. 217 is a line 5 CRC @ control path that generates a CRC and detects errors in sector data using the CRC. 218 is a C2 error detection circuit that detects errors caused by the C2 code from the error correction data output from the ECC calculation circuit 216 and generates a C2 error detection bias code 24. That's all 5 1p! In the ECC@Oryariro 2k consisting of
No. I is generated. 7 rip 7Qνp2Ω7 generates the sector cut II command number JA that changes by toggle in the sector cycle from this sector ayaseki number, and by this sector cut ** number, the address cut Il & Sonoji 208, 20? and data switching circuits 211 and 212, respectively. 10,000, address counter 2 (12 and 205 series of kakunta) is a predetermined ECC operation so that the ECC operation of the sector data is completed within one sector period of data transfer.
Clock OF of output of CC calculation block generated cell #111201
Count the number of ECC operations until the specified number of times is reached. That is, the address counter 202 generates an address corresponding to the C1 code direction of the seven-point format shown in Figure 4, and the address counter 20s generates an address corresponding to the C2 code. The ECC calculation fl conversion circuit 205 includes an address counter 20
Using the address that is the output of 2 and 205, ECC
Switching between C1 operation (Ct code generation operation or error correction operation using C1 code) and C2 operation (C2 code generation operation or error correction operation using C2 code) is performed in line 5C1.
/C2 operation off 11 {I outputs N206K times of address interleaving ``j''.

The address interleague circuit 2ro 6 is this 01/c'2
The address output from the address kakunme 202 and the address output from the address counter 20& are exchanged by the arithmetic switching polarization. When performing a C1 operation, the address is increased in the horizontal direction, and when performing an 02 operation, the address is increased in the vertical direction, and so on. Output to.

The address switching circuit 20B and 2Ω9 are connected to the address supplied from the address inter-1 circuit 206, the address supplied from the data transfer circuit 2[14], and the sector cut-off signal supplied from the 7-lip 7ay circuit 207. The address switched by the address switching circuit 208 is switched to the sector memory A 215 K, address switched! 1 circuit 2
Sector memo 9 B 214 for the address switched in 09
K, respectively, supply. The address switching circuits 208 and 209 switch the address switching circuits 208 and 209 so that the sector memory A 215K receives the address supplied from the data transfer counter 204 and the sector memory B 214K receives the address supplied from the address interleaving 1 circuit 206 in a sector period. the address to be
Each of them operates to supply, and the next cycle K is vice versa, #c, and they switch each other to supply 5K11.
Make J. The data switching channels 211 and 212 transmit data 22 via the data port ν7a 21b and data transfer data 21s via the data port ν7a 21b.
The calculation data from the ECCyi arithmetic circuit @ 216 via t is switched by the sector switching decoder supplied from the 7-lip 7o-p 207, and the data switching excitation path 211 is connected to the data input/output sK of the sector memory A21&. Switching cell tract 21
2 is inputted to the data input/output S of the sector memory B214 by 1ikIjk, respectively. These data switching circuits 211 and 212 also have address switching circuits 2Ω8 and 2Ω? and Pl4i1 K, sector period, data transfer mass and EC
C calculation processing is alternately switched.

That is, in a certain sector period, the sector memory A215
The data input/output unit performs input/output of the ii sending data 22, and the data input/output 1 of the sector memory B 214 performs input/output by ECC calculation, and vice versa in the next sector cycle. Chivalrous.

The ECCyL arithmetic circuit 216 is an Ijl2I circuit that performs ECC generation (during recording) and error correction using ECCK (during reproduction) based on the frame data read from the sector memory A 21S or sector memory B 214. The ECC calculation process is as shown in Figure 5 (,4) K, C1
There are calculations for the horizontal frame of the sector format using the code, and calculation of the vertical 7-ray ▲ of the sector 7 format using the K%C2 code as shown in sW(#).
I calculation escape monkey K (1'2 calculation processing is performed. Therefore, the error correction during playback is horizontal error correction by C1 code @
K. Error correction is performed using the C2 code, and if an error is detected using the C2 code or occurs in that frame, a C2 frame ▲g1 No. 25 is output.

CRC@@@Route 217 is as shown in Figure 5 (CC),
When storing data on the optical disk 10, a CRC is generated from the sector data before ECC generation, and the generated CRC
is sector memory A21 & and sector memory B214
Transfer to. In addition, when reproducing data from the disk 10, the CRC code is used to process the ECC calculation.
Detect data errors in the sector data of
If there is an error, convert the CRC error detection decoding 2s
- File processor outputs 5K. The C2 error detection circuit 218 indicates that the ECC calculation circuit 216
When performing error correction using C2 code in the CC processing unit,
The C2 frame error code 25 that detects and outputs errors in each frame data of the C2 code is K1 in the sector.
If there are more than one frame, C2 error detection {II! 2a is generated and output to the control a setter 5.

The above is a detailed explanation of the operation of the ECCiIII@circuit 2.

Next, upon receiving the output from ECC division # circuit 2, control a
- Aq regarding the replacement processing method of this example performed by the file processor 5.

Figure 6 is a processing flowchart of the replacement process. When data is recorded on the optical disk 10, the control a-roup a setter 5 records the original data and records the reproduced data. Verify (ii) and verify 7 i W.
If the result is defective, the data is transferred and recorded in the replacement sector area as shown in the diagram. As mentioned above, during data reproduction, the ECC allocation circuit 2 detects data errors in the horizontal direction by the C1 code and data errors in the vertical direction by the C2 code in the sector format shown in the $S diagram. , corrected, and if a data error due to C2 code exists even in 17th ray ▲, C2 error detection fault signal 2
4 to the controller set tS, and also outputs the CRC
Therefore, if there is an error in the sector data for which error correction is required, the CRC error detection signal 2S'9t controller 5K is output.

Control a-loop a7t5 is data record lk* @6
As shown in the figure 7a-chart, reproduce the data,
CRC error detection polarization 25 or C2 error sideways {! No. 24
detects an error, the recorded data of that sector is
The data is transferred to a replacement sector storage area and recorded. It should be noted that this recorded data is also verified again, and when a data error due to the C2 code is detected, it is rewritten to the next replacement sector area, and so on, and the replacement process is repeatedly performed.

From this, %wk1k is missing when comparing the recorded data and the reproduced data as before! Compared to the method of determining defects by tl, the method of determining defects based on the CRC error detection signal 25 and the C2 error detection a & polarization code 24K can significantly shorten the processing time.

Figure 7 shows CRC error detection code 2s and C2 error detection {Ir
24 is an i4lgk diagram showing the relationship between the combinations of states No. 24 and the presence or absence of replacement processing in each combination. FIG.

In addition, Fig. 8 is an RA4LK diagram showing the relationship between the respective defects shown in Fig. 7 and the data error rate. In Fig. 8, the vertical axis is the error rate, and the correction by C1 code and The level at which errors are corrected by both code correction (C1a(:'2)ki is indicated by a dotted line, and
Level at which errors are corrected only by correction using C1 code (C
1) is shown using broken koji.

Since the CRC1@redetection command code 2s is the error detection result of the sector data of (2) that has undergone error correction using the %C1 code and error correction using the C2 code, the CRC shown in ■ in Figure 7 is
The error state is as shown in FIG.
The error correction level of both of the two codes is higher than the error correction level of the two codes. In addition, in the state marked ■ in Figure 7, the error rate is lower than the error correction level of both the CI code and the C2 code, but the error correction level is corrected only by the C1 code. In addition, the error rate of Ji7a, which has no errors in both the CRC and the C2 code, is at a lower level than the level at which errors can be corrected using only the C1 code. The situation of ■ in i47k, where it is determined that there is no error due to the C2 code, does not exist in theory.

The replacement process is performed when an error is detected by the C2 code, as shown in ■ and ■ in FIG. 7, so the error is detected by the CRC! Compared to the case of [Yes] in Figure 7, where the error rate is low, it will be classified as a defect, and there will be more margin for the deterioration of the medium due to the aging rate, and the gI of the data will increase. Personality improves.

As described above, in this embodiment, defects can be immediately identified by 4tl in the replacement process using the error detection value signal based on the C2 code, so that the number of defects is greatly reduced to Wa&. In addition, since defects are detected using C2 codes rather than CRC error detection based on error correction using C1 and C2 codes, defects can be detected at a low processing rate, improving the AM characteristics of data. .

In this actual Mfl, we have described the correction using the C1 code and the correction using the c2 code for row 5J111, but 2l! The effectiveness is the same even if the method uses the above-mentioned principle and determines defects by error correction and detection using C1 codes.

In addition, in this embodiment, if the error correction and detection by the C2 code is 17 rays or more, it is determined as a defect. It is also possible to use K to determine that this is a defect. Furthermore, in this example, a horizontal code consisting of a CI code and a C2 code is used, but a long-distance code (Log Dis
tance Cods). [Effects of the invention] That's all I1! As explained above, according to the present invention, there are 4Il! defects in the recording area in the replacement mass. The difference is that the recorded data is not compared with the reproduced data after error correction, but is determined based on the presence or absence of error correction during reproduction, so processing can be significantly shortened, and the I &
This has the effect of shortening the time spent on the site.

Also, how to determine defects? ! Because this is done based on the presence or absence of error correction at the time of raw recording, it is possible to distinguish between publications at a lower rate compared to the comparison between recorded data and reproduced data after error correction. 5JtJ-jI! :There is,

[Brief explanation of drawings]

Figure 1 shows the detailed structure of the ECC @Misonoji for data recording and reproduction using an optical disk according to the present invention. Figure 1 shows the overall structure of the data recording and reproducing device; A conceptual diagram showing an example of the sector 7 format, Figure 5 shows the direction of each calculation frame in the sector 7 format. The light figure and Tame 6 figure show the missing part 7a- of the replacement process.
The chart, Figure 7, is a relational diagram showing the relationship between the combination of the states of the CRC error detection defect signal and the C2@ri detection defect signal, and the presence or absence of replacement processing in the 4r combination, and Figure 8 shows the relationship shown in Figure 7. FIG. 3 is a relationship diagram showing the relationship between book condition and data error rate. 1-Foreign interface control circuit 2.1 ECC @ control circuit S-R recovery III 1 circuit 4.1 synchronous regeneration circuit 5-j-control a processor 6.1-tracking control circuit 7-t-e control circuit 8-Data access circuit 9
-Mo7 1019 disk 21-Data transfer link 22-1i transmission f-123-CRC error detection signal 24-Cl error horizontal a & polarization 25-C27 ray ▲
Error decoding 201 - ECC calculation a y / 'A raw a jl
l202 * 20J$ ”-address kakunta 2Ω4
・-Data transfer kakunta 205--ECC operation switching control 206--Address interface three 1 circuit 207-
7 rip 7a rip 208 . 209--address switching excitation path 210--data bus circuit 211, 212--data switching path 215, 214--sector memory 215--data path buffer circuit 216--ECC calculation circuit 217-CRC@control QM 21B-CRC Error Yokode Ichiro Tsuyoshi Figure 1 2 Figure 1n Figure 5 Punishment 4 Figure Power 5 (A) Figure ¥55 (8) Funeral Figure 5 (C) Figure 6

Claims (1)

[Claims] 1. For a recording medium in which a part of a plurality of divided recording areas provided on the recording medium is used as a spare area,
Data to which at least an error correction code has been added is recorded in the recording area, the recorded data is reproduced, and a defect in the recording area in which the data is recorded is determined, and if it is determined that a defect exists, the above-mentioned A replacement processing method in which the data is transferred and recorded in a spare area, characterized in that defects in the recording area are determined based on the presence or absence of error correction using the error correction code. 2. For a recording medium that uses part of a plurality of divided recording areas provided on the recording medium as a spare area,
a recording/reproducing means for recording and reproducing data in the recording area, generating at least an error correction code and adding it to the data when recording data, and using the error correction code when reproducing the data to correct errors in the data; an error correction means for correcting the data; and a replacement processing means for determining a defect in the recording area in which the data is recorded during data recording, and transferring and recording the data in the spare area when it is determined that there is a defect. In the data recording and reproducing apparatus, the replacement processing means determines whether there is a defect in the recording area,
A data recording/reproducing apparatus characterized in that the error correction is performed depending on whether or not errors are corrected by the error correction code of the error correction means. 3. When the error correction code is a product code composed of two codes, the defect in the recording area is determined based on the presence or absence of error correction by the code that performs the correction last. The alternation processing method according to claim 1 or the data recording and reproducing apparatus according to claim 2. 4. The data recording and reproducing apparatus according to claim 2, wherein the error correction means includes means for outputting information indicating whether or not errors are corrected by the error correction code.