JPH0320682A - Inspection device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable prevention of extension of measuring time by providing a bypass capacitor for preventing oscillation with an opening/closing means. CONSTITUTION:A switch 6 is added in the course of a line to a bypass capacitor 5 for preventing oscillation and in an normal operation, with the bypass capacitor 5 kept opened, a power source applying condition is set into an inspection program so that the switch 6 is turned ON when oscillation items are set. Then, when inspection reaches an oscillation item, a power source 7 is inputted to turn ON the switch 6, so that the capacitor 5 is connected. Upon the ending of a set item, the switch 6 is turned OFF and the capacitor 5 becomes open. With this action, effect of the capacitor 5 can be prevented on inspection items other than the oscillation item. This eliminates extension of measuring time required depending on abnormal characteristic thereby enabling reduction in inspection cost.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor integrated circuit testing and aims to shorten measurement time.

Conventional Technology In recent years, intense sales competition has surfaced in the semiconductor industry, and this has also intensified cost competition among manufacturers. Reducing inspection time, which is part of product cost, is also becoming an important issue. A conventional inspection example will be explained below.

Figure 2 shows an example of an inspection currently used as a measure to prevent oscillation. When testing a semiconductor integrated circuit 1, bypasses are used between power supply voltage 2 and ground 4, between output bin 3 and ground 4, and between other bins to prevent oscillation. A capacitor of 5 is inserted to bypass unnecessary AC power to ground, etc. to prevent oscillation. The normal test characteristics are as shown in Figure 3 (a), but due to the influence of the bypass capacitance, the waveform becomes dull as shown in the characteristic line in Figure 3 (b), and at the stable measurement point A, it is lower than the normal value characteristic range. Since the measured value deviates, the measurement time must be extended to reach the stable measurement point B. The more items such countermeasures are taken, the longer the measurement time becomes, causing an increase in inspection costs.

Problems to be Solved by the Invention Conventionally, this problem has been solved by extending the measurement time of inspection items whose measurement stability points have shifted due to the influence of bypass capacitors for preventing oscillation. Therefore, the inspection time becomes longer than necessary and the inspection cost becomes expensive. The present invention solves the above-mentioned conventional problems, and aims to eliminate the extension of measurement time due to the influence of bypass capacitance and reduce inspection costs.

Means for Solving the Problems In order to achieve this object, the present invention has a function of preventing an extension of the measurement time by using switching means such as a relay or a transistor switch for the external bypass capacitor.

Effect: This function eliminates the effect of the oscillation prevention bypass capacitor on items other than the necessary items, so there is no longer any interference with the output rise of other items, and there is no need to extend the measurement time.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor device characteristic testing apparatus according to an embodiment of the present invention. In FIG. 1, l is a semiconductor integrated circuit that is a fixed object, 2 is a power supply voltage input, 3 is an output bin, 4 is ground, 5 is a bypass capacitor 16 is a switch, and 7
is the power source. 1 to 5 are the same as the configuration of the conventional example.

The operation of the semiconductor integrated circuit testing apparatus of this embodiment configured as described above will be described below.

First, a switch 6 is added in the middle of the oscillation prevention bypass capacitor 5, and power supply conditions are set in the test program so that the bypass capacitor is in an oven state during normal times and the switch is turned on when measuring oscillation items. When the test reaches the oscillation item, the power supply 7 is input, the switch is turned on, and the bypass capacitor is connected. When the source setting items are completed, the switch is turned off and the bypass capacitor is in the oven state. This operation can prevent the adverse effects of bypass capacitance on test items other than oscillation items. Therefore, the inspection cost can be reduced since the extension of measurement time due to abnormal characteristics as shown in FIG. 3(b) becomes unnecessary.

Effects of the Invention The present invention provides an excellent semiconductor integrated circuit that can prevent the influence of the bypass capacitor on items other than necessary by providing a switch in the oscillation prevention bypass capacitor in a semiconductor integrated circuit testing device, thereby suppressing the extension of the measurement time. This enables circuit inspection.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit testing device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional integrated circuit testing device, and FIG. It is a characteristic diagram showing the influence given. 1...Object to be measured, 2...Power supply voltage, 3
...Output bin, 4...Ground, 5...
...Bypass capacity, 6...Switch, 7.
·····power supply.

Claims (1)

[Claims] Bypass capacitors for preventing oscillation are connected between the external lead terminals of the semiconductor integrated circuit and between the external lead terminal and the ground through switching means, and the switching means is closed when the corresponding terminal is inspected, and when not inspected. A semiconductor integrated circuit testing device characterized by being open.