JPH0321141A - Adjacent interference removing device - Google Patents

Abstract

PURPOSE:To remove inter-code interference generated by the over-suppression of a sidelevel on the end part of a required frequency band by providing the adjacent interference removing device with an adaptive type transversal equalizing unit consisting of a transversal filter and a gain control circuit. CONSTITUTION:A receiving filter 1 filters an input signal and outputs the filtered output signal to an adaptive type amplitude equalizing unit 2. The unit 2 supplies a curvature equalizing signal to an amplitude control circuit 23 and an adaptive type transversal equalizing unit 3 as the 1st equalizing signal through an inclination equalizer 21 and a curvature equalizer 22. A transversal filter 31 in the unit 3 equalizes the inter-code interference of the inputted 1st equalizing signal in response to plural controllable tap gains and generates and supplies the 2nd equalizing signal to a demodulator 4. A gain control circuit 32 inputs the output of the demodulator 4 and controls the tap gain in response to reproduced code sequence and digital error signal so as to reduce the inter- code interference. Thereby, the inter-code interference to be generated by the over-suppresion of a side level on the end part of a required frequency band can be removed.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is an adjacent interference canceller that processes a human code carrying a digital code sequence digitized by a reference clock signal and outputs an output signal to a demodulator. Regarding dog equipment.

Here, the demodulator demodulates the output signal into a regenerated clock signal and a regenerated collar code sequence that is digitized and accompanied by the output signal, and the regenerated evening lock signal is used to reproduce the reference signal. The reproduced code sequence is a reproduced digital code sequence.

Conventional Technology Generally, devices of this type are supplied with a human signal carrying a digital code sequence. Such devices include a receive filter that filters a human signal having a digital code sequence and generates a filtered output signal.

The filtered output signal has amplitude distortion in the desired frequency band due to adjacent interference on the desired frequency band by other frequency {1} bands adjacent to the desired frequency band. The adjacent interference remover is used to equalize this amplitude distortion.

A conventional adjacent interference canceling device is disclosed in US Pat. No. 4,333,063, invented by Toshihiko Ryu. The disclosed apparatus is responsive to the filtered output signal described above and equalizes adjacent interference along the frequency axis of the filtered output signal to generate an amplitude equalized signal with intersymbol interference as an output signal. It was something.

The human signal has a center level at the center of the desired frequency band. This desired frequency band lies between two other frequency bands and is located at the frequency ends of these other frequency bands. The input signal has side levels at one or both ends of the desired frequency band. Therefore, the human signal will necessarily include side levels as level components located in one or two regions of the desired frequency range adjacent to other frequency bands.

[Problem to be Solved by the Invention] However, in the adaptive amplitude equalization unit in the conventional adjacent interference cancellation device, there is a problem in that inter-symbol interference occurs in the amplitude equalized signal due to excessive side-level suppression. . This is due to the reception filter being unable to appropriately suppress the side level.

That is, when the input signal undergoes fading or the like, the center level decreases. Also, the side level is usually lower than the center level. However, if the center level decreases, the side levels will be overestimated as being higher than the center level. As a result, the adaptive amplitude equalization unit 1 works to suppress the side level excessively, and an amplitude equalized signal accompanied by intersymbol interference is generated.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, it is a technical object of the present invention to provide an adjacent interference cancellation device that cancels intersymbol interference caused by excessive suppression of side level I at the ends of a desired frequency band.

[Means for Resolving the Problem] According to the present invention, an input signal having a digital code sequence is filtered to eliminate interference caused by adjacent interference on the desired frequency band due to other frequency bands adjacent to the desired frequency band. do,
a receive filter that outputs a filtered output signal with amplitude distortion occurring in the desired frequency band; and a receive filter that is responsive to the filtered output signal and equalizes the adjacent interference along the frequency axis of the filtered output signal. , and a first adaptive equalization means that generates a first equalized signal with intersymbol gradation. There is obtained an adjacent interference canceling device characterized in that a second adaptive equalization means is provided for equalizing the intersymbol interference along the line and generating a second equalized signal as an output signal.

Further, according to the present invention, in the adjacent interference canceling apparatus according to claim 1, the digital code sequence is digitized using a reference clock signal, the output signal is digitized with a reproduced clock signal, and the output signal is digitized with the reproduced clock signal. Played with a signal? ] Compound in the number series: J;. Do you want to +? M
:J;! The regenerated cross signal is a regenerated version of the arbitration signal, and the regenerated initial sequence is connected to the digital signal? ] code sequence, the digitized and output signal is digitized in relation to the intersymbol interference, and the second adaptive equalization means has a controllable Tasob gain The first adaptive equalizer and the demodulator are connected to the first adaptive equalizer and the demodulator to equalize the intersymbol difference lJIli in response to the tap gain, and 1. generates a second equalized signal and supplies the second equalized signal to the demodulator;
A Lance Herzal filter is connected to the demodulator, and in response to the recovered Xun code sequence and the digitized output signal, the tap gain? II, the intersymbol difference? and gain control means for controlling e to decrease.

[Example of large vertebrae] Next, length embodiments of the present invention will be described with reference to the drawings.

The adjacent interference removal device according to Nobuaki Hon receives a human input signal modulated at a predetermined modulation rate and generates an output signal. The human input signal converts the digital code sequence digitized by the reference signal into an H signal.

As shown in FIG. 1, the adjacent interference canceling device includes a reception filter 1 that receives an input signal, and adaptive amplitude equalization units 1 and 2.
and an adaptive transversal equalization unit 3 which provides an output new word to a demodulator 4.

The receive filter 1 filters the input signal and outputs the filtered output signal to the adaptive amplitude equalization unit 2.

As shown in Fig. 2(a), the input signal is composed of a desired frequency/1 band signal A and other frequencies/2 band signals BC. The filtered output signal is at the desired frequency;'
Although there is a signal in the i': range A, as shown in FIG. 2(b), it is accompanied by amplitude distortion caused by another frequency -i1:.range BC. This is because the reception filter 1 cannot properly suppress the other frequency band signals B and C.

Transverse width strain consists of first-order tilt strain and higher-order curvature strain. The primary slope distortion is defined by the primary slope and the slope polarity. The several-order curvature run includes a second-order curvature distortion and a higher-order curved skew distortion. High-order curvature distortion is defined by a high-order curvature component and curvature polarity, and second-order curvature distortion is defined by a second-order curvature component and a curvature slope.

Hereinafter, the first-order tilt distortion and the second-order curvature distortion will be explained.

Returning to the figure, the adaptive amplitude equalization unit 2 includes a slope equalizer 21 and a curvature equalizer 22 arranged in series. Equalizer 2
1.22 is designed to equalize the first-order slope distortion and higher-order West modulus distortion of the filtered output signal, respectively.

The filtered output signal is provided to a slope equalizer 21 .

The slope equalizer 21 equalizes the primary slope distortion in response to the slope control signal X, and generates a slope equalization signal.

The A diagonal equalization signal is supplied to the R diagonal equalization signal.

In response to the quadratic curvature control signal Y, the curvature equalizer 22
Next, equalize the distortion. Then, the curvature equalizer 22
A curvature equalization signal is supplied as an equalization signal to the amplitude control path 23 and to the adaptive 1-Lance Barzal equalization unit 3 .

As shown in FIGS. 1 and 5, the adaptive 1-Lanceversal unit 3 has an l-Lanceversal filter 3], and the i-Lanceversal filter 3] receives the first equalized signal IN. C(-1), C(0), and C++
1) filtering into a second equalized signal OUT which is equalized in response to a plurality of controllable tap gains represented by: This equalized second equalized signal OUT is also
Like the equalized signal IN, it is subjected to 4×4 orthogonal amplitude modulation, but is equalized by the transversal filter 31. The illustrated transversal filter 31 includes 3
I'm having sex with the tap. The central one of the three taps is called the center or first tap 33. Other taps are shown to the left and right of the central tap 33;
They are called a second tab 34 and a third tap 35, respectively. Further, the second and third taps 34 and 35 are connected to the first and second taps 34 and 35.
{, also called I-added tap.

The first and second delay units I-36.37 are located between the second and first taps 34.33 and between the first and third taps 33.35, respectively. Each of the first and second delay units I-36.37 provides a delay substantially equal to the reciprocal of the modulation rate. The first equalized signal IN is sent to the second tap 34 as the first {=J added tap signal of {=J added taps, and the first equalized signal IN is sent to the second tap 34 as the first {=J added tap signal of the They are successively delayed by spreading units 1 and 36.37 and sent to the first and third taps 33.35, respectively. The center tap signal and the second additional tap signal are outputted respectively, and the second, first and third taps 34, 33 and 35 are outputted as the center tap signal and the second additional tap signal, respectively (-
Let us indicate them by consecutive numbers: 1), O, (+1). In this regard, the 1 additional tap signal appearing at (-1) tap 34 is designated by S (-1). Similarly, the center and second additional tap signals are each S
The first equalized signal IN, denoted by (0) and S (+1), is quadrature modulated and includes in-phase and quadrature-phase components.

The in-phase and quadrature-phase components are processed individually with respect to the center tap signal S(0). More specifically, the first additional tap signal S (-1) is sent to the first in-sync multiplier 41 and the first orthogonal multiplier 42 . The second additional tap signal S (+1) is sent to a second in-sync multiplier 43 and a second orthogonal multiplier 44 . It is provided only to the central synchronizer 45. This is because the center tap signal S(0) has no quadrature phase component. Each of multipliers 41-45 is called a weighting circuit.

．． Iill controllable tap gain C (0),
C (-1>, and C (+1) are as described below,
It is generated by the gain control circuit 32. The controllable tap gains C(0), C(-1), and C(+1> are called the center complex control signal, first and second complex control signals, respectively. The center complex control signal C(0) is the real , and is therefore represented by r(0) in FIG.

On the other hand, the first and second complex control signals C (-1), and C
(+1) consists of a real part and an imaginary part, respectively denoted by r and d. In FIG. 5, the first complex control signal C
(profit) is expressed by the combination of r (-1) and d (-13), and the second complex control signal C (+1) is r (1
)1 2 and d(1).

As shown in FIG. 5, the first complex control signal C (-1
) are sent from the gain control circuit 32 to the first in-phase and first quadrature multipliers 41 and 42, respectively. Similarly, the real and imaginary parts r(1) and d(1) of the second complex control signal C(1) are sent to second in-phase and second quadrature multipliers 43 and 44, respectively. The central complex control signal C(0), i.e., r(0), is sent to the central synchronizer 45 in the following manner.

The first in-phase and first quadrature multipliers 41 and 42 supply a first controlled in-phase component S' (-1) and a first controlled quadrature component to the first and second adders 51 and 52, respectively. S'(-1) is supplied. The second in-phase and second quadrature multipliers 43 and 44 supply the first and second adders 51 and 52, respectively, with second controlled in-phase components and A second controlled orthogonal component is provided. Each of the first and second in-phase components is referred to as a first controlled signal, and each of the first and second quadrature components is referred to as a second controlled signal. The central controlled in-phase component S'(0) is sent from the central in-phase multiplier 45 to the first adder 51.

The first and second adders 5] and 52 perform addition and output an in-phase signal RS and a quadrature signal IS, respectively, representing the addition results. The in-phase and quadrature signals RS and IS are referred to as first and second processed signals, respectively. In this regard, the first and second adders 51 and 52 are referred to as first and second processing circuits, respectively. The in-phase and quadrature signals RS and Is are combined into a combined signal by a combining circuit 53 while maintaining the quadrature phase relationship between the in-phase and quadrature signals RS and Is. The combined signal is sent to the demodulator 4 as an equalized signal OUT.

The demodulator 4 has a coherent detector 56 responsive to the equalized signal OUT and a regenerated carrier provided by a carrier regenerator 57. The coheren 1 detector 56 performs coheren 1 detection on the recovered carrier wave and outputs a demodulated baseband signal. The demodulated perspective hand signals are separated from in-phase and out-of-center components represented by BT) and Bq, respectively. In-phase and quadrature components B T)
and B q have in-phase and quadrature levels, respectively.

In response to the in-phase and quadrature components Bp and Bq of the base hand signal, clock generator 59 sends a recovered clock signal C L K to both gain control circuit 32 and discriminator 61 . The reproduced clock signal CLK is a reproduction of the reference clock signal. The discriminator 61 produces a reproduced data sequence D. 11↑The generated data series is ilj il= of the transmission data series. The reproduced data series D has in-phase data components Dp, Dp'
and orthogonal data components Dq, Dq'. In-phase data components Dp, Dp' represent the orthogonal level of the in-phase component Bp of the demodulated baseband signal, and similarly, orthogonal data components Dq, Dq' represent the orthogonal level of the orthogonal component Bq of the demodulated baseband signal. represents. Discriminator 61
also generates a digital error signal E. A digital error signal E is associated with the reproduced data sequence D. Each digital error signal E consists of in-phase and quadrature error components Ep and Eq corresponding to in-phase and quadrature data components Dp and Dq.

Such a discriminator 61 is a "1'11 concave path" described in the above-cited US patent, and therefore a description thereof will be omitted.

The carrier wave regeneration circuit 57 generates a regenerated carrier wave in response to the in-phase and quadrature components Bp and Bq of the demodulated baseband signal.The regenerated carrier wave chain 57 is coupled to an asynchronous detection circuit 62. ing.

The asynchronous detection circuit 62 supervises the carrier wave regeneration circuit 47 to detect an asynchronous state of the ':5 conversion system, and when the asynchronous detection circuit 62 detects an asynchronous state, outputs an asynchronous state signal ASY indicating a bad asynchronous state. Output.

The in-phase and quadrature errors Ep and Eq of the digital error signal E and the in-phase and quadrature data components Dp and Dq of the reproduced data sequence are the evening lock signal C L K reproduced from the demodulator 55 and the asynchronous state. Signals ASY and J (to,
The signal 1 5 1 6 is outputted to the gain control circuit 38 .

The gain control circuit 38 receives a regenerated clock signal CLK,
Corresponding to the in-phase and quadrature errors Ep and Eq of the digital error signal E and the in-phase and quadrature data components Dp and Dq of the reproduced data series D, the gain control circuit 38 controls the F) Using an algorithm to control the controllable tap gain C(i). Here, J represents a tap number such as O, (1), and (+1). Assume that the time k of the kth 1 is earlier than the (k+1)th time (k→1) by the repetition period of the clock signal C L K generated by 11↑. According to the zero-phonenk algorithm, 1,1j controllable tap gain C (
j. k+1) is the digital error at the first (time l(), f≦E(k),
No. II] 1,? 41r generated data sequence D (k-j) at time (k-i), and the first (number "II of 1, 1
It is determined by the combination with the controllable tap gain C (j.k) at j increments.

C (j.k+1)-C (j,k)-Δ[sgnfΣ
D ” (k-j)XE (k)lko... (1
) C (j, k) - r (j, k) + id (j
, k) − (2)E (k)
1 E p (lc) + i E q (1()
... (3) D ″(k-j) = D p
(k-j)-i D q (k-j)...
(4) where Δ represents the fixed j soka step size, 1 is the number of blood equal to J-1, ! , 11, the symbol sgn represents the polarity of the variable enclosed in a pair of curly braces, and H represents a raw integer.

The tap profit m C (j, k+1) that can control +1J is the real part and imaginary part r (j.k+1) given by the following equation.
and d(j.k+1).

r (j, k+1) − r (j, k) 18 [sgnfl
(lEp(k)■D I) (k−D+ E q (
k) ■D q (k-j)l] (5) ] 8 d (j.k+1)-d (j,k)-Δ[sgn(Σ
(Eq(k)■D p (k-j) 1 Ep(k) ■
D q(k−j)lko (6) Here, the symbol ■ is used as the υ1/adversarial OR operator, and the symbol ○ is used as the exclusive NOR operator.

The gain control circuit 38 and the correlation detection circuit 63 perform integration Ii''!
I-way 64. The correlation detection circuit 63 detects the data series D (m) which has been converted by +lj and the digital vote difference signal E.
(m) and output a plurality of correlation signals. The integrating circuit 63 integrates the correlation signal and converts a plurality of integrated signals into a controllable tap gain? 'MC(j
).

Referring to FIG. 6, in order to better understand the present invention,
A conventional correlation detection circuit will be explained.

The illustrated correlation detection circuit 63 has a delay circuit 65 and an exclusive logic circuit 70. The delay circuit 65 outputs the reproduced data series D (m) and the digital error IZ E (m).
and outputs a delayed data series D(rn1) and a delayed error signal E(m-1) in synchronization with the reproduced clock signal CLK. The delayed data sequence D (m-1) and the delayed error signal E (m-1) are compared with the reproduced data sequence D (m) and digital error signal E (+m), respectively. It is delayed by one repetition period of the regenerated clock signal C L K.

More specifically, the delay circuit 65 includes the first to fourth
It has flip-flops 66, 67, 68, and 69. The first flip-flop 66 propagates the in-phase error component Ep(m) of the digital error signal E(m) in synchronization with the regenerated clock signal CLK, and converts the delayed error signal E(m-1). Delayed common-mode error component Ep(m-1.
) is output.

Similarly, the second flip-flop 67 delays the orthogonal error component Ep(m) of the digital error signal E(m) in synchronization with the regenerated clock signal CLK, and outputs the delayed error signal E(m- 1) Delayed orthogonal error component Eq
Output (m-1). The third and fourth flip-flops 68 and 69 synchronize the in-phase and quadrature data 20 components Dp(m) and Dq(m) of the reproduced data series D(m) with the reproduced evening lock signal CLK. and outputs delayed in-phase and extended orthogonal data components Dp(m-1) and Dq(m-1) of the delayed data sequence D(m-1).

The delayed data series D (m-1), the delayed error signal E (m-1), the reproduced data series D (m), and the digital error signal E (m) are excluded as multiple input signals. is supplied to a logical logic circuit 70. Exclusive logic circuit 7
0 performs an exclusive logic operation on the input signal and outputs a correlated signal. The exclusive logic circuit 70 has first to ninth exclusive OR gates 71, 72, 73, 7
4, 75, 76, 77, 78, and 79, and first to third exclusive NOR gates 81, 82
, and 83. More specifically, the first exclusive OR gate 71 performs an exclusive OR operation on the in-phase error component Ep(m) and the in-phase data component Dp(m), and generates the first correlation signal Pr(0). Output. Therefore, the first correlation signal Pr(0) can be given by the following equation.

P r (0) = Ep (m) ■Dp(
m). Similarly, the second exclusive OR gate 72 performs an exclusive OR operation on the orthogonal error component Eq(m) and the orthogonal data component Dq(m), and outputs the second correlation signal Qr((1) .The second correlation signal Qr(0) is given by the following equation.

Qr (0)-Eq (m)■Dq(m). Similarly, the third exclusive OR gate 73 calculates the orthogonal error component Eq(m)
and the in-phase data component Dp(m), and outputs the third correlation signal Qd(0). The correlation signal Qd (0) of scoop 3 is given by the following equation.

Qd (0)=Eq (m)■Dp(m). The first exclusive NOR gate 81 performs an exclusive NOR operation on the in-phase error component Ep(m) and the orthogonal data component Dq(m), and
A correlation signal Pd(0) is output. Fourth correlation signal Pd
(0) is given by the following equation.

Pd (0)=Ep (m)■Dq(m). In this way, the fourth, fifth, and sixth exclusive OR nodes i-}74,7
5, 76, and the second exclusive NOR gate 82, the correlation signals Pr(-1.)Qr(-1),Qd( -1
), and Pd(-1.) are output.

P r (-1.) 1E T) (m - :l.
)■Dp (m)Qr (-1)-Eq (m-1)
■Dq (m)Qd (-1)=Eq (m-1)■
Dp(m)P r (-1) 1Ep (m-1)■D
q(rn). Similarly, the 7th, beat 8, and 9th exclusive O
Rke 1, 77, 78, and 79, and the third JJI other N
○R game 1/83 is the 9th, 1st,
Eleventh and twelfth correlation signals Pr(1)Qr(1)
, Qd (1), and Pd (1).

Pr (1)=Ep (m)■Dp(m-1)Qr
(1)=Eq (tn)■Dq(m-1)Qd
(].)=Eq (m)■[)p(m-1.). P
d(1)=Ep(m)ODq(m-1) The correlation signals other than the third and fourth correlation signals Qd(0) and Pd(0) are supplied to the equity circuit 64.

Although the in-phase and quadrature components Bp and Bq of the demodulated baseband signal are supplied to the carrier wave IT% same path 57 as described above, the in-phase and quadrature components Bp and Bq of the demodulated baseband signal are It does not necessarily have to be supplied to the carrier wave regeneration [Ol path 57. In this case, the third and fourth Kankan 1, January QcJ (0) and Pd
(0) but; J. 'J is used in place of the in-phase and quadrature components Bp and Bq of the baseband signal.

Returning to FIG. 1, the integration circuit 64 includes first through fifth reconfigurable integrators 91, 92, 93, 94, and 95. The first reconfigurable integrator 91 is coupled to the first and second exclusive OR gates 71 and 72 via the barrel 1 and the second resistors 101 and 102. Similarly,
The second reconfigurable integrator 92 includes the third and fourth reconfigurable integrators 92.
through resistors 103 and 104 to fourth and fifth exclusive OR gates 74 and 75. The third configurable integrator 93 connects the sixth exclusive O R ke = 1・
76 and the second exclusive NOR game 1.82. The fourth reconfigurable integrator 94 includes a seventh and an eighth reconfigurable integrator 94.
are coupled to the brush 7 and the eighth alternative OR gate 77 and 78 via resistors 107 and 108 . The reset function 1-IJ function 2g95 of button 5 connects the 9th exclusive OR gate 7 and the gate 3 exclusive NOR through the 9th and 10th resistors]09 and 1]0. It is combined with Game 1.83.

The pair of first and second resistors 101 and 102 are
Correlation signal P r (0) and second correlation signal Qr (0)
and outputs a first combination signal E R (0). Therefore, the first match signal E R (0) is given by the following equation.

E R (0) − P r (0) + Q r (
0) = E p (m) ■ D p (
m)+Eq(…)■D q (m). Similarly, another pair of third and fourth resistors]03 and]
04 combines the 24 5 correlation signal Q r (-1) to the fourth correlation signal P r (-1) and the first one, and the combined signal E R of Koma 2 is given by the following equation. Outputs (-1).

E R (-1) = P r (-1) + Q r (
-1) = E p (m-1) ■ D p (m) + E
q (m-1)■Dq(m). In this way, the fifth
and the sixth resistor 105 and ]06, the seventh and eighth resistors 107 and ]08, and the ninth and tenth resistors 109 and 1]0, respectively, as shown in the following equation. The third, fourth, and fifth condensed signals E I (-1
), E R (1), and E I (1).

E I (-1) = Q d (-1) -1- P d
(1) = E q (-1) ■ D p (m) + E
p (-1)■D q (m) ,ER(1) 1P
r (1.) → −Q r (1)= E p (m)■
D p (m-1)+ E q (m) OD q (
m-1) El (l.) = Qd (↓) + Pd (1.) -E
q (m) ■Dp (...-1) + E p (m) ■D q (m-1) 1st to 5th
The reconfigurable integrators 91 to 95 are connected to the asynchronous detection circuit 62.
is combined with The asynchronous state signal ASY is transmitted from the asynchronous detector 62 to the first to fifth reconfigurable integrators 91 to
95, the first reconfigurable integrator 91
is reset to a logic "1" level and maintained at a logic "1" level. Each of the other integrators 91 to 93 has a logic “O”.
” level. Meanwhile, the asynchronous status signal ASY
does not exist, each of the integrators 91 to 95 is
Combined f! No. ER (0), ER (-1),
E I (-1), E R (1) and E I (
1) to remove unnecessary noise components from each combined signal. In any case, the first to fifth integrators 91 to 95 have controllable tap gains C(0),
C (-1) and c (+i) are output.

The first to tenth resistors 101 to 110 are used to balance each pair of correlated signals, as described above. However, OR gates may be used in place of the first to tenth resistors 101-110.

As shown in FIG. 2(d), it can be seen that the adaptive transversal equalization unit 3 operates to eliminate intersymbol interference. This has made it possible to remove all amplitude distortion caused by intersymbol distortion.

[Effects of the Invention] According to the present invention, it is possible to obtain an adjacent interference canceling device that cancels 7:) inter-signal interference caused by excessive suppression of side levels at the ends of a desired frequency band.

[Brief explanation of the drawing]

FIG. 1 is a block diagram relating to an embodiment of the present invention, and FIG. 2 (
a) is a diagram showing the spectrum 1 of the human signal, and Figure 2 (b)
) Diagram showing the spectrum of the hollow wave output signal, Figure 2 (c
) is a diagram showing the spectrum of the first equalized fci signal with intersymbol interference, FIG. 2(d) is a diagram showing the spectrum of the second equalized signal with intersymbol interference removed, and FIG. is a block diagram of the amplitude control circuit shown in Fig. 1, Fig. 4 is a characteristic diagram of the three waves in the amplitude control circuit of Fig. 3, and Fig. 5 is a diagram of the adaptive transversal etc. used in Fig. 1. A block diagram of the equalization unit, FIG. 6; is a correlation detection circuit in the adaptive transversal equalization unit of FIG. DESCRIPTION OF SYMBOLS 1... Reception filter, 2... Adaptive amplitude z5 equalization unit, 3... Adaptive transversal equalization unit 1
・, 4... Capacity adjuster, 21... Slope equalizer, 22...
- Curvature equalizer, 23... Amplitude control circuit, 31... Transversal filter, 32... Gain control circuit. 2nd frequency fo-f1fofo+f1 fo"-f 1fo fo"f1 +a+ tb+ (Cl (di W4馨

Claims (1)

Claims: 1) filtering an input signal having a digital code sequence to reduce the frequency of the desired frequency band due to adjacent interference on the desired frequency band by other frequency bands adjacent to the desired frequency band; a receive filter that outputs a filtered output signal with amplitude distortion occurring in the band; and a receive filter that is responsive to the filtered output signal and equalizes the adjacent interference along the frequency axis of the filtered output signal to eliminate intersymbol interference. and a first adaptive equalization means that generates a first equalized signal with an adjacent interference canceling device that receives the first equalized signal and generates a first equalized signal along the time axis of the first equalized signal. 1. An adjacent interference canceling device comprising second adaptive equalization means for equalizing interference and generating a second equalized signal as an output signal. 2) The adjacent interference canceling device according to claim 1, wherein the digital code sequence is digitized by a reference clock signal, and the output signal is demodulated into a recovered code sequence with a recovered clock signal and a digital error signal. the regenerated clock signal is a regenerated version of the reference signal; the regenerated code sequence is a regenerated version of the digital code sequence; and the digital error signal is a regenerated version of the digital code sequence. associated with intersymbol interference, the second adaptive equalization means having a plurality of taps with controllable tap gains and connected to the first adaptive equalization means and the demodulator; a transversal filter that equalizes the intersymbol interference in response to the tap gain to generate the second equalized signal and supplies the second equalized signal to the demodulator; and a transversal filter connected to the demodulator. , and gain control means for controlling the tap gain so as to reduce the intersymbol interference in response to the reproduced code sequence and the digital error signal.