JPH03211760A - Repairing and connection of input/output pin - Google Patents
Repairing and connection of input/output pinInfo
- Publication number
- JPH03211760A JPH03211760A JP2006111A JP611190A JPH03211760A JP H03211760 A JPH03211760 A JP H03211760A JP 2006111 A JP2006111 A JP 2006111A JP 611190 A JP611190 A JP 611190A JP H03211760 A JPH03211760 A JP H03211760A
- Authority
- JP
- Japan
- Prior art keywords
- pin
- repair
- input
- electrically insulating
- output pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体パッケージ、具体的にはLSIチップを
高密度に集積したモジュールのためのパッケージ実装に
好適な半導体パッケージの入出力用ピンの補修接続法に
関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the repair of input/output pins of semiconductor packages, specifically, semiconductor packages suitable for package mounting for modules in which LSI chips are integrated at high density. Regarding the subjunctive method.
半導体デバイスの製造技術における微小化と単−装置上
の素子数の増加という傾向に伴って、これらのデバイス
間の信号接続、及び、供給電源などの外部信号の接続に
ついても微小化される。このため信号接続の短小化、信
頼性向上と同時に不良素子交換の容易な入出力用ピンに
よる接続構造の半導体パッケージを提供する必要性があ
る。With the trend toward miniaturization in semiconductor device manufacturing technology and an increase in the number of elements on a single device, signal connections between these devices and connections for external signals such as power supply are also miniaturized. For this reason, there is a need to provide a semiconductor package having a connection structure using input/output pins that can shorten signal connections, improve reliability, and facilitate the replacement of defective elements.
例えば、特公昭58−73139号公報に示される高密
度半導体装置では、半導体装置の基板に取付けられた外
部リードの入出力ピンとプリント基板のスルーホールに
固定されたボス1〜が、各々、双方向コネクタの上、下
のソケットに挿入されて、半導体装置の外部リードとプ
リント基板との電気的接続が図られている。For example, in the high-density semiconductor device disclosed in Japanese Patent Publication No. 58-73139, the input/output pins of the external leads attached to the substrate of the semiconductor device and the bosses 1~ fixed to the through holes of the printed circuit board are bidirectional. They are inserted into the upper and lower sockets of the connector to establish electrical connections between the external leads of the semiconductor device and the printed circuit board.
半導体装置の外部リードとして多数の入出力ピンによる
ピングリッドアレイ構造は、プリント基板への容易で確
実な装着を可能にしているが、この多数の入出力ピンが
一本でも脱落、あるいは。A pin grid array structure with a large number of input/output pins as external leads of a semiconductor device enables easy and reliable mounting on a printed circuit board, but even one of these many input/output pins may fall off or fall off.
曲がりが生じた時、装着は不可能となる。When bending occurs, installation becomes impossible.
上記従来技術に見られるように、チップ間の信号接続や
外部との信号接続に入出力ピン接続を行って実装距離の
微小化が求められる。しかし、チップレベルの高集積化
とともに多数のチップを単一基板に搭載するモジュール
レベルでの高密度化の傾向があり、当然のことながら、
入出力ピンの数は膨大となり、製造過程等で生じる人出
力ピンの曲がり、基板パッドからの脱落等入出力ピンの
破損は皆無とは言い難い。この点、従来技術における半
導体装置の入出力ピンである外部リートについても、人
出力ピンの補修手段が必要とされる。As seen in the above-mentioned conventional technology, miniaturization of the mounting distance is required by making signal connections between chips and input/output pin connections for external signal connections. However, along with higher integration at the chip level, there is a trend toward higher density at the module level, where many chips are mounted on a single substrate, and as a matter of course,
The number of input/output pins is enormous, and it is difficult to say that there is no possibility of damage to the input/output pins, such as bending of the output pins or falling off the board pads, which occurs during the manufacturing process. In this regard, repair means for human output pins are also required for external REITs that are input/output pins of semiconductor devices in the prior art.
本発明の目的は、多数の人出力ピンを効率的に接続する
ことができ、入出力ピンの曲がり、脱落等の破損に対し
て、破損入出力ピンの修復を可能にし、ピングリッドア
レイを成立させる入出力用ピンの補修接続法を提供する
ことにある。The purpose of the present invention is to be able to efficiently connect a large number of human output pins, to repair damaged input/output pins in case of damage such as bending or falling off, and to establish a pin grid array. The purpose of this invention is to provide a repair connection method for input/output pins.
上記目的を達成するために、本発明に係る半導体装置は
、一個あるいは複数個の半導体チップを搭載された配線
基板とこの基板に外部リードとして多数の入出力ピンを
備え、前記配線基板の入出力ピンと接続されて配線基板
間の信号あるいは外部電源との接続を図るコネクタ及び
プリント基板からなる半導体装置において、前記配線基
板の既設の健全な人出力ピンに係留してなる電気絶縁性
の部材に補修用の入出力ピンを固定し、配線基板の既設
パッドに前記入出力ピンを接続して構成したものである
。In order to achieve the above object, a semiconductor device according to the present invention includes a wiring board on which one or a plurality of semiconductor chips are mounted, and a large number of input/output pins as external leads on this board. In a semiconductor device consisting of a connector and a printed circuit board that are connected to pins to connect signals between wiring boards or to an external power supply, repairs are made to an electrically insulating member that is moored to an existing and healthy human output pin of the wiring board. The input/output pins are fixed and connected to existing pads on the wiring board.
多数の半導体チップを搭載した配線基板表面には金属パ
ッドがあり、入出力ピンはこのパッドにろう付けされる
。補修が必要とされる入出力ピンの破損形態は、ピング
リッドのアライメントをずらすピンの曲がり、ピンの脱
落が考えられる。この時、金属パッドも使用に耐えなく
なることから、元のパッド位置でのはんだ付けによるピ
ン修復は困難となる。There are metal pads on the surface of a wiring board on which many semiconductor chips are mounted, and input/output pins are brazed to these pads. Possible forms of damage to input/output pins that require repair include bent pins that shift the alignment of the pin grid, and pins that fall off. At this time, the metal pads also become unusable, making it difficult to repair the pins by soldering at the original pad positions.
従って、補修ピンをあらかじめろう付けした電気絶縁性
の支持体の弾性変形を利用して補修ピンは、元のパッド
位置の配線層メタライズ部に、直接、押し付は接続され
る。補修ピンの支持板は。Therefore, by utilizing the elastic deformation of the electrically insulating support to which the repair pin is previously brazed, the repair pin is directly pressed and connected to the metallized portion of the wiring layer at the original pad position. The support plate for the repair pin.
補修ピン位置近傍の健全ピンに固定出来る。または、補
修ピンの支持板は、入出力ピンが挿入接続されるコネク
タ板によって抑圧固定することも可能である。It can be fixed to a healthy pin near the repair pin position. Alternatively, the support plate of the repair pin can be fixed by being pressed by a connector plate into which the input/output pin is inserted and connected.
ピンアレイの挿通孔とのマツチング、すなわち、位置ず
れが許容されない完全なアライメントが要求されるため
、元のパッド位置に接続されて設けられた補修パッドを
利用することが出来る。すなわち、ワイヤとピン部から
なるワイヤ付きピン型コンセントを用い、ワイヤの一端
を補修パッドにろう付けすることにより、ワイヤのフレ
キシビリティで、ピンアライメントを保つピン挿通によ
り接続を図ることが出来る。Since matching with the insertion hole of the pin array, that is, perfect alignment with no misalignment is required, a repair pad connected to the original pad position can be used. That is, by using a wired pin type outlet consisting of a wire and a pin part and brazing one end of the wire to the repair pad, the flexibility of the wire allows the connection to be made by inserting the pin to maintain pin alignment.
[実施例] 以下、本発明の実施例を図面により具体的に説明する。[Example] Embodiments of the present invention will be specifically described below with reference to the drawings.
第1図ないし第3図は、本発明の一実施例の入出力用ピ
ンの補修接続法を示す構成図である。第1図は接続構造
の全体構成、第2図は、補修ピン近傍の詳細を示す斜視
図、第3図は、第2図の1−1部の断面図である。1 to 3 are configuration diagrams showing a repair connection method for input/output pins according to an embodiment of the present invention. FIG. 1 is an overall configuration of the connection structure, FIG. 2 is a perspective view showing details of the vicinity of the repair pin, and FIG. 3 is a sectional view taken along line 1-1 in FIG.
一個あるいは複数個の半導体チップが電気的に接続され
てセラミックス配線基板2の上表面に搭載されている。One or more semiconductor chips are electrically connected and mounted on the upper surface of the ceramic wiring board 2.
配線基板2の上部には、半導体チップを封止する封止キ
ャップ1が設けられ、単一のモジュールが構成される。A sealing cap 1 for sealing a semiconductor chip is provided on the upper part of the wiring board 2, and a single module is configured.
一方、半導体チップを外部回路に接続するため、配線基
板2の表面層及び内層回路配線10を電気的に導通した
金属パッド8が配線基板2の裏面に設けられ、金属バッ
ド8には入出力ピン7がろう接合8aされている。On the other hand, in order to connect the semiconductor chip to an external circuit, a metal pad 8 that electrically connects the surface layer of the wiring board 2 and the inner layer circuit wiring 10 is provided on the back surface of the wiring board 2, and the metal pad 8 has input/output pins. 7 is soldered to 8a.
他方、内層配線をもつプリント基板6において多数のス
ルーホールを設け、コネクタピン5aを挿通しはんだ接
合され、コネクタ5が配置される。On the other hand, a large number of through holes are provided in the printed circuit board 6 having inner layer wiring, and the connector pins 5a are inserted and soldered together, and the connector 5 is arranged.
コネクタ5の開口部に入出力ピン7が挿通、接触される
ことにより、モジュール内部、あるいは、モジュール間
の外部信号伝送が図られる。By inserting and contacting the input/output pin 7 into the opening of the connector 5, external signal transmission within the module or between modules is achieved.
そして、第2図及び第3図を用いて、補修ピン4の接続
法について説明する。補修ピン4の位置の入出力ピンの
補修は以下のように行う。あらかじめ電気絶縁性の支持
板3にプリント基板6で実施されるのと同じ要領で、ス
ルーホールを設け。Next, a method of connecting the repair pin 4 will be explained using FIGS. 2 and 3. The input/output pin at the location of the repair pin 4 is repaired as follows. Through holes are provided in advance in the electrically insulating support plate 3 in the same manner as in the printed circuit board 6.
金属ラント部4bがメツキされ、ここに補修用の入出力
ピン4が挿通され、はんだにより接合固定されている。The metal runt portion 4b is plated, and a repair input/output pin 4 is inserted therethrough and fixed by soldering.
そして、電気絶縁性の支持板3は、補修ピン4に隣接す
る入出力ピン7aに挿通され、補修ピン4が内層配線1
0に押し付け、支持板3が弾性変形する程度に押し付け
た状態で、入出力ピン7aのろう付は部8aに、はんだ
ろう8bによりろう付けし、支持板3を入出力ピン7a
に固定する。はんだろう8bは元のろう材8aより融点
の低いろう材であっても良い。The electrically insulating support plate 3 is inserted into the input/output pin 7a adjacent to the repair pin 4, and the repair pin 4 is inserted into the inner layer wiring 1.
0, and while the support plate 3 is pressed to the extent that it is elastically deformed, the input/output pin 7a is brazed to the part 8a with solder 8b, and the support plate 3 is connected to the input/output pin 7a.
Fixed to. The solder solder 8b may be a brazing material having a lower melting point than the original soldering material 8a.
第4図は、さらに他の実施例を示したもので、補修ピン
の取付は状態を示す断面図である。補修ピン4の電気絶
縁性の支持板3への取付は固定は前述の実施例と同様に
行う。そして、支持板3には、補修ピン4の近傍の入出
力ピン7aを挿通してなる位置決め用の孔が設けられて
いる。支持板3が入出力ピン7aを挿通して、補修ピン
4が内層配線10に位置決めされ、コネクタ5に、補修
ピンを含めすべての入出力ピンが挿入される。この時、
入出力ピン7aとコネクタ5のコンタクト9との接触圧
により、支持板3が固定され、補修ピン4の金属パッド
、あるいは、内部配線部への押付は接続が図られる。FIG. 4 shows still another embodiment, and is a sectional view showing how the repair pin is attached. The repair pin 4 is attached and fixed to the electrically insulating support plate 3 in the same manner as in the previous embodiment. The support plate 3 is provided with a positioning hole through which the input/output pin 7a near the repair pin 4 is inserted. The input/output pin 7a is inserted into the support plate 3, the repair pin 4 is positioned on the inner layer wiring 10, and all the input/output pins including the repair pin are inserted into the connector 5. At this time,
The support plate 3 is fixed by the contact pressure between the input/output pin 7a and the contact 9 of the connector 5, and the connection is achieved when the repair pin 4 is pressed against the metal pad or the internal wiring section.
第5図は、さらに他の実施例を示したもので、補修ピン
の取付は状態を示す断面図である。あらかじめ、配線基
板2の裏面には、本来の金属パッド8と導通した補修用
パッド11が設けられている。一方、補修ピン4のヘッ
ド部にワイヤ4cが取付けられており、ワイヤ4cの他
端が、補修布線のルーティングと同じ要領で、補修用パ
ッド11にボンディング接合する。その後、コネクタ5
のコンタクト9に補修ピン4をワイヤ4cの伸長性を利
用して挿通し、他の入出力ピンをコネクタ5に挿入する
。FIG. 5 shows still another embodiment, and is a sectional view showing how the repair pin is attached. A repair pad 11 electrically connected to the original metal pad 8 is provided on the back surface of the wiring board 2 in advance. On the other hand, a wire 4c is attached to the head portion of the repair pin 4, and the other end of the wire 4c is bonded to the repair pad 11 in the same manner as the repair wiring is routed. After that, connector 5
The repair pin 4 is inserted into the contact 9 using the extensibility of the wire 4c, and the other input/output pin is inserted into the connector 5.
第6図及び第7図は、各々、他の実施例を示す斜視図で
ある。FIG. 6 and FIG. 7 are perspective views showing other embodiments.
第6図に示す実施例では、補修ピン4の支持部材が十字
形状をなし、補修ピン4に隣接する健全な入出力ピン7
aを用い、四本の入出力ピンに支持部材を係留して固定
する。In the embodiment shown in FIG. 6, the support member of the repair pin 4 has a cross shape, and a healthy input/output pin 7 adjacent to the repair pin 4
Using a, the support member is moored and fixed to the four input/output pins.
第7図に示す実施例では、補修ピン4の支持部材3の固
定を、隣接する二本の入出力ピンに係留して固定する。In the embodiment shown in FIG. 7, the repair pin 4 is fixed to the support member 3 by being moored to two adjacent input/output pins.
〔発明の効果〕
本発明によれば、入出力ピンの曲がり、脱落等の破損に
対して、破損入出力ピンの修復を効率的に行うことが出
来、ピングリッドアレイが成立する。結果的に、ピン付
は作業性の向上が図られ、信号接続を極小化する入出力
ピン接続構造が得られ、高性能で、信頼度の高い半導体
パッケージを提供することが出来る。[Effects of the Invention] According to the present invention, damaged input/output pins can be efficiently repaired when the input/output pins are damaged due to bending, falling off, etc., and a pin grid array is established. As a result, the pin attachment improves workability, provides an input/output pin connection structure that minimizes signal connections, and provides a high-performance, highly reliable semiconductor package.
第1図は本発明の一実施例の接続構造の斜視図、第2図
は、補修ピン近傍の詳細を示す斜視図、第3図は、第2
図の1−に矢視断面図、第4図は。
他の補修接続法の実施例を示す断面図、第5図は、本発
明のさらに他の実施例に係る断面図、第6図及び第7図
は、各々、本発明のさらに他の実施例を示す要部斜視図
である。
1・・・封止キャップ、2・・配線基板、3・・・補修
ピン固定部材、4・・・補修ピン、5・・・コネクタ、
6・・・プリント基板、7・・・入出力ピン、8・・・
金属パッド、9・・・コネクタコンタクト、10・・・
内層配線、11栗
図
第
図
図
0
築
団
不
第
図FIG. 1 is a perspective view of a connection structure according to an embodiment of the present invention, FIG. 2 is a perspective view showing details near the repair pin, and FIG.
1- in the figure is a sectional view taken in the direction of arrows, and FIG. FIG. 5 is a cross-sectional view showing an embodiment of another repair connection method, FIG. 5 is a cross-sectional view according to yet another embodiment of the present invention, and FIGS. 6 and 7 are each a further embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Sealing cap, 2... Wiring board, 3... Repair pin fixing member, 4... Repair pin, 5... Connector,
6... Printed circuit board, 7... Input/output pin, 8...
Metal pad, 9... Connector contact, 10...
Inner layer wiring, 11 chestnut diagram diagram 0 construction plan diagram
Claims (1)
されて搭載された配線基板と前記配線基板に外部リード
として多数の入出力ピンを備え、前記配線基板の前記入
出力ピンと接続されて前記配線基板間の信号あるいは外
部電源との接続を図るコネクタ及びプリント基板からな
る半導体装置において、 前記配線基板の既設の前記入出力ピンに係留してなる電
気絶縁性の部材に補修用入出力ピンを固定し、前記配線
基板の既設パッドに前記補修用入出力ピンの接続を図る
ことを特徴とする入出力用ピンの補修接続法。[Claims] 1. A wiring board on which one or more semiconductor chips are electrically connected and mounted, and a large number of input/output pins as external leads on the wiring board, and the input/output of the wiring board In a semiconductor device consisting of a connector and a printed circuit board that are connected to pins to connect signals between the wiring boards or to an external power supply, the electrically insulating member moored to the existing input/output pins of the wiring board is repaired. 1. A repair connection method for input/output pins, characterized in that the repair input/output pins are fixed, and the repair input/output pins are connected to existing pads of the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111A JP2796394B2 (en) | 1990-01-17 | 1990-01-17 | Repair connection method for input / output pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006111A JP2796394B2 (en) | 1990-01-17 | 1990-01-17 | Repair connection method for input / output pins |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03211760A true JPH03211760A (en) | 1991-09-17 |
| JP2796394B2 JP2796394B2 (en) | 1998-09-10 |
Family
ID=11629394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006111A Expired - Fee Related JP2796394B2 (en) | 1990-01-17 | 1990-01-17 | Repair connection method for input / output pins |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2796394B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102382A (en) * | 1991-10-11 | 1993-04-23 | Nec Corp | I / O pin repair structure and repair method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226048U (en) * | 1985-07-31 | 1987-02-17 | ||
| JPH01211878A (en) * | 1988-02-19 | 1989-08-25 | Fujitsu Ltd | Rehabilitation of i/o pin |
| JPH0346780A (en) * | 1989-07-12 | 1991-02-28 | Fujitsu Ltd | Restoration method of i/o pin |
-
1990
- 1990-01-17 JP JP2006111A patent/JP2796394B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226048U (en) * | 1985-07-31 | 1987-02-17 | ||
| JPH01211878A (en) * | 1988-02-19 | 1989-08-25 | Fujitsu Ltd | Rehabilitation of i/o pin |
| JPH0346780A (en) * | 1989-07-12 | 1991-02-28 | Fujitsu Ltd | Restoration method of i/o pin |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102382A (en) * | 1991-10-11 | 1993-04-23 | Nec Corp | I / O pin repair structure and repair method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2796394B2 (en) | 1998-09-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |