JPH03212083A - High efficiency coding device - Google Patents

Abstract

PURPOSE:To prevent occurrence of mis-matching between an encoder and decoder sides by applying quantization depending an allocated bit number decided through the comparison of a threshold level decided by buffering processing based on the corrected dynamic range with the corrected dynamic range itself. CONSTITUTION:The setting of threshold levels T1'-T4' to make the quantity of calculation of generated information quantity and the generated information quantity to a prescribed value or below are implemented by a buffer circuit 26 based on a corrected dynamic range DR'. The set threshold levels T1'-T4' and the corrected dynamic range DR' are compared and the resulting comparison output is used to decide a 2nd allocated bit number n' of a coding circuit 23. Thus, the occurrence of mis-matching between an encoder and decoder sides is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device for compressing the number of bits per pixel of image data such as a digital television signal.

[Summary of the Invention] The present invention provides a method for calculating the maximum and minimum values of a plurality of pixel data contained within a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames. a circuit that calculates the value and detects the original dynamic range of each block from the maximum value and the minimum value;
calculating the amount of information generated in a predetermined period based on the original dynamic range, and controlling a threshold value for setting the first number of allocated bits of each block so that the amount of generated information is within the predetermined amount of data; means for setting a first allocated number of bits for each block by a comparison output comparing a threshold value and an original dynamic range of each block; and a means for setting the original dynamic range to a plurality of level ranges corresponding to the first allocated bit number The input image data included in the maximum level range and the minimum level range when divided are extracted, and the first part of the input image data included in the maximum level range is extracted.
a circuit that forms a second average value of the input image data included in the average value and the minimum level range of the input image signal; an encoding circuit that subtracts a second average value from the subtracted value and encodes the subtracted output according to the second allocated focus number and the corrected dynamic range, and an amount of information generated in a predetermined period based on the corrected dynamic range. The threshold value for setting the second allocated bit number of each block is calculated so that the amount of generated information is within a predetermined amount of data, and the second allocated bit number of each block in the encoding circuit is calculated. and a circuit for setting the number based on a comparison output comparing a threshold value and the corrected dynamic range, and transmits information related to the corrected dynamic range and an output code of the encoding circuit, Block distortion due to ringing and impulse noise can be prevented, and the amount of information generated by variable length ADRC can be correctly controlled.

[Conventional technology]

As video signal encoding methods, several high efficiency encoding methods are known in which the average number of bits per pixel or the sampling frequency is reduced in order to narrow the transmission band.

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and A high-efficiency encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in the specification of Japanese Patent Application No. 6C)-268817, there is a variable length encoding method in which the number of bits is converted according to the dynamic range so that the maximum distortion caused when quantization is constant. is proposed.

FIG. 7 is used to explain the previously proposed encoding method adapted to the dynamic range (referred to as ADRC). For example, the dynamic range DR (difference between maximum value MAX and minimum value MIN) is (8 lines x 8 pixels - 64
It is calculated for each two-dimensional block consisting of pixels). Also, the lowest level (minimum value) within the block is removed from the input pixel data. The pixel data after this minimum value has been removed is converted to a representative level. This quantization divides the detected dynamic range DR into four level ranges AO to A3 corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and divides the detected dynamic range DR into four level ranges AO to A3 to which each pixel data in the block belongs. This is a process that detects the level range and generates a code signal indicating this level range.

In FIG. 7, the dynamic range DR of the block is divided into four level ranges AO to A3. Pixel data included in the minimum level range AO is encoded as (00), pixel data included in level range A1 is encoded as (01), and pixel data included in level range A2 is encoded as (00).
pixel data included in the maximum level range A3 is encoded as (11). Therefore, 8-bit data of each pixel is compressed into 2-bit data and transmitted.

On the receiving side, the received code signal is at the representative level LO-
Restored to L3. The representative levels LO to L3 are the respective center levels of the level range AO to A3.

The above-mentioned encoding method adapted to the dynamic range has a problem in that block distortion occurs due to ringing and impulsive noise. FIG. 8 is a diagram for explaining the occurrence of block distortion. In Figure 8, for ease of explanation,
Changes in data for a one-dimensional block, that is, a block formed by a predetermined number of samples in the horizontal direction, are represented as analog waveforms, and the restored values on the receiving side are shown by broken lines.

As shown in FIG. 8, a small level of ringing often occurs in the image output of a video camera near edges where the level changes sharply. In a block including this ringing, the peak value of the ringing is detected as the maximum value MAXI, and encoding is performed in accordance with the dynamic range DR1 determined by the minimum value MINI. In the next block, since the ringing is concentrated, the maximum value decreases as shown by MAX2, and encoding is performed in accordance with the dynamic range DR2 determined by the minimum value MIN2 and the maximum value MAX2. Therefore, a difference in brightness level occurs between these two blocks, causing block distortion. Block distortion also occurs in the case of impulsive noise for the same reason. Although the difference in luminance level of the block distortion described above is small, it has a certain area, so there is a visually noticeable problem.

In order to solve the problem of the occurrence of block distortion due to ringing and impulsive noise described above, the applicant of the present application has developed an input method that is converted into a block structure as described in Japanese Patent Application No. 61-202118. We propose a method for preprocessing data. In other words, the average value MAX' of the input data values included in the maximum level range (A3 in Figure 7) when the dynamic range is equally divided by the number of ADRC quantization bits, and the minimum level range (A3 in Figure 7). As shown in FIG. 9, the average value MAX' of the input data contained in
and average value MIN" are respectively set as restoration levels L3 and LO. As shown in FIG. 7, representative levels LO to L3 do not include maximum value MAX and minimum value MIN, and each level Quantization that takes the median value of the range is called non-edge matching, and as shown in Figure 9, the average value M
Quantization involving AX' and MIN'' is called edge matching.

In ADRC, which is preprocessed by the above-mentioned non-edge matching and quantized by edge matching, in FIG. 8, even in a block that includes ringing, the maximum value is changed to the average value MAX' instead of the ringing peak. , similarly the minimum value is changed to MIN'. This MAX' and M
Since the edge matching quantization is performed within the modified dynamic range DR'' determined by IN'', the difference between the restoration level and the restoration level of adjacent blocks is reduced, and block distortion is prevented from occurring.

ADRC encoding adapted to the above-mentioned dynamic range can significantly compress the amount of data to be transmitted, and is therefore suitable for application to digital VTRs.

In particular, variable length ADRC can increase the compression ratio. However, with variable length ADRC, the amount of data to be transmitted varies depending on the image content, so when using a fixed rate transmission path such as a digital VTR that records a predetermined amount of data as one track, buffering processing is required. Needed.

As a buffering method for variable length ADRC, the applicant of the present application forms a cumulative dynamic range frequency distribution, as described in Japanese Patent Application No. 61-257586, and calculates the frequency distribution for this frequency distribution. , applies a threshold value prepared in advance to determine the number of allocated bits, calculates the amount of information generated during a predetermined period, for example, one frame period, and controls the amount of generated information so that it does not exceed the target value. is proposed.

[Problems to be Solved by the Invention] As described above, ADRC performs preprocessing using non-edge matching quantization, and then performs quantization using edge matching.
On the other hand, when variable length ADRC is applied, the original dynamic range DR used to set the number of allocated bits, and the modified dynamic range DR used when encoding with this allocated number of bits and transmitted to the receiving side. Since the dynamic ranges DR' are different, a problem of mismatch between the encoder side and the decoder side has arisen.

That is, in order to control the amount of generated information, a frequency distribution table is formed for a predetermined period of the dynamic range DR, for example, one frame period, and this frequency distribution table is converted into a cumulative frequency distribution table. T1, T2, T3, T4 (
A threshold of Tl<T2<T3<T4 is applied. (
When DR<Tl), the number of allocated bits n is set to O (that is, no code signal is transmitted), and (Tl≦DR<
T2), (n=1) and (72≦DR<
73), (n=2) and (T3≦DR<
In the case of T4), (n=3) and (T4≦DR)
In this case, (n=4).

As mentioned above, (MAX ” − M I N ′ − D
R'), and this corrected dynamic range DR
', quantization is performed based on the dynamic range DR
' is transmitted. Regarding the dynamic range of a certain block, (T2≦DR<73) and (T2≦DR'<T
If the relationship 3) holds, on the encoder side, (n
= 2), and (n = 2) on the decoder side, so no problem occurs.

However, since (DR>DR'), (Tl≦DR
If '<72), the decoder side incorrectly determines that (n=1), causing a problem in which the correct decoding operation is not performed.

In order to solve this problem, the applicant proposed a method of transmitting an additional code indicating that an inconsistency occurs (Japanese Patent Application No.
-189888). In this method, since the additional code is transmitted, there is a risk that the compression of the transmitted data will be insufficient.

Also, by looking at the original dynamic range DR and performing buffering processing, the threshold values Tl to T4 are determined,
A predetermined level range from the maximum value and minimum value is determined using the threshold values T1 to T4 and the original dynamic range DR,
Furthermore, a method (see Japanese Patent Application No. 1-189889) of determining the number of allocated bits for encoding from the corrected dynamic range DR' and threshold values T1 to T4 has been proposed. In this method, buffering is performed based on the original dynamic range DR, so there is a risk that the amount of data will be compressed more than necessary and the transmission rate will be wasted.

Furthermore, a predetermined level range from the maximum value and minimum value is determined based on the maximum allocated bit number for the original dynamic range DR, and the modified dynamic range DR'
By performing buffering processing, the threshold value T
1 to T4 and perform encoding using this threshold value and the corrected dynamic range DR' (Japanese Patent Application No.
189886). in this way,
To form the corrected dynamic range DR',
Since the maximum number of allocated bits is always used, the predetermined level range is quite narrow for blocks with a small dynamic range DR, and the advantages of the hybrid configuration of non-edge matching quantization and edge matching quantization are fully utilized. There was a risk that it would not be possible.

Therefore, an object of the present invention is to improve the original dynamic range DR.
The level range is set by comparing the threshold value determined in the buffering process based on the original dynamic range DR, and the level range is set by comparing the threshold value determined in the buffering process based on High efficiency that prevents mismatch between the encoder and decoder sides by performing quantization using the number of allocated bits determined by comparing the determined threshold and the corrected dynamic range DR' An object of the present invention is to provide an encoding device.

Another object of the present invention is to provide a high-efficiency encoding device that does not require transmitting additional codes, does not waste transmission rates, and can fully utilize the advantages of hybrid quantization. It is in.

(Means for Solving the Problems) The present invention provides the maximum value of a plurality of pixel data contained within a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames. Find the MAX and minimum value MIN, and also calculate the maximum value MA
A maximum value/minimum value detection circuit 3 detects the original dynamic range DR for each block from Thresholds T1 to T4 for setting the first allocated bit number n of each block are controlled so that the first allocated bit number n of each block is set within the thresholds T1 to T.
4 and the original dynamic range DR of each block. The input image data included in the maximum level range and the minimum level range are extracted, and the first average value MAX' of the input image data included in the maximum level range and the input image data included in the minimum level range are calculated. A circuit 5.6.7.8.10.11.12.13 forming a second average value MIN' and a dynamic range DR modified from the first average value MAX' and the second average value MIN'', subtracts the average value MIN' from the input image signal, and encodes the subtracted output according to the second allocated bit number n' and the corrected dynamic range DR'; A threshold value for calculating the amount of generated information in a predetermined period based on the dynamic range DR' and setting the second number of allocated bits n' for each block so that the amount of generated information is within the predetermined amount of data. Tl'～T4
” of each block in the encoding circuit 23.
means 24.25.26 for setting the number of allocated bits n' of the modified dynamic range by comparing the threshold value TI' to T4' with the modified dynamic range DR' of each block; DR' and related information,
It is for transmitting the output code of the encoding circuit 23.

[Effect]

Since the television signal has three-dimensional correlation in the horizontal direction, vertical direction, and time direction, the range of change in the level of pixel data included in the same block is small in the stationary portion. Therefore, even if data after removing the minimum level shared by pixel data in a block is quantized with a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs.

Furthermore, the average values MAX' and MIN of pixel data included in the maximum level range defined by the maximum value MAX and a value that is a predetermined level lower than MAX, and the minimum level range defined by the minimum value MIN and a value that is a predetermined level higher than MIN, respectively. By detecting the average value and performing edge matching quantization using the average value as a new maximum value and minimum value, generation of block distortion due to ringing, impulse noise, etc. can be prevented.

A buffering circuit 16 is provided to set a maximum level range and a minimum level range corresponding to the first allocated bit number n. Buffering circuit 16
is the threshold value T1 based on the original dynamic range DR.
.about.T4 is determined, and the first allocated bit number n is determined from the threshold values T1 to T4 and the original dynamic range DR. Therefore, the number of bits n is determined in accordance with the dynamic range DR of the block.

Calculation of the amount of generated information and setting of threshold values T1' to T4'' for keeping the amount of generated information below a predetermined amount are performed by the buffering circuit 2 based on the corrected dynamic range DR.
It is done in 6. Based on the comparison output that compares this set threshold value and the corrected dynamic range DR',
Since the second allocated bit number n' of the encoding circuit 23 is determined, mismatch between the encoder side and the decoder side can be prevented.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. This description is given in the following order.

a. Configuration of the transmitting side; Configuration of the receiving side; C; Buffering circuit d; Modification a; Configuration of the transmitting side FIG. 1 shows the overall configuration of the transmitting side (recording side) of the present invention. . For example, a digital video signal in which one sample is quantized to 8 bits is input to the input terminal indicated by ■.
A digital luminance signal) is input. This digital video signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding. In this embodiment, one block has a size of (8 lines x 8 pixels = 64 pixels) as shown in the second section. The output signal of the blocking circuit 2 is supplied to a maximum value/minimum value detection circuit 3 and a delay circuit 4. Maximum value,
The minimum value detection circuit 3 detects the minimum value MIN and maximum value MAX for each block. The delay circuit 4 delays the input data by the time required for the maximum and minimum values to be detected. Pixel data from the delay circuit 4 is supplied to a comparison circuit 5 and a comparison circuit 6.

The maximum value MAX from the maximum value/minimum value detection circuit 3 is supplied to a subtraction circuit 7, and the minimum value MIN is supplied to an addition circuit 8. These subtracting circuits 7 and adding circuits 8 are supplied with a value Δ of one quantization step width when non-edge matching quantization is performed with variable length from a bit shift circuit 9. The bit shift circuit 9 is configured to shift the dynamic range DR by n bits so as to perform division by (DR/2'') when the first allocated bit number is n.

The subtraction circuit 7 obtains a threshold value of (MAX-Δ), and the addition circuit 8 obtains a threshold value of (MIN+Δ). The threshold values from these subtraction circuit 7 and addition circuit 8 are supplied to comparison circuits 5 and 6, respectively.

The output signal of the comparator circuit 5 is supplied to an AND gate 10,
The output signal of the comparator circuit 6 is supplied to an AND game (1). Input data from the delay circuit 4 is supplied to AND gates 10 and 11. The output signal of the comparison circuit 5 becomes high level when the input data is larger than the threshold value, and therefore, the output terminal of the AND gate 10 has (MAX-M
Pixel data of input data included in the maximum level range of AX-Δ) is extracted. The output signal of the comparison circuit 6 becomes high level when the input data is smaller than the threshold value, and therefore, the output terminal of the AND gate 11 has (MIN-M
Pixel data of input data included in the minimum level range of IN+Δ) is extracted.

The output signal of the AND gate 10 is supplied to an averaging circuit 12, and the output signal of the AND gate 11 is supplied to an averaging circuit 13. These averaging circuits 12 and 13 calculate an average value for each block, and a reset signal of the block period is supplied to the averaging circuits 12 and 13 from the terminal 4. From the averaging circuit 12, (MAX-MAX-
Average value MA of pixel data belonging to the maximum level range of Δ)
X'' is obtained, and from the averaging circuit 13, (M I N ~
The average value MIN'' of pixel data belonging to the minimum level range of MIN+Δ) is obtained. From the average value MAX' to the average value M
IN' is subtracted by a subtraction circuit 15, and a corrected dynamic range DR' is obtained from the subtraction circuit 15.

In order to optimize the above-mentioned first allocated bit number n for each block, a buffering circuit indicated by 16 is provided. This buffering circuit 16 determines threshold values T1-T4 for setting the amount of generated information to a predetermined value based on the original dynamic range DR. In the buffering circuit 16, a set of threshold values (Tl, T2, T3, T
4) are prepared, for example, 32 sets, and these sets of threshold values are the parameter code Pi (i=0.1°2
,...,31). Parameter code P
It is set so that as the number i of i increases, the amount of generated information decreases monotonically.

However, as the amount of generated information decreases, the quality of the restored image deteriorates.

A comparison circuit 18 to which the threshold values T1 to T4 from the buffering circuit 16 and the dynamic range DR from the subtraction circuit 17 are supplied, calculates the dynamic range D of the block.
R and each threshold value are compared, and the comparison output is supplied to the bit number determining circuit 19, which determines the number n of bits to be allocated to the block. The bit shift circuit 9 shifts the dynamic range DR according to the number n of allocated bits.

Further, the average value MIN' is supplied to the subtraction circuit 20, and the average value MIN'' is subtracted from the input data via the delay circuit 21 in the subtraction circuit 20, and the data P after the minimum value is removed is
A DI is formed. Data PD passed through delay circuit 22
I and the modified dynamic range DR" are supplied to the quantization circuit 23. In this embodiment, the second allocated bit number n' for quantization is 0 bit (no code signal is transmitted), 1 bit , 2 bits, 3 bits, or 4 bits, and edge matching quantization is performed.The second allocated bit number n' is determined by the bit number determining circuit 24 for each block. , the number of bits n data is supplied to the quantization circuit 23.

The output signal of the comparison circuit 25 is supplied to the bit number determination circuit 24 . The comparison circuit 25 receives the corrected dynamic range DR' from the subtraction circuit 15 and the threshold values T1 to T4'(Tl''<T2) from the buffering circuit 26.
'<T3'<T4') is supplied. The number of allocated bits n is determined based on the relationship between the dynamic range DR' and the threshold values Tl'' to T4'.

The buffering circuit 26 performs the same buffering as the buffering circuit 16 described above. That is, (DR”<
In the block Tl'), no code signal is transmitted, and only the dynamic range DR'' and the average value MIN' are transmitted, and in the block (T1'≦DR''<T2''), the code signal is not transmitted.
= 1), and the process of (T2'≦DR'<73'') is (n'=2), (T3'≦DR''<74')
The block is (n''=3), and (DR'≧T4'
), the allocated bit number n' determined in this way and the corrected dynamic range DR', where n'=4, are supplied to the quantization circuit 23. In the quantization circuit 23, the data PDI after minimum value removal is converted into a code signal DT by edge matching quantization using the dynamic range DR'' and the allocated bit number n'. It is configured.

In such variable length ADRC, the amount of generated information can be controlled (so-called buffering) by changing the threshold values Tl' to T4'. Therefore, the amount of generated information per field or frame can be controlled to a predetermined value. The buffering circuit 26 determines the threshold values Tl' to T4' that can be used.

The dynamic range DR' and the average value MIN'' modified through the delay circuits 27 and 28 are sent to the frame forming circuit 2.
9, and a parameter code Pi' indicating a set of a code signal DT and a threshold value is also supplied to a framing circuit 29. At the output terminal 30 of the framing circuit 29,
Transmission data converted to serial data is extracted. In the framing circuit 29, an error correction code is encoded as necessary, and a synchronization signal is added.

b. Receiving side configuration FIG. 3 shows the configuration on the receiving (or reproducing) side.

The received data from the input terminal 31 is sent to the frame decomposition circuit 3.
2. The frame decomposition circuit 32 separates the code signal DT and additional codes DR", MIN", and Pi', and performs error correction processing.

The code signal DT, the dynamic range DR'' and the parameter code Pi' are supplied to the decoding circuit 33. In the decoding circuit 33, a set of threshold values indicated by the parameter code Pi' is generated. is compared with the dynamic range DR' in the comparison circuit in the decoding circuit 33, thereby obtaining the allocated bit number n'. Edge matching decoding is performed from this allocated bit number n', the dynamic range DR', and the code signal DT. is performed, and the code signal DT is decoded to a representative level.

Further, the average value MIN' is supplied to the adder circuit 34. The output signal of the decoding circuit 33 is supplied to the addition circuit 34, and the output signal of the addition circuit 34 is supplied to the block decomposition circuit 35. The block decomposition circuit 35 is a circuit for converting the restored data in the order of the blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side.

A decoded video signal is obtained at the output terminal 36 of the block decomposition circuit 35.

C. Buffering Circuit FIG. 4 shows an example of the buffering circuit 16. The buffering circuit 16 is provided with a memory (RAM) indicated by 41 in order to create a frequency distribution table and a cumulative frequency distribution table, and an address is supplied to this memory 41 via a multiplexer 42. The dynamic range D is input from the input terminal 43 as one input of the multiplexer 42.
R is supplied, and the address from the address generation circuit 50 is supplied as the other input. The output signal of the adder circuit 44 is input to the memory 41, and the output data of the memory 41 and the output of the multiplexer 45 are added together by the adder circuit 44.

The output of the adder circuit 44 is supplied to a register 46, and the output of the register 46 is supplied to a multiplexer 45 and a comparator circuit 47. The multiplexer 45 is supplied with O and +1 in addition to the output of the register 46. When the amount of generated information is calculated, the amount of information Ai generated in one frame period, for example, is determined from the output of the register 46.

In the comparison circuit 47, the generated information amount At is compared with the target value Q from the terminal 48, and the output signal of the comparison circuit 47 is supplied to the parameter code generation circuit 49 and the register 51. Parameter code Pi from parameter code generation circuit 49 is supplied to address generation circuit 50 and register 51. The parameter code Pi taken into the register 51 is supplied to the ROM 52. The ROM 52 stores a set of threshold values (Tl i, T2 i, T3 i, T4i) corresponding to the parameter code Pi input as an address.
occurs. This threshold value is supplied to comparator circuit 18, as described above.

FIG. 5 is a flowchart showing the operation of the buffering circuit 16. In a first step 61, the memory 41,
Register 46 is cleared to zero.

For clearing the memory 41 to zero, the multiplexer 42
selects the address generated by the address generation circuit 50,
The output of the adder circuit 44 is always set to O. The address is (
0, l, 2. . . , 255), and O data is written to all addresses of the memory 41.

In the next step 62, the dynamic range D of one frame, which is a unit period buffered in the memory 41, is
A frequency distribution table of R is created. The multiplexer 42 is
Dynamic range DR from terminal 43 is selected, and multiplexer 45 selects +1. Therefore, when one frame period is about to end, the frequency of occurrence of each DR is stored in each address of the memory 41 corresponding to the dynamic range DR. The frequency distribution table in the memory 41, as shown in FIG. 6A, has DR as the horizontal axis and frequency as the vertical axis.

Next, the frequency distribution table is converted into a cumulative frequency distribution table (step 63). When creating a cumulative frequency distribution table, multiplexer 42 selects the address from address generation circuit 50, and multiplexer 45 selects the output of register 46. The address decrements sequentially from 255 to 0.

The readout output of the memory 4I is supplied to the adder circuit 44,
The adder circuit 44 adds the contents of the register 46. The output of the adder circuit 44 is written to the same address as the read address of the memory 41, and the contents of the register 46 are updated to the eight values of the adder circuit 44. In the initial state where the address of the memory 41 is set to 255, the register 46 is cleared to zero. When the frequencies are accumulated for all addresses in the memory 41, the memory 41 stores the information shown in FIG. 6B.
The cumulative frequency distribution table shown in is created.

For this cumulative frequency distribution table, a set of threshold values (T1 t,
The amount of information Ai generated when T2 i, T3 i, T4 i) is applied is calculated (step 64).

When calculating the generated information amount Ai, the multiplexer 42 selects the output of the address generation circuit 50, and the multiplexer 4
5 selects the output of register 46.

The parameter code generation circuit 49 generates parameter codes that change sequentially from PO to P31. Parameter code Pi is supplied to address generation circuit 50,
Addresses corresponding to each threshold value (Tl i, T2 i, T3 i, T4i) are generated sequentially. Values read from addresses corresponding to each threshold value are accumulated by an adder circuit 44 and a register 46. This cumulative value corresponds to the amount of information Ai generated when the set of threshold values specified by the parameter code Pi is applied. That is, in the cumulative frequency distribution table shown in FIG. 6B, the threshold values T1, T2, T3,
The value At read from the address corresponding to T4,
Total value of A2, A3, A4 (A1+A2+A3+A4)
, the value multiplied by the number of pixels in the block (64) is
However, since the number of pixels is constant, the buffering circuit 21 shown in FIG.
In this example, the 64 multiplication process is omitted.

The generated information amount Ai is compared with the target value Q (step 65), and the output of the comparison circuit 47, which is generated when (Ai≦Q) holds, is supplied to the parameter code generation circuit 49 and the register 51, and the parameter code Pi The increment of is stopped, and the parameter code Pi is taken into the register 51. The parameter code Pi from the register 51 and the set of threshold values generated in the ROM 52 are output (step 66).

At step 65 of determination in the comparison circuit 47, (Ai≦
When Q) does not hold, the parameter code Pi is changed to the next one, P i+1, and the address corresponding to P i+1 is generated from the address generation circuit 50. The generated information amount A i+1 is calculated in the same manner as described above, and compared with the target value Q in the comparison circuit 47. The above-mentioned operation is repeated until (Ai≦Q) is established.

The buffering circuit 26 also has a similar configuration to the buffering circuit 16 described above. However, buffering circuit 1
In step 6, the amount of generated information is calculated based on the corrected dynamic range DR''.Furthermore, the parameter code Pi' corresponding to the determined threshold values TI' to T4' is sent to the framing circuit 29. Output.

d. Modification In the above explanation, the code signal DT, dynamic range DR', and average value MEN' are transmitted. However, the average value MAX'' or the quantization step width may be transmitted instead of the dynamic range DR'' as an additional code.

〔Effect of the invention〕

According to the present invention, it is possible to prevent block distortion from occurring in blocks containing ringing, impulsive noise, and the like. In this invention, encoding can be performed efficiently using variable length ADRC, and since the dynamic range used for controlling the amount of generated information and quantization is different, the number of allocated bits is different between the encoder side and the decoder side. Different inconsistencies can be prevented. Furthermore, the present invention does not require additional codes and there is no risk of insufficient data compression.Furthermore, the present invention can effectively utilize transmission rates. Furthermore, according to the present invention, the maximum level range and the minimum level range can be set according to the dynamic range DR of the block, so that hybrid encoding can be performed effectively.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a line diagram of an example of the block, Fig. 3 is a block diagram showing an example of the configuration of the receiving side, and Fig. 4 is an example of a buffering circuit. The block diagram of FIGS. 5 and 6 is a flowchart and route map used to explain the buffering circuit, and FIGS.
9 and 9 are route charts used to explain the quantization operation and the occurrence of block distortion. Explanation of main symbols in the drawings 1: Input terminal, 3: Maximum value, minimum value detection circuit, 7sfIi arithmetic circuit, 8: Addition circuit, 9: Bit shift circuit, 12.13: Averaging circuit, 16: Buffering circuit , 23: Quantization circuit, 24: Bit number determining circuit to be allocated to the quantization circuit, 26: Buffering circuit, 29: Framing circuit, 30: Output terminal. emit number of hits

Claims (1)

[Scope of Claims] Determining the maximum and minimum values of a plurality of pixel data contained within a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames, and means for detecting the original dynamic range for each block from the maximum value and the minimum value; and calculating the amount of generated information in a predetermined period based on the original dynamic range so that the amount of generated information is within a predetermined amount of data. A threshold value for setting the first allocated bit number of each block was controlled, and the above first allocated bit number of each block was compared with the above threshold value and the above original dynamic range of each block. means for setting by comparison output, and extracting input image data included in the maximum level range and the minimum level range, respectively, when the original dynamic range is divided into a plurality of level ranges corresponding to the first allocated bit number. means for forming a first average value of the input image data included in the maximum level range and a second average value of the input image data included in the minimum level range; A corrected dynamic range is calculated from the second average value, the second average value is subtracted from the input image signal, and the subtracted output is calculated according to the second allocated bit number and the corrected dynamic range. an encoding means for encoding, and calculating the amount of generated information in a predetermined period based on the corrected dynamic range, and the second allocation of each block so that the amount of generated information is within a predetermined amount of data. controls the threshold for setting the number of bits,
means for setting the second allocated number of bits for each block in the encoding means using a comparison output that compares the threshold with the modified dynamic range of each block; 1. A high-efficiency encoding device, characterized in that information related to the encoding means and an output code of the encoding means are transmitted.