JPH03214204A - programmable controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a programmer full controller that allows easy modification and modification of programs. Japanese Patent Publication No. 61-21392
There is a program change method as described in No. 8. In this method, a program for addition and modification is created in a separate area from the program currently being executed, and the program in the separate area is not executed when additions and modifications are made. [Problem to be Solved by the Invention] However, the above-mentioned conventional technology is not suitable for modifying a part in the middle of a program. In other words, (the modification work is completed as expected)
) I tried actually running Progera l, and found the problem, but the problem was in the middle of the block. If you try to execute a change using the conventional technology, the problem will be brought to an area separate from the main body of the block, so you will need a separate area (7), and when you run the program after the change, you will need to specify the branch point address and branch destination. Since addresses are stored in registers and controlled according to the contents, the memory capacity increases and preparation work for changes and control operations become complicated.If there are many parts to change, this complexity becomes unbearable. An object of the present invention is to provide a sequence controller that can easily modify a program without stopping the program currently being executed. In order to solve the purpose, the branch start address and branch destination address, which respectively indicate the front and rear parts of the program modification area, are stored in a branch control table. The branch start address is compared with the branch start address in the arithmetic unit, and when the two have a certain relationship, the branch destination address is transferred to the program counter above, and the program is executed continuously without stopping, skipping the modified part in the middle of the program. Furthermore, (1! The program is stored in memory with a flag at the front of the main area, and the above 1.

[1 position where the last part of the positive enoa is the branch destination address and corresponds to the above flag in the branch control table The branch control table is moved to the above program counter, and the program is configured so that the correction part in the middle of the program is skipped and the calculation is executed continuously without stopping. Write down the address that specifies the correct enoa, and write down multiple keys if necessary.By doing so, you can correct the necessary part at the original location in the middle of Progera J1. The branch address in the branch control table is 1 of Procla J1.
It is necessary only on the hour, and after the corresponding part is corrected, the calculation execution starts as soon as it is deleted, and at the same time it becomes possible to set another new 11) positive. Furthermore, when actually running the entire program, the branch control table is not used, so
Operation becomes simple. [Example] The present invention will be described in detail below. FIG. 1 shows the first embodiment of the present invention.
In the block configuration diagram of the embodiment, 1 is a block memory that stores programs including various sequence instructions, 2 is a program counter that indicates the storage address in the block memory of instructions to be executed, and 3 is an instruction to be executed. 4 is a branch control table that stores the branch start address and branch destination address (both will be described later) in the block memory; 5 is an arithmetic unit including parts surrounded by corruption; 6 is a Program counter 2 and branch control table l■
It includes a differentiation/k control table control unit that controls the comparison of the branch start address of 11 The branch address taken out by Ube 6 is written to the branch control section, and the counter 1 remains unchanged.
, a counter update control unit, 51 is an instruction extraction unit that takes out instructions without execution from the block memory 1, IO is an arithmetic unit that performs calculations based on arithmetic instructions, and 11 reads data from the input unit and internal data memory and outputs it. section and internal data memory (data input/output system 1ll that controls the old data)
Sections 11 and 12 are human power sections that convert external signals into data;
1:3 is an internal data memory that stores the results of the performance W in progress,
14 is an output unit that converts the data into external No. 18. FIG. 2 is a block diagram of the branch control table control section 6. 6a is a comparison section that compares the address from the program counter 2 and the branch start address extracted from the branch control table 4. , and outputs either a match signal or a mismatch signal as a result. Reference numeral 6b designates the branch start address to be fetched from the table 4, and also updates the position when receiving the mismatch signal. 6c is a branch start address extractor that extracts the branch start $j+!! from the position specified by the two-leg extractor position updater 6b, and the branch start address extractor 6c extracts the branch start address from the position specified by the two-leg extractor position updater 6b.
Sequentially supply to a. Reference numeral 6d denotes a branch destination address extraction unit that extracts a branch destination address corresponding to the branch start address that is a comparison target when a match occurs in the comparison unit C3a. Figure 3 shows the leap between the two-legged memory and the branch control table 4 (!
It is an explanatory diagram showing . 1a is the instruction at address m in memory 1, I b is the instruction at address n, and lc is the same < 1
This is an instruction at address 1 + 1, and the above m and n addresses specify the 11th tomajo area (part to be changed) of the program. 4a is address m (corresponding to address m of memory 1) stored in the branch control table 4 as a branch start address, and 4b is a branch destination address corresponding to address m, which is stored in the branch destination table 4 as a - mark. It is address n (corresponding to address +1 of memory l). Fig. 1 is a flowchart of the operation of the program in the memory 1 in memory 1, and Fig. 5 shows the change in the program during execution of the program in the memory 1 (while the device is running)
x positive) is a flow diagram. Next, we will explain the operation of correcting part of the program memory 1 being executed (1z). In the above configuration, from address m of program memory 1 to
Assume that address 1-1 is the target of change ((j1 primary area), and that no conflict will occur even if the n address at the top of 011 is adjacent when executing a series of programs. First, branch control The comparison unit C>a in the table-based iaj unit 6 stores the program counter 2 and the branch control table 4ζ, and sequentially compares all branch start addresses (step I 00 in FIG. 1). If there is no match, a mismatch signal is generated, the movement of the takeout unit 6 is prohibited, and the branch control table control unit 6
does nothing to the program counter. The instruction fetch unit 9 reads the block commanded by the program counter 2.
Step 200) of retrieving an instruction from an address in Cochram memory 1. Next, the instruction retrieval section 9 activates the instruction decoding section 3 and at the same time activates the program update control section 8 to update the program counter 2. As a result, the program counter 2 is retrieved from the program memory 1. It will point to the next address after the command. If the program counter 2 reaches address m and matches the branch start address l↓a, the comparator 6a generates a match signal and the extractor 6d operates to extract the corresponding branch destination address 4b(n) from the branch control table 4. Address) and branch control unit 7
moves this to program counter 2. Instruction retrieval unit 9
is address 11 indicated by program counter 2 at that time.
, that is, the instruction 1b from the block memory at the branch destination address. Next, the instruction fetch section 9 operates the program counter update control section 8 in parallel with operating the instruction decoding section 3 to update the program counter 2, and as a result, the program counter 2 is read out from the block memory 1. Indicates address n+1 of the instruction 1c following the instruction 1b. In this way, addresses from nl to n-1 will be bypassed and not executed.Next, change the program from addresses I'n to n-1 (step 300 in Figure 5).End the modification. After that, check the syntax of the blockrum (step 400 in Figure 5). If there is a syntax error, edit the program from address 1 to address n-1 again. Next, check the syntax and the program ends normally. If so, the branch start address 4a and branch destination address t↓1) of the branch 1ial 1 are rewritten to valid values, for example all 0 (step 500). With this -), from m to f
)-1 address is included, and the program change during operation is completed. According to the above embodiment, the program can be changed without stopping the execution of the entire program, and even if the block diagram is changed illegally, there is no abnormal stoppage. In the above embodiment, the program counter 2 is
Since all of the branch start addresses in the branch control table 4 are compared with each other, there is a waste of time. Therefore, a second embodiment will be described below in which a flag is preliminarily provided in the program memory 1 to indicate whether the comparison is to be performed, and the comparison is performed only when the flag is set. 7JtJG is a flowchart of the instruction execution operation in the second embodiment. Figure 7 shows the relationship between program memory 1, branch, and VI# table...1 in this embodiment, where 1d is the instruction at address I+111, e is the flag for the instruction at address 11, and 4c is the start of branching. Branch control table 1 as address
4d is the address 11111 of the program memory 1 stored in the branch destination address 1, and 4d is the address 11 of the program memory 1 stored in the branch control table 41 as the branch destination address. It is assumed that addresses 01 to n] of the program memory 1 are to be changed, and that no contradiction occurs when blockograms are executed adjacently at addresses m and r1. First, the instruction fetch section 9 inside the calculation section 5 fetches an instruction from the program memory 1 at the address indicated by the program counter 2. If the instruction fetching section 9 does not have a flag set on the fetched instruction, it passes it to the instruction decoding section 3 and operating the instruction decoding section 3. Also, in parallel with this, the program counter update control section 8 is operated to update the program counter 2, and as a result, the program counter 2 becomes the program memory 1.
This will point to the next address of the instruction retrieved from. When the program counter 2 reaches address m, the flag 1e of the instruction fetched by the instruction fetching section 9 is set, so the instruction is not decoded and the program counter 2 is updated, but the branch control table control section 6 is make it work. The branch control table control unit 6 sequentially compares the branch start addresses of the program counter 2 and the branch control table 4, and takes out the branch destination address l) d corresponding to the matched branch start address 4C from the branch control table 4. , the branch control unit 7 transfers it to the program counter 2. As a result, the next address in the program memory 1 from which the instruction fetching section 9 fetches an instruction becomes address n. According to this embodiment, since the program counter 2 and the branch start address in the branch initial table 4 are compared only when the flag is set, it is possible to eliminate wasteful comparison each time. In the two embodiments described above, the branch destination address was selected by comparing all the branch start addresses in the program counter 2 and the branch control table 4, but in the third embodiment in which the program counter 2 and the branch control table 4 are missing, An example will be described in which a multi-bit flag is provided and this flag directly indicates the storage position of the branch destination address in the branch 11ial table 4, thereby eliminating the need for comparison. In the following, an example will be explained in which the flag is set to 3 bits. FIG. 8 is a flowchart of the actual operation of an instruction in the IFJ 11 of this embodiment. FIG. 8 shows the relationship between the program memory 2 and the branch control table 4 in this embodiment, where If is the instruction at address n], 1g is the flag for the instruction at address m, and 4e is the flag for the instruction at address m.
is the address n of the program memory 1 which is stored in the branch *Ji wholesale table 4 as the branch destination address. It is assumed that addresses m to n-1 of the program memory 1 are to be changed, and that no contradiction occurs when programs are executed adjacently at addresses m and n. The 3-bit flag Ig of the instruction 1f at address m is set, and the branch destination address 4e is placed in the position of the branch control table 4 indicated by this flag.
Set it. First, the instruction fetch unit 9 inside the calculation unit 5 instructs the program counter 2 @II! ! An instruction is retrieved from program memory 1 of . If no flag of the fetched instruction is set, the instruction fetching section 9 transfers it to the instruction decoding section 3, and activates the instruction decoding section 3. In parallel with this, the program counter updater 1 group 8 is activated to update the program counter 2, and as a result, the program counter 2 points to the next address of the instruction taken out from the program memory I. When the program counter 2 reaches address m, the flag 1g of the instruction fetched by the instruction fetch unit 9 is set, so
The branch control table controller 6 is operated without decoding the instruction or updating the program counter 2. The branch control table control unit 6 sets the branch destination address of the branch control table 4 stored at the position indicated by the flag, which is 01 in binary in this example.
1, that is, 3 in decimal notation, the third stored branch destination address 4e is taken out and the branch control unit 7 transfers it to the program counter 2. As a result, the address of the program memory l from which the instruction fetching section 9 will extract the next instruction will be address n. According to the third embodiment, the branch destination address can be directly selected using the flag without comparing the branch start addresses in the program counter 2 and the branch control table 4, and the comparison can be made more efficiently. . In each of the above embodiments, the branch control table 4 has a branch start address, a branch destination address, or just one branch destination address, but it is possible to set a plurality of strings. Also, since it is only installed on table 4 when modifying the program (after modification, comparison with table 4 is not necessary). Since the execution of a part can be skipped, it becomes extremely easy to modify the part in the middle. [Effects of the Invention] According to the present invention, when changing a program without stopping the execution of the program, it is possible to modify the part that has already been created. The address of the correction area in the middle of the program is temporarily stored in the branch control table so that corrections and changes can be made. , the same table is not required and the operation becomes simple.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the embodiment of the present invention, 2ci] is a block diagram of the branch control table 1# section, Fig. 3 is a relationship diagram between the program memory address and the branch control table, and Fig. 4 is the same operation flow. 5 is an operational flowchart for changing a program during operation in an embodiment of the present invention, and FIG. 6 is a flowchart for an instruction execution operation in a second embodiment in which comparison is performed only when a flag is set. Figure 7 is a diagram showing the relationship between program memory addresses and branch control tables, Figure 8 is a flowchart of instruction execution operations in the third embodiment that eliminates the need for comparison, and Figure 9 is a diagram showing the relationship between program memory addresses and branch control tables. 1sflvf, figure. 1: Niprogram memory, 2: Program counter, 3
: Instruction decoding unit, 4 = Branch control table, 5: Arithmetic unit, 6
: Branch control table control section, 7: Branch control section, 8 Niprogram counter update control section, 9: Instruction fetch section. Nosorifu Ko 2゛Two runs, Rimin] Branch control table Jitsu X (A7, Yui Handi Hand DeP (Bottom/θ) Ward map

Claims (1)

[Claims] 1. A memory that stores a program including various sequence instructions, a program counter that indicates an operation execution address, and a branch that stores the preceding and following parts of the modification area of the program as a branch start address and a branch destination address, respectively. It comprises a control table and an arithmetic unit that executes the program read from the memory, and when modifying the program, the arithmetic unit compares the contents of the program counter being operated with the branch start address in the branch control table, A programmable controller characterized in that, when the two have a certain relationship, the branch destination address is transferred to the program counter and an operation is executed. 2. In claim 1, the arithmetic unit compares the value of the program counter and the branch destination address in the branch control table during the calculation, and when the two match, branch control moves the branch destination address to the program counter. 1. A programmable controller comprising: a program counter; and an arithmetic unit that executes an operation by skipping over the correction area according to the contents of the program counter. 3. In claim 1, the memory stores flags before and after the modification area of the program,
The programmable controller is characterized in that the branch control unit is configured to compare the contents of the program counter and the branch destination address in the branch control table when detecting the flag during calculation. 4. In claim 1, the branch control table stores a plurality of sets of branch start addresses and branch destination addresses, and the arithmetic unit executes arithmetic operations by skipping over a plurality of correction areas designated by each set. programmable controller. 5. A memory for storing a program consisting of various sequence instructions and having a flag at the front of the modification area, a program counter indicating the execution address of the program, and a branch destination address indicating the rear part of the modification area corresponding to the flag. It is equipped with a branch control table stored in a location, and an arithmetic unit that executes a program read from the memory, and when the arithmetic unit detects the flag during execution of an operation, it selects the branch destination address indicated by this flag. A programmable controller characterized in that the programmable controller is configured to transfer the information from the branch control table to the program counter and execute the calculation.