JPH03214705A - Manufacturing method of voltage nonlinear resistor element - Google Patents
Manufacturing method of voltage nonlinear resistor elementInfo
- Publication number
- JPH03214705A JPH03214705A JP2011336A JP1133690A JPH03214705A JP H03214705 A JPH03214705 A JP H03214705A JP 2011336 A JP2011336 A JP 2011336A JP 1133690 A JP1133690 A JP 1133690A JP H03214705 A JPH03214705 A JP H03214705A
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- Prior art keywords
- thin film
- zinc oxide
- film
- manufacturing
- sio2
- Prior art date
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、酸化亜鉛を主成分とし、それ自身が電圧非直
線性を示す焼結体の側面に、高抵抗層を形成した電圧非
直線抵抗体素子の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a voltage non-linear resistor which has zinc oxide as a main component and has a high resistance layer formed on the side surface of a sintered body which itself exhibits voltage non-linearity. The present invention relates to a method for manufacturing an element.
従来の技術
従来より、酸化亜鉛を主成分とし、これにビスマス、マ
ンガン等の酸化物を添加物として加え、成形して、焼成
することにより得られる電圧非直線性の高い抵抗体は、
酸化亜鉛ハリスタと呼ばれ、?圧安定化素子、サージ吸
収素子、避雷器等として広く用いられている。Conventional technology Conventionally, resistors with high voltage non-linearity have been made by using zinc oxide as a main component, adding oxides such as bismuth and manganese as additives, molding and firing.
Zinc oxide called Halista? Widely used as pressure stabilizing elements, surge absorbing elements, lightning arresters, etc.
この酸化亜鉛バリスタを電力用避雷器として用いる場合
、要求されるべき特性の一つに放電耐量特性がある。こ
れは、JRC−187−1973に規定されているよう
に、4/10μsの衝撃電流を5分間隔で2回印加し、
素子が耐え得るピーク電流の最大値である。When this zinc oxide varistor is used as a power surge arrester, one of the required characteristics is discharge withstand capability. As specified in JRC-187-1973, a 4/10 μs impact current is applied twice at 5 minute intervals.
This is the maximum value of peak current that the element can withstand.
従来より、電力用避雷器の製造方法として、放電耐量を
上げることを目的に、避雷素子の側面に、SiOz
Znt sb2 012.8I2 03等の混合物を塗
布し、焼結させ、高抵抗層を形成したり(特開昭56−
69804号公報)、焼成容器内にsb.():+
BizC)+ SiQ■等からなる混合物を配置し、
気一固相反応により避雷素子の側面に高抵抗層を形成す
る方法(特公昭60−15128号公報)等が知られて
いた。Traditionally, as a manufacturing method for power surge arresters, SiOz was added to the side of the lightning arrester element in order to increase the discharge capacity.
A mixture such as Znt sb2 012.8I2 03 is applied and sintered to form a high-resistance layer (Japanese Patent Laid-Open No. 1986-
69804), sb. ():+
A mixture consisting of BizC) + SiQ■ etc. is placed,
A method has been known in which a high resistance layer is formed on the side surface of a lightning arrester element by a gas-solid phase reaction (Japanese Patent Publication No. 15128/1983).
発明が解決しようとする課題
しかしながら、上記の方法では、前者の場合、焼結後の
高抵抗膜中の粒子の大きさが不均一であ?たり、作製膜
がボーラスであったりすることがあり、避雷素子と高抵
抗膜との密着性が必ずしも十分ではない場合がある。ま
た、後者の場合、作製膜厚の均一性が良くない場合があ
る。そして、高抵抗層と、避雷素子との密着性が十分で
はないと、サージ電流が避雷素子と高抵抗層の間をリー
クし、木来持つべき高抵抗層の特性は十分に満たされず
、放電耐量の限界値が低下することがある。Problems to be Solved by the Invention However, in the above method, in the former case, does the size of the particles in the high-resistance film after sintering become non-uniform? In some cases, the formed film may be a bolus, and the adhesion between the lightning arrester element and the high-resistance film may not necessarily be sufficient. Furthermore, in the latter case, the uniformity of the produced film thickness may not be good. If the adhesion between the high-resistance layer and the lightning arrester is not sufficient, surge current will leak between the lightning arrester and the high-resistance layer, and the characteristics of the high-resistance layer that should have been achieved will not be fully met, resulting in discharge. The limit value of tolerance may decrease.
また、高抵抗膜の膜厚が均一でないと、膜の薄いところ
を選択的にサージ電流が流れ、放電耐量の限界値が低下
する原因になる。Furthermore, if the thickness of the high-resistance film is not uniform, a surge current will flow selectively through the thinner parts of the film, causing a reduction in the limit value of the discharge withstand capacity.
本発明は、このような課題を解決するもので、避雷素子
と密着性の高い高抵抗膜を均一に形成し、放電耐量の高
い避雷器の作製を目的とするものである。The present invention is intended to solve these problems, and aims to manufacture a lightning arrester with high discharge resistance by uniformly forming a high-resistance film with high adhesion to a lightning arrester element.
課題を解決するための手段
上記のような課題を解決するために、本発明の電圧非直
線抵抗体素子の製造方法は、酸化亜鉛ハリスタ素体の側
面に、高抵抗膜であるSiO■薄膜またはSi3NaF
il膜を化学的または物理的な製膜法により形成する方
法を提案するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the method for manufacturing a voltage non-linear resistor element of the present invention provides a method of manufacturing a voltage non-linear resistor element by applying a high-resistance film such as an SiO2 thin film or Si3NaF
This paper proposes a method of forming an il film using a chemical or physical film forming method.
作用
一般的に化学的または、物理的な製膜法で薄膜を形成す
ると、緻密で密着性の高い薄膜の形成が可能である。ま
た、s10zFiN膜またはS!3N4薄膜は耐熱衝撃
性、絶縁性に優れ、サージ電流による素子の発熱や、サ
ージ電流印加時の強電界に十分耐え得る材料である。こ
のことから、上記方法により、より放電耐量の高い避雷
素子の作成が可能となる。Function Generally, when a thin film is formed using a chemical or physical film forming method, it is possible to form a dense and highly adhesive thin film. In addition, s10zFiN film or S! The 3N4 thin film has excellent thermal shock resistance and insulation properties, and is a material that can sufficiently withstand element heat generation due to surge currents and strong electric fields when surge currents are applied. From this, the method described above makes it possible to create a lightning arrester element with higher discharge resistance.
実施例
以下、本発明の製造方法について、実施例に基づき詳細
に説明する。EXAMPLES Hereinafter, the manufacturing method of the present invention will be explained in detail based on examples.
まず、酸化亜鉛粉末に、ビスマス、コハルト、マンガン
、アンチモン、クロム等の酸化物を、合計量に対してそ
れぞれ0.3mo1%〜1.5mo1%加え、十分に粉
砕、混合した後、造粒し、原料粉を作製した。この原料
粉を直径4 0 mm、厚さ30帥の大きさに圧縮形成
し、空気中で700゜C〜900゜Cの温度で十分にバ
インダーを分解した後、空気中において?200゜Cで
焼結させ、酸化亜鉛バリスタ素体を得た。First, oxides such as bismuth, cohardt, manganese, antimony, and chromium are added to zinc oxide powder in an amount of 0.3 mo1% to 1.5 mo1% based on the total amount, and the mixture is sufficiently crushed and mixed, and then granulated. , raw material powder was prepared. This raw material powder is compressed into a size of 40 mm in diameter and 30 mm thick, and after sufficiently decomposing the binder in the air at a temperature of 700°C to 900°C, it is placed in the air. It was sintered at 200°C to obtain a zinc oxide varistor element.
このようにして得られたバリスタ素体の側面に、プラズ
マCVD法を用い、SiO■の高抵抗膜を形成した。以
下に、その具体的な作製方法を示す。A high-resistance film of SiO2 was formed on the side surface of the varistor body thus obtained using plasma CVD. A specific manufacturing method is shown below.
すなわち、第2図に示すように、バリスタ素体4の上下
を回転可能な治具5で挟み、予め300゜Cの温度に赤
外線を用いてバリスタ素体4を加熱させた後、ゆっくり
回転させながら反応室6を通過させた。ここで、膜厚は
反応室6を通過させる時間で制御した。そして、反応室
6の内容量は、約65リットル、反応ガスは、SIH4
ガスが30 (ml/min)、N20ガスが800(
ml/min)の流量で反応室6中にガス導入バルブ8
を制御して導入し、製膜中の反応室6のガス圧は、I
Torr,になるように真空ポンプ(図示せず)へのメ
インバルブ9により制御した。また、プラズマを作る放
電電極7は、40cm角の平面で、13.56MHzの
高周波電源を用い、500(W)の電力を投入した。上
記条件でのバリスタ素体4上での製膜速度は、約150
(ml/min)であった。この条件で膜厚を変えて、
4種類の試料を?成した。このようにして作製した試料
の両端面を研磨してアルミニウムの容躬電極を形成し、
ハリスタ素子を作製した。このようにして作製したバリ
スタ素子の概略図を第1図に示す。下記の第1表に作製
した試利のSiO■VR膜の膜厚を示す。That is, as shown in FIG. 2, the upper and lower parts of the varistor element 4 are sandwiched between rotatable jigs 5, and after the varistor element 4 is heated in advance to a temperature of 300°C using infrared rays, the varistor element 4 is slowly rotated. The mixture was allowed to pass through the reaction chamber 6 at the same time. Here, the film thickness was controlled by the time for passing through the reaction chamber 6. The internal capacity of the reaction chamber 6 is approximately 65 liters, and the reaction gas is SIH4
Gas is 30 (ml/min), N20 gas is 800 (ml/min)
A gas introduction valve 8 into the reaction chamber 6 at a flow rate of ml/min)
is introduced in a controlled manner, and the gas pressure in the reaction chamber 6 during film formation is I
Torr, was controlled by a main valve 9 to a vacuum pump (not shown). Further, the discharge electrode 7 for generating plasma was a 40 cm square plane, and a 13.56 MHz high frequency power source was used to supply a power of 500 (W). The film forming speed on the varistor body 4 under the above conditions is approximately 150
(ml/min). By changing the film thickness under these conditions,
Four types of samples? accomplished. Both end faces of the sample thus prepared were polished to form aluminum capacitive electrodes.
A harista element was fabricated. A schematic diagram of the varistor element produced in this manner is shown in FIG. Table 1 below shows the thickness of the sample SiO₂VR film prepared.
また、第1図において、1は酸化亜鉛バリスタ素体、2
はSiO■薄膜、3は電極である。In addition, in FIG. 1, 1 is a zinc oxide varistor element body, 2
is a SiO2 thin film, and 3 is an electrode.
〈第1表〉
また、比較のために、従来例の素子として、SO。薄膜
の代わりに、ハリスタ素体の側面に、S ioz ,Z
n7 Sbg 012.B iz 03を適当な割合で
混合した絶縁材料を薄くコーティングし、熱処理を施し
、上記と同様の方法で電極を形成して作製した試料(試
料5)を用意した。<Table 1> For comparison, SO is used as a conventional element. Instead of a thin film, S ioz , Z
n7 Sbg 012. A sample (Sample 5) was prepared by coating a thin layer of an insulating material containing B iz 03 in an appropriate proportion, heat-treating the sample, and forming an electrode in the same manner as described above.
このようにして得られたハリスタ素子(試料1〜5)に
対して、4/10μsの衝撃電流を5分間隔で2回印加
し、素子が耐え得るピーク電流の限界値を測定した。An impact current of 4/10 μs was applied twice at an interval of 5 minutes to the thus obtained harista elements (samples 1 to 5), and the limit value of the peak current that the element could withstand was measured.
この結果を下記の第2表に示す。第2表中、× 印が素子の破壊した電流値である。The results are shown in Table 2 below. In Table 2, × The mark is the current value at which the element was destroyed.
く第2表〉
?2表より、s+ozfl膜をバリスタ素体の側面にコ
ーティングした素子の放電耐量は何もコーティングして
いない素子、または熱処理により絶縁材料をコーティン
グした素子のそれに比べて、大きく優れていることがわ
かる。また、今回の実験では、SiO■薄膜の膜厚が厚
くなるほど放電耐量は大きくなっているが、膜厚が10
μmの素子においても、従来例に比べ十分特性の向上は
認め?れる。Table 2〉? From Table 2, it can be seen that the discharge withstand capacity of the device in which the s+ozfl film is coated on the side surface of the varistor body is significantly superior to that of the device without any coating or the device coated with an insulating material through heat treatment. In addition, in this experiment, the discharge withstand capacity increased as the thickness of the SiO thin film became thicker;
Even in μm devices, is it recognized that the characteristics are sufficiently improved compared to conventional examples? It will be done.
尚、今回の実験において、SiO■薄膜はSiH.ガス
と、N20ガスを用いたプラズマCVD法により作製し
たが、これはプラズマCVD法に限らず、減圧CVD法
や、常圧CVD法等、他の化学気相成長法、あるいはス
パッタリング等の物理的蒸着法によっても、SiO■薄
膜の作製は可能であり、本発明の素子に適応することは
可能である。In this experiment, the SiO2 thin film was SiH. Although the plasma CVD method using N20 gas and N20 gas is used, this method is not limited to the plasma CVD method. It is also possible to produce a SiO2 thin film by the vapor deposition method, and it is possible to apply this method to the device of the present invention.
ここで、上記のSiOzFi!膜に代えてS13N4薄
膜により高抵抗膜を形成しても、上記実施例と同様の効
果を得ることができた。下記の第3表に作製した試料の
Sf3N4薄膜の膜厚を示す。ここで、試料の作製条件
は、反応ガスが、S i H 4ガス: 30 (ml
/min), Nzガス: 800(ml/min)で
あり、バリスタ素体上での製膜速度:約50 (nm/
min)とした以外は、全て上記実施例と同一条件とし
た。Here, the above SiOzFi! Even when a high resistance film was formed using a S13N4 thin film instead of the film, the same effect as in the above example could be obtained. Table 3 below shows the thickness of the Sf3N4 thin film of the prepared sample. Here, the sample preparation conditions are such that the reaction gas is S i H 4 gas: 30 (ml
/min), Nz gas: 800 (ml/min), and film forming rate on the varistor body: approximately 50 (nm/min).
The conditions were all the same as in the above example, except that the conditions were set to (min).
以下余白
く第3表〉
ここで、試料6は上記実施例の試料1と同一のものであ
る。これらの試料について、上記実施例と同様の衝撃電
流を印加し、素子が耐え得るピーク電流の限界値を測定
した結果を下記の第4表に示す。また、第4表において
も、上述した比較用の試料5による測定結果を参考のた
めに記載している。Below is Table 3 with blank spaces> Here, sample 6 is the same as sample 1 of the above example. For these samples, the same impact current as in the above example was applied, and the limit value of the peak current that the device could withstand was measured. The results are shown in Table 4 below. Also, in Table 4, the measurement results of the above-mentioned comparative sample 5 are listed for reference.
く第4表〉
?記の第4表に示すように、SisN4薄膜を用いた場
合においても、優れた放電耐量特性を得ることができる
。特に、Si3N4ffi膜の場合は、膜厚が2.0μ
mの素子においても、従来例に比べ十分に特性の向上が
認められるものである。また、このSt3Na薄膜は、
SiH3ガスと、NH.ガスを用いたプラズマCVD法
によっても作製することができ、その他に上記実施例と
同様に、減圧CVD法や常圧CVD法等の他の化学気相
成長法、あるいはスパッタリング等の物理的蒸着法によ
っても、作製可能なことはもちろんである。Table 4〉? As shown in Table 4 below, excellent discharge withstand characteristics can be obtained even when a SisN4 thin film is used. In particular, in the case of Si3N4ffi film, the film thickness is 2.0μ
Even in the element of m, the characteristics are sufficiently improved compared to the conventional example. Moreover, this St3Na thin film is
SiH3 gas and NH. It can also be produced by a plasma CVD method using a gas, and in addition, as in the above embodiment, other chemical vapor deposition methods such as a low pressure CVD method or an atmospheric pressure CVD method, or a physical vapor deposition method such as sputtering can be used. Of course, it can also be produced by
発明の効果
以上のように本発明によれば、酸化亜鉛ハリスタ素体の
側面に、化学的または物理的な薄膜成長方法を用いてS
iO■薄膜またはS i 3Na 71膜を形成するこ
とにより、放電耐量特性の優れた電圧非直線体素子を製
造することができる。Effects of the Invention As described above, according to the present invention, S is grown on the side surface of a zinc oxide halistan element body using a chemical or physical thin film growth method.
By forming the iO2 thin film or the S i 3Na 71 film, a voltage nonlinear element with excellent discharge withstand characteristics can be manufactured.
第1図は本発明の製造方法により作製した電圧非直線抵
抗体素子の断面図、第2図は本発明の製造方法における
薄膜形成方法の一例を示した図である。
l・・・・・・酸化亜鉛バリスタ素体、2・旧・・Si
n2薄膜、3・・・・・・電極、4・・・・・・酸化亜
鉛バリスタ素体、5・・・・・・回転可能な治具、6・
旧・・反応室、7・・・・・・放電電極、8・・・・・
・ガス導入バルブ、9・・・・・・真空ポンプへのメイ
ンバルブ。FIG. 1 is a cross-sectional view of a voltage nonlinear resistor element manufactured by the manufacturing method of the present invention, and FIG. 2 is a diagram showing an example of a thin film forming method in the manufacturing method of the present invention. l... Zinc oxide varistor element, 2 Old... Si
n2 thin film, 3... Electrode, 4... Zinc oxide varistor element, 5... Rotatable jig, 6...
Old...Reaction chamber, 7...Discharge electrode, 8...
・Gas introduction valve, 9...Main valve to the vacuum pump.
Claims (1)
バリスタ素体の側面に、化学的または物理的な薄膜成長
方法を用い、SiO_2薄膜またはSi_3N_4薄膜
を形成することを特徴とする電圧非直線抵抗体素子の製
造方法。Voltage non-linearity characterized by forming a SiO_2 thin film or Si_3N_4 thin film on the side surface of a zinc oxide varistor element body which contains zinc oxide as a main component and exhibits voltage non-linearity using a chemical or physical thin film growth method. A method for manufacturing a resistor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011336A JP2800341B2 (en) | 1990-01-19 | 1990-01-19 | Method for manufacturing voltage non-linear resistor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011336A JP2800341B2 (en) | 1990-01-19 | 1990-01-19 | Method for manufacturing voltage non-linear resistor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03214705A true JPH03214705A (en) | 1991-09-19 |
| JP2800341B2 JP2800341B2 (en) | 1998-09-21 |
Family
ID=11775191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011336A Expired - Fee Related JP2800341B2 (en) | 1990-01-19 | 1990-01-19 | Method for manufacturing voltage non-linear resistor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2800341B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS577904A (en) * | 1980-06-17 | 1982-01-16 | Matsushita Electric Industrial Co Ltd | Method of producing voltage non-linear resistor |
| JPS6480002A (en) * | 1987-09-21 | 1989-03-24 | Chichibu Cement Kk | Nonlinear resistor |
-
1990
- 1990-01-19 JP JP2011336A patent/JP2800341B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS577904A (en) * | 1980-06-17 | 1982-01-16 | Matsushita Electric Industrial Co Ltd | Method of producing voltage non-linear resistor |
| JPS6480002A (en) * | 1987-09-21 | 1989-03-24 | Chichibu Cement Kk | Nonlinear resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2800341B2 (en) | 1998-09-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |