JPH0321793U - - Google Patents
Info
- Publication number
- JPH0321793U JPH0321793U JP8149489U JP8149489U JPH0321793U JP H0321793 U JPH0321793 U JP H0321793U JP 8149489 U JP8149489 U JP 8149489U JP 8149489 U JP8149489 U JP 8149489U JP H0321793 U JPH0321793 U JP H0321793U
- Authority
- JP
- Japan
- Prior art keywords
- data
- processing
- devices
- target detection
- perform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006835 compression Effects 0.000 claims description 9
- 238000007906 compression Methods 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 9
- 230000001629 suppression Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第1図はこの考案の一実施例を示すレーダ信号
処理装置の構成図、第2図はこの考案の他の実施
例を示すレーダ信号処理装置の構成図、第3図は
制御データを説明する図、第4図は従来のデータ
信号処理装置の構成図、第5図は従来のレーダ信
号処理装置の処理時間を説明するための図である
。
図において、1……A/D変換器、2……出力
装置、3……パルス圧縮装置、4……クラツタ抑
圧装置、5……目標検出装置、6……相関処理装
置、7……マルチポートメモリ、8……コネクタ
、9……制御データ書き込み装置である。なお、
各図中同一符号は同一または相当部分を示す。
Fig. 1 is a block diagram of a radar signal processing device showing one embodiment of this invention, Fig. 2 is a block diagram of a radar signal processing device showing another embodiment of this invention, and Fig. 3 explains control data. 4 is a block diagram of a conventional data signal processing device, and FIG. 5 is a diagram for explaining the processing time of the conventional radar signal processing device. In the figure, 1...A/D converter, 2...Output device, 3...Pulse compression device, 4...Clutter suppression device, 5...Target detection device, 6...Correlation processing device, 7...Multiple Port memory, 8...connector, 9...control data writing device. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
A/D変換器、A/D変換器と接続され、複数の
入出力ポートを持つマルチポートメモリを持ち、
マルチポートメモリのデータに対してパルス圧縮
処理を行う一個以上のパルス圧縮装置を持ち、マ
ルチポートメモリのデータに対してクラツタ抑圧
処理を行う一個以上のクラツタ抑圧装置を持ち、
マルチポートメモリのデータに対して目標検出処
理を行う一個以上の目標検出装置を持ち、マルチ
ポートメモリのデータに対し参照データとの相関
処理を行う一個以上の相関処理装置を持ち、マル
チポートメモリのデータを外部に出力する出力装
置を持ち、パルス圧縮装置およびクラツタ抑圧装
置および目標検出装置および相関処理装置とマル
チポートメモリを接続し必要に応じて接続するパ
ルス圧縮装置およびクラツタ抑圧装置および目標
検出装置および相関処理装置を交換できるような
コネクタを持つことを特徴とするレーダ信号処理
装置。 (2) アナログ信号をデイジタル信号に変換する
A/D変換器、A/D変換器と接続され、複数の
入出力ポートを持つマルチポートメモリを持ち、
マルチポートメモリのデータに対してパルス圧縮
処理を行う一個以上のパルス圧縮装置を持ち、マ
ルチポートメモリのデータに対してクラツタ抑圧
処理を行う一個以上のクラツタ抑圧装置を持ち、
マルチポートメモリのデータに対して目標検出処
理を行う一個以上の目標検出装置を持ち、マルチ
ポートメモリのデータに対し参照データとの相関
処理を行う一個以上の相関処理装置を持ち、マル
チポートメモリのデータを外部に出力する出力装
置を持ち、パルス圧縮装置およびクラツタ抑圧装
置および目標検出装置および相関処理装置とマル
チポートメモリを接続し必要に応じて接続するパ
ルス圧縮装置およびクラツタ抑圧装置および目標
検出装置および相関処理装置を交換できるような
コネクタを持ち、制御データをマルチポートメモ
リのメモリ領域を介して行う制御データ書き込み
装置を持つことを特徴とするレーダ信号処理装置
。[Claims for Utility Model Registration] (1) An A/D converter that converts analog signals into digital signals, and a multi-port memory connected to the A/D converter and having multiple input/output ports;
It has one or more pulse compression devices that perform pulse compression processing on the data in the multi-port memory, and it has one or more clutter suppression devices that perform clutter suppression processing on the data in the multi-port memory,
It has one or more target detection devices that perform target detection processing on data in the multi-port memory, one or more correlation processing devices that perform correlation processing with reference data on the data in the multi-port memory, and A pulse compression device, a clutter suppression device, and a target detection device that has an output device that outputs data to the outside, and connects the multiport memory to the pulse compression device, clutter suppression device, target detection device, and correlation processing device, and connects them as necessary. and a radar signal processing device characterized by having a connector that allows exchange of the correlation processing device. (2) It has an A/D converter that converts analog signals to digital signals, and a multiport memory that is connected to the A/D converter and has multiple input and output ports.
It has one or more pulse compression devices that perform pulse compression processing on the data in the multi-port memory, and it has one or more clutter suppression devices that perform clutter suppression processing on the data in the multi-port memory,
It has one or more target detection devices that perform target detection processing on data in the multi-port memory, one or more correlation processing devices that perform correlation processing with reference data on the data in the multi-port memory, and A pulse compression device, a clutter suppression device, and a target detection device that has an output device that outputs data to the outside, and connects the multiport memory to the pulse compression device, clutter suppression device, target detection device, and correlation processing device, and connects them as necessary. and a connector for exchanging correlation processing devices, and a control data writing device for writing control data via a memory area of a multiport memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8149489U JPH0321793U (en) | 1989-07-11 | 1989-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8149489U JPH0321793U (en) | 1989-07-11 | 1989-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0321793U true JPH0321793U (en) | 1991-03-05 |
Family
ID=31627491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8149489U Pending JPH0321793U (en) | 1989-07-11 | 1989-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0321793U (en) |
-
1989
- 1989-07-11 JP JP8149489U patent/JPH0321793U/ja active Pending
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