JPH03218193A - Receiving equipment compatible with high quality/ standard television - Google Patents

Abstract

PURPOSE:To make it possible to display a high quality television(TV) signal and a standard TV signal on the same display by controlling a selector, a by-pass existence selecting means and an IDTV processor based upon an output from a high quality TV signal detecting circuit and an output from a wide signal detecting circuit. CONSTITUTION:The scanning speed and the number of scanning lines of an MUSE signal are converted by a wide converter 103 as a standard TV signal having the size almost equal to that of a high quality TV signal in both vertical and horizontal display ranges. An IDTV processor 105 successively converts input signals from the wide converter 103 to scanning signals and outputs the converted signals. Thereby, signals corresponding to approximately the same contents as one scanning line of the high quality TV signal are outputted in both the horizontal and vertical directions. Thereby, any inputted TV signal, i.e., a high quality TV signal or a standard TV signal, can be displayed on the screen of the common display 108 adopting the sequential scanning system based upon a wide aspect ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for selectively inputting a high-definition television signal inputted from a certain first terminal and a standard television signal inputted from a second terminal. The present invention relates to a high-definition/standard television common receiving device that outputs data to a common display and displays the screen on the display.

[Conventional technology]

Since digital signal processing was introduced to signal processing in television receivers, the definition of television images has progressed, and high-definition television broadcasting is being put into practical use.

For example, IDT, which aims to achieve higher definition in the current broadcasting system,
V (Improved Definition T
elevision), and EDT V (Enhan TV), which aims to achieve high definition while maintaining compatibility with current broadcasting systems.
ced Definition Television
), a different type of HD that is stuck with the current broadcasting system.
TV (High Definition Te
(Levision) and the like are examples of television systems aiming at high definition.

As seen in Japanese Unexamined Patent Publication No. 123295/1982, IDTV performs three-dimensional processing using a frame memory, sequential scan conversion, etc. to eliminate interference and improve resolution on the display screen.

In addition to IDTV processing, EDTV aims to eliminate ghost interference by inserting a reference signal, and studies are also underway to make the screen wider.

}Various systems have been proposed for iDTV, but material rN
HK Technology Research Journal 1986, Volume 39, Issue 2, Volume 172, p.
MUSE (Multi
ple Sub-Nyquist SamplingE
ncoding) system is moving toward practical use as high-definition television. The MUSE system will be explained below as a representative example of a high-definition television system.

The MUSFJ method is a method in which a luminance signal and a color difference signal are multiplexed on the time axis in a television signal, and further pixels are thinned out so as to go around once every two frames to compress the band and then transmitted.

The number of scanning lines is 1125, the frame frequency is an interlaced signal of 30 frames, and the screen aspect ratio is (16
:9), which is a wide aspect ratio that is significantly different from the current broadcasting system.

Receivers compatible with such television systems aiming at higher definition have large circuit scales and include frame memories with a capacity of IOM bits or more.

Furthermore, since the above-mentioned I DTV/EDTV receiver and MUSE receiver are being developed as independent receivers, there is still no receiver that can receive these multiple television broadcasts in common with one receiver. Doesn't exist. Only recently has a signal conversion device been announced, such as the one introduced in Japanese Patent Application Laid-Open No. 5970369, for viewing high-definition television broadcasts on current receivers.

Japanese Patent Application Laid-Open No. 59-70369 thins out the scanning lines of a high-definition television signal and further converts the time axis to conform to the standards of standard television. A down converter that converts MUSE signals to NTSC signals has also been recently announced. This down converter is MU
The SE signal is subjected to scanning speed conversion and simple two-dimensional filtering to conform to standard television specifications. Therefore, in such a signal processing device, deterioration of resolution and occurrence of disturbances such as aliasing noise cannot be avoided.

For example, the above-mentioned down converter performs aspect ratio conversion because it is assumed that the image will be displayed on a monitor (cathode ray tube screen) used in current receivers as described above. This situation is shown in Figure 2(a). (b)
Shown below.

It has a wide aspect ratio of (16:9)＼
In order to display Ivision images on a monitor screen with the current standard television signal aspect ratio of (4:3), the down converter uses two display methods as shown in Figure 2. are prepared. Figure 2 (
A) is a method in which undisplayed portions are provided at the top and bottom of a (4:3) monitor, and the image is displayed while maintaining the (16:9) aspect ratio. FIG. 2(b) shows a method in which both sides of a (16:9) high-definition signal are cut and displayed on a (4:3) monitor.

In this way, currently there is one receiver that corresponds to one broadcasting method, and in order to receive another broadcasting method with this receiver, a signal converter is used to convert it into a displayable format before receiving it. It was possible.

[Problem to be solved by the invention]

As mentioned above, when EDTV systems and No. 1 vision receivers become widespread in the future, the screen display devices for television will be the current broadcasting display devices with an aspect ratio of (4:3) and (16:3). 9) There are two types of display devices for high-definition broadcasting, etc., that have a wide aspect ratio. At this time, when a video signal with an aspect ratio of (16:9) is displayed on a display device with an aspect ratio of (4:3), as in the down converter described in the prior art section, the following problems occur. .

As shown in Figure 2 (a), (16
:9), the number of scanning lines is thinned out to create upper and lower empty areas, and the vertical resolution is extremely degraded due to the thinning of the -scanning lines. When the vertical display ranges are aligned as shown in FIG. 2(b), the left and right images are cut off, which has the disadvantage that the content intended by the video producer cannot be accurately conveyed to the viewer.

An object of the present invention is to solve the above problems and to sequentially scan television signals with a wide aspect ratio, regardless of whether a high-definition television signal or a standard television signal is input. A low-cost, high-quality display that can be displayed face-to-face on a common display that uses
An object of the present invention is to provide a standard television common receiving device.

[Means to solve the problem]

In order to achieve the above object, the high-definition/standard television shared receiving device according to the present invention selectively receives a high-definition television signal input from a first terminal and a standard television signal input from a second terminal. a display that adopts a progressive scanning method with a wide aspect ratio, and a high-definition television signal that detects the presence or absence of a high-definition television signal as a signal input from the first terminal; a television signal detection circuit; a scan conversion circuit that scan-converts the high-definition television signal input from the first terminal into a signal having a number of scanning lines and a scanning speed that conforms to a standard television signal and outputs the signal; a wide converter comprising: a wide signal detection circuit for detecting a wide signal having a wide aspect ratio when a wide signal having a wide aspect ratio is added to the standard television signal input from the second terminal; a selector that receives a standard television signal input from a second terminal and a high-definition television signal after scan conversion from the scan conversion circuit, and selects and outputs one of them; and the selector an IDTV processor that receives an output signal from the IDTV processor, performs signal processing, doubles the speed, and outputs the signal; and an aspect ratio conversion circuit that receives an output signal of the IDTV processor, converts its aspect ratio to a wide aspect ratio, and outputs the same. , bypass selection means for passing the output signal of the IDTV processor through the aspect ratio conversion circuit or bypassing it and outputting it to the display; and detecting output from the high-definition television signal detection circuit and the wide signal. The detection output from the detection circuit is input,
and a control circuit that controls the selector, bypass presence/absence selection means, and IDTV processor based on these.

[Effect]

First, connect the MUS from the high-definition television signal input terminal.
Let us explain the case when the E signal is input. In the wide converter, the MUSE signal is converted into a standard television signal having approximately the size of a high-definition television signal in both the vertical display range and the horizontal display range in terms of scanning speed and number of scanning lines. Further, the IDTV processor converts the manual signal from the wide converter into a progressive scanning signal and outputs the signal. Therefore, a signal having substantially the same content as one scanning line of the high-definition television signal in the horizontal direction is output, and a signal having substantially the same content as the high-definition television signal in the vertical direction is also output.

In this case, since the television signal inherently has a wide aspect ratio, the aspect ratio changing circuit is bypassed and the signal is output directly to the display. Therefore, a video signal with a wide aspect ratio is directly supplied to the display. As a result, (1
An image with a wide aspect ratio of 6:9) is displayed to fill the entire display screen.

If a standard television signal is input, the IDT
In the V processor, high-definition processing is performed and output as a progressive scanning signal. At this time, since the image reproduced by the standard television signal has an aspect ratio of (4:3), a signal compressed in the horizontal direction by the aspect ratio conversion circuit is supplied to the display. As a result, a display with a wide aspect ratio (4
:3) can be displayed.

Also, if a video signal that is a standard television signal but has a wide aspect ratio (such a signal exists as a playback signal for a VTR, etc.) is input from the standard television signal input terminal, The wide signal detection circuit recognizes the video signal as having a wide aspect ratio from a signal indicating that the video signal is added to the video signal,
After high-definition processing is performed in the IDT processor, the aspect ratio conversion circuit is bypassed and output to the display without changing the aspect ratio, displaying a wide video signal, in the same way as when inputting the MUSE signal. .

[Example] An example of the present invention is shown in FIG. In Figure 1, l
O1 is an input terminal for a standard television signal (for example, an NTSC TV signal), 102 is an input terminal for a high-definition television signal (for example, a MUSE television signal), and 103 is an input terminal for a high-definition television signal (for example, a MUSE television signal). 6
: 9) A wide converter that converts to a standard television signal while maintaining the wide aspect ratio, and further detects the presence or absence of input of a high-definition television signal and outputs it.
04 is a first selector that switches between the video signal from the standard television signal input terminal 101 and the output signal (converted standard television signal) from the wide converter 103; 106 is an aspect ratio conversion circuit that compresses the video signal in the horizontal direction; 107 is a second selector; 10B is (1
6:9) aspect ratio and horizontal scanning frequency of approximately 31
．． A wide signal detection circuit 109 detects the aspect ratio of the signal from the input terminal 101 of the standard television signal (for the signal input from the input terminal 101, This is a video signal reproduced from a VTR, etc., and is basically a standard television signal, but there are also signals that have a wide aspect ratio and have a signal indicating that aspect added, so a circuit for detecting this), 110 a control method setting circuit 11 that sets a control method for a control circuit 111 that controls the operations of the first selector 104, the IDTV processor 105, and the second selector 107;
1 selects the first selector 104 using the high-quality television signal detection output from the wide converter 103, the detection signal from the wide signal detection circuit 109, and the setting output signal from the control method setting circuit 110. and said ID
This is a control circuit that generates and outputs operation control signals for the T-processor 105 and the second selector 107.

Below, in explaining the circuit operation in Fig. 1, depending on the type of input signal, (a) NTSC signal, (c) NTSC-compliant signal corresponding to wide aspect ratio, and (c) M
The case where three USE signals are input will be explained separately.

(In FIG. 1, we will explain the case where an NTSC signal with an aspect ratio of (4:3) is being received.The signal from the NTSC signal input terminal 101 is sent to the first selector 104. The signal is input to the IDTV processor 105 through the a-side terminal of the .

The IDT processor 105 mainly performs the following high-definition processing on the NTSC signal.

(1) Motion adaptive Y (luminance signal)/C (color signal) separation (2
) Motion adaptive scanning line interpolation (3) Noise reduction (4) Motion detection (5) Double speed conversion If an NTSC signal that has undergone such high definition processing is converted into a wide aspect ratio (16:9) as it is, If the image is displayed on the display 108 with the same ratio, the image will be played back as a horizontally long image. Therefore, the signal processed for high definition by the IDTV processor 105 is converted into an image by inserting other video signals such as planking on the left and right sides, as shown in FIG. 3(a), in the aspect ratio conversion circuit 106. Wide display with aspect ratio conversion 107
and display the regular image.

Here, the signal compliant with the NTSC signal is an NTSC signal from normal terrestrial broadcasting, satellite broadcasting, etc., or a reproduced signal close to the standard of the NTSC signal from a VTR, personal computer, etc.
A signal with standard synchronization that supports wide screens, and is a standard (
A signal that would be reproduced as a vertically long image if displayed on a display with an aspect ratio of 4:3.

This signal is generated when an NTSC signal is output from a camera having an image sensor with a wide aspect ratio of (16:9), or when the signal is sent to an NTSC VTR (4:9).
3) recorded as the aspect ratio signal.

This situation is shown in Figures 4(a) and (b). Figure 4 (
A) shows a video signal with a circle drawn as a video signal with a wide aspect ratio of (1 6 : 9). For example, this video signal may have an aspect ratio (16:9).
) After being imaged and recorded with a special camera, if it is displayed as a reproduced video signal on a (4:3) display, it will be displayed in a vertically elongated format as shown in Figure 4 (b). This results in a distorted image (16:9)
If displayed on a display with a wide aspect ratio,
The resulting image becomes a regular image as shown in FIG. 4(c).

Here, the fact that the recorded video signal is a wide aspect ratio signal is written in some format (for example, by inserting a special pulse signal during the blanking period), and this is written in the first video signal. If detected by the wide signal detection circuit 109 shown in the figure, it can be detected that the input video signal has a wide aspect ratio.

When such a video signal is input, the IDTV processor 105 performs the same processing as for a normal NTSC signal to achieve high definition.

The control circuit 111 knows from the detection signal from the wide signal detection circuit 109 that the video signal output after high-definition processing by the IDTV processor 105 is a signal with a wide aspect ratio. The container 107 is b
side, the aspect ratio conversion circuit 106 is bypassed, the image is guided to the display 108, and the image is displayed as a normal image.

Finally, a case will be described in which the MUSE signal input from the input terminal 102 is displayed. The MUSE signal input from the input terminal 102 is first input to the wide converter 103.

At this point, a high-quality television signal {K (MUSE signal) is detected and the MUSE signal is scan-converted into a signal having the scanning speed and number of scanning lines of an NTSC signal.

In FIG. 1, the control circuit 111 uses the high-definition television signal detection signal from the wide converter 103 to determine whether or not the MUSE signal is input.
selector 104, IDTV processor 105, and second selector 107. That is, when the MUSE signal is input, the first selector 104 selects the control circuit 111.
is connected to the b side under the control of wide converter 10
3 mainly performs scanning speed conversion and scanning line number conversion, so its output signal is a component signal.

That is, the luminance signal and color signal can be separated and output. Therefore, in the IDTV processor 105, only scanning line interpolation and double speed conversion processing are important, and Y/C separation is not particularly necessary, so the control circuit 111 notifies the IDTV processor 105 of this fact. I DTV processor 10
The second selector 107 is connected to the b side under the control of the control circuit 111 so that the output signal from the second selector 107 bypasses the aspect ratio conversion circuit 106 and is directly supplied to the wide display 108 . Therefore, (16:9)
The MUSE signal can be displayed on the display 10B with its wide aspect ratio.

In this way, in the embodiment shown in FIG.
Both SE signals can be displayed on a (16:9) wide display.

Note that here, the control circuit 111 determines the reception of the MUSE signal and automatically switches the first selector 104 and the second selector 107, but the control method setting circuit 110 It is also possible to manually switch between MUSE signal processing and NTSC signal processing without using the control circuit 111 by switching the settings in . The embodiment shown in FIG. 1 has been described above by classifying the cases of three input signals.

FIG. 3(b) is a block diagram showing the configuration of the aspect ratio conversion circuit 106 in FIG. 1.

In FIG. 3(b), 301 is the output terminal of the aspect ratio conversion circuit 106, and 302 is the output terminal of the aspect ratio conversion circuit 10.
6, 307 is an input terminal for the control signal from the control circuit l10, 303 and 304 are the first and second line memories, 305 is a fixed level generation circuit that outputs a signal at a certain fixed level, and 306 is the input terminal for the control signal from the control circuit l10. A selector 308 switches between the output signals of the first and second line memories 303 and 304 and the output signal of the fixed level generation circuit 305. Second line memories 303 and 304 and the selector 3
This is a controller that creates control signals for 06.

FIG. 3(C) is a timing chart showing operation waveforms of each part of the aspect ratio conversion circuit 106.

(A) shows the aspect ratio (4) input to the input terminal 301.
:3) video signal (in this case, a lamp signal).

The first and second line memories 303 and 304 receive their write control signal WE 1 (W
E: Write Enable (hereinafter abbreviated as WE), WE2, read control signal OEI (OE: Out
put Enable (hereinafter abbreviated as OE), OE2
It operates alternately for each line.

3(C) is the WEI signal, and the signal is written into the first line memory 303 when WE1 is at a low level. (a) in FIG. 3(c) is the first line memory 3.
The range of the video signal written in 03 is shown. The write clock WCK at this time is, for example, 8 fsc (fs
c is the frequency of the color subcarrier), etc. I in Figure 1
The same clock as that at the time of output of the DTV processor 105 is used.

(O) in FIG. 3C shows the line memory read control signal OE1. Therefore, the signal written one line before is read out here. At this time, the read clock RCK is about (4) the write clock WCK.
/3) The one with twice the frequency is selected.

(C) in FIG. 3(C) shows the read period. If the control signals WE2, OE2 of the second line memory 304 are set to have almost the opposite phase to the control signals WE1, OEI of the first line memory, the first and second line memories 303.30
4 are operated alternately, and a horizontally compressed ramp signal is obtained as shown in (force) in FIG. 3(c).

The solid line (force) in FIG. 3(C) indicates the first line memory 30.
3, the dotted line is the second line memory 304
The signal obtained with is shown. In order to insert a fixed level signal into the non-video period of the compressed signal (the shaded area in FIG. 3(a)), a fixed level signal from the fixed level generation circuit 305 and the first and second line memories are used. 303,30
A selector 306 selects and outputs the compressed video signal from 4.

Note that in the aspect ratio conversion circuit 106 of FIG. 3(b), a fixed level signal is inserted into the non-video period, but the signal inserted into this period may be other video signals, such as black level reproduction (not shown). It is also possible to insert a circuit reference value or a small screen of other video signals such as picture-in-picture.

The video signal compressed in this way is (16:9
) progressive scan display 10 with an aspect ratio of
7 and displayed.

In this way, when a (4:3) video signal is input, the control circuit 111 in FIG.
6 controls the signal to be compressed in the horizontal direction.

In FIG. 1, the control circuit 111 controls the IDTV processor 105 based on the detection from the wide signal detection circuit 109.
When it is known that the video signal output after high-definition processing is a wide aspect ratio signal, the aspect ratio conversion circuit 106 can be controlled so as not to perform the horizontal compression operation. , in this case, the bypass circuit by the second selector 107 is unnecessary.

This operation is performed by the controller 308 in FIG.
, by supplying the same clock to the write clock WCK and read clock RCK of the second line memories 303 and 304. Therefore, I.D.
The output signal of the TV processor 105 will be displayed as is on the wide display 107. Since the input signal has a wide aspect ratio, the aspect ratio conversion circuit 106 does not perform compression, so that the original wide video signal is displayed on the wide display as shown in FIG. 4(C). The circle that was recorded in a distorted shape as shown in Figure 4(b) returns to a perfect circle.

FIG. 5 is a block diagram showing a simple configuration example of the wide converter 103 in FIG. 1. In Figure 5,
501 is the input terminal of the wide converter, 502 is the output terminal of the scan conversion output of the wide converter, and 503 is the MUS
504 is a preprocessing circuit that performs signal processing such as A/D conversion, 505 is a scanning speed conversion circuit, 506 is an interpolation filter in the field, and 507 is a synchronization The processing circuit 508 is a high definition television signal detection circuit.

In FIG. 5, a pre-processing circuit 504 performs clamp processing and
The MUSE signal that has undergone processing such as /D conversion or de-emphasis is sent to a scanning speed conversion circuit 505, a synchronization processing circuit 507, and a high-definition television signal detection circuit 508.

The synchronization processing circuit 507 performs processing such as synchronization separation, control signal separation, and clock generation. The scanning speed conversion circuit 505 sets the horizontal scanning frequency to 33.75kHz.
z to about half of that 1 5. 75k7 to match the horizontal scanning frequency of the NTSC signal. However, even at this time, the wide aspect ratio of the video signal is maintained. This conversion process can be performed relatively easily using a buffer memory.

At this point, the high-definition television signal is converted to an aspect ratio of (4:3), and the video signal is as shown in Figure 4(b).
It is distorted as shown in the figure. The interpolation filter 506 performs intra-field interpolation using a filter with a built-in line delay circuit. Through this processing, some aliasing noise components appear as interference, but M
The USE signal can be restored without using a large-scale circuit such as a frame memory.

Furthermore, the high-definition television signal detection circuit 508 determines whether the incoming signal is a MUSE signal or not, and outputs the determination result from the output terminal 503 as a detection signal.

For example, whether or not an internally generated clock is synchronized with an incoming synchronization signal, the presence or absence of a PCM audio synchronization signal, etc. can be used for this purpose.

Next, the IDTV processor 105 as an important processing circuit in FIG. 1 will be explained in detail.

First, the principle of a normal IDTV processor dedicated to NTSC signals will be explained with reference to FIG.

In FIG. 6, 601 and 602 are the input and output terminals of the IDTV processor, 603 is a frame memory, 604 is a motion adaptive Y/C separation circuit, 605 is a field memory, 606 is a motion adaptive scanning line interpolation circuit, and 607 is a double speed The conversion circuit 608 is a motion processing circuit.

In an NTSC signal, the phase of the frequency-multiplexed color signal is inverted between frames, so in a still image signal, complete Y/C separation can be performed by performing calculations between frames.

On the other hand, in a moving image signal, since the inversion relationship of color phases between frames is broken, Y/C separation is performed by performing calculations within the same field. Therefore, the motion adaptive Y/C separation circuit 604 performs arithmetic processing on the current signal from the input terminal 601 and a signal delayed by one frame from the frame memory 603, and performs arithmetic processing using only the current signal from the input terminal 601. performs Y/C separation, and switches and outputs them according to the motion signal from the motion processing circuit 608.

That is, when the motion adaptive Y/C separation circuit 604 is used, complete Y/C separation can be performed on still images, and it is possible to prevent resolution deterioration.

Further, the motion adaptive scanning line interpolation circuit 606 uses a signal from one field before as an interpolation signal for a still image, and uses a signal created from upper and lower scanning lines as an interpolation signal for a moving image. Therefore, it is possible to significantly improve the vertical resolution of still images.

However, inter-field interpolation is not possible for moving images because it causes interference such as double images. Therefore, motion adaptive Y/C
Similar to the separation, the control signal of the motion processing circuit 608 is used to
Switch and output different types of interpolation signals.

The signal created by the motion adaptive Y/C separation circuit 604 (hereinafter referred to as the actual scanning line signal) and the motion adaptive scanning line interpolation circuit 60
The double speed conversion circuit 6 uses the interpolated scanning line signal created in step 6.
07 doubles the speed of the signal and creates a progressive scanning signal. In this way, by using the IDTV processor as shown in FIG. 6, it is possible to improve the definition of the NTSC signal.

The IDTV processor shown in FIG. 6 described above is compatible with only NTSC signals, but the IDTV processor 105 in the embodiment shown in FIG. 1 also needs to process component signals from the wide converter 103. Therefore, the circuit configuration is different from that shown in FIG.

FIG. 7 is a block diagram showing a specific example of the IDTV processor 105 in FIG. 1.

In FIG. 7, 701 is an input terminal for the control signal from the control circuit 110 in FIG. This is the same as the circuit shown in Figure 6.

When a normal NTSC signal is being received in FIG. 7, a control signal from the control circuit 110 in FIG. 1 connects the selector 702 to the a side through the input terminal 701. Therefore, the circuit shown in FIG. 7 operates in exactly the same way as the circuit shown in FIG. 6, and a high quality video signal can be obtained.

On the other hand, when receiving the MUSE signal, the input terminal 601
The signal from is a component signal of 525 scanning lines, a frame frequency of 307, and interlaced scanning. Therefore, there is no need to perform Y/C separation processing. If the motion adaptive Y/C separation circuit 604 performs processing at this time, line comb filter processing will be applied to the moving image portion, leading to deterioration of vertical resolution.

In the control circuit 111 of FIG.
The presence or absence of the MUSE signal is determined based on the signal from the selector 702 through the input terminal 107 of the IDTV processor 105.
control. At this time, the selector 702 is connected to the b side, making it possible to omit the processing of the motion adaptive Y/C separation circuit 604. Therefore, if the circuit of FIG. 7 is used as the IDTV processor 105 of FIG. 1, the shared receiving device of FIG. 1 will have a circuit configuration that prevents deterioration of vertical resolution.

In addition, Fig. 6. In the circuit of FIG. 7, only the luminance signal is explained, but the same can be said about the color signal.

The motion adaptive Y/C separation circuit 604 and frame memory 603 shown in FIG. 7 will be explained in detail below using FIG. 8.

In FIG. 8, 801 is an output terminal for Y/C separated signals, 802 is an input terminal for motion signals from the motion processing circuit 608 in FIGS. 6 and 7, and 803 and 805 are first and second addition terminals. 804 is a 1H delay memory, 806 is the first
This is a selector that switches the output signals of the second adders 803 and 805.

In FIG. 8, a first adder 803 adds the input signal and output signal of the frame memory 603, and can perform Y/C separation of the still image signal. The second adder 805 is 1
It adds the input signal and output signal of the H delay memory (1H is one horizontal scanning period) 804, and can perform Y/C separation of the moving image signal.

A selector 806 switches the signals of the first and second adders 803 and 805 according to the motion signal from the input terminal 802. Through this signal processing, a Y/C separation output optimal for the motion of the image can be obtained from the output terminal 801.

In addition, in the example of the ID TV processor shown in FIG.
The configuration of 05 is not limited to this.

For example, a noise reducer may be configured using the frame memory 603 in FIG. 7, and the Y/C separation process may be switched to when an NTSC signal is input, and the noise reducer process is switched to when a MUSE signal is input. In this case, even if the wide converter 103 performs in-field processing, S
There is an advantage that an image with improved /N can be obtained.

FIG. 9 shows the motion adaptive Y/C separation circuit 604 and frame memory 603 of FIG. 7 in detail.

In FIG. 9, 901 is a control signal from the control circuit l11 of FIG. 1, 902 is a selector that is switched depending on whether the MUSE signal is input or the NTSC signal is input, and the rest is the same as the circuit shown in FIG. 8. In this circuit example, when the MUSE signal is input, the selector 902 is connected to the b side by the control signal from the input terminal 901, and the line-type comb filters (804, 805) do not operate. Become. Selector 806 is switched by a motion signal from input terminal 802 as usual.

Therefore, the signal obtained from the output terminal 801 is a signal obtained by applying a comb filter between frames for a still image, and the input signal is output as is for a moving image signal. When this circuit example is used as a motion adaptive Y/C separation circuit in the IDTV processor 105 shown in FIG. 1, there is an advantage that the S/N ratio of the signal is improved with respect to a still image signal.

Figure 1O shows the motion processing circuit used in the present invention (Figures 6 and 7).
A detailed configuration diagram of 608) in the figure is shown. Motion processing circuit 60
8, the general outline of the motion processing circuit will first be explained using FIG. 10, similar to the explanation of the Y/C separation circuit described above, and then the embodiment shown in FIG. A circuit configuration that meets the above will be explained using FIGS. 11 and 12.

In the 101ffl, 1001 is a subtracter that calculates the difference between the input signal and the output signal of the first frame memory 6030, 1002 is a first low-pass filter (hereinafter referred to as LPF), 1003 is a first nonlinear conversion circuit, 1004 is a band pass filter (hereinafter referred to as BPF), 1005 is a color demodulation circuit, 1006 and 1007 are second and third frame memories, and 1008 is the input signal of the first frame memory 1006 and the second frame memory 1007. 1009 is a second nonlinear conversion circuit; 1010 is a second subtracter for calculating the difference between the output signals of the first . This is a synthesis circuit that synthesizes the output signals of the second nonlinear conversion circuit.

In the above example, only the luminance signal has been explained for the sake of simplicity, but with regard to the motion processing circuit of FIG. 10, the chrominance signal will also be considered.

In FIG. 10, the NTSC signal from the human input terminal 601 is divided into a luminance signal processing system and a color signal processing system. In the luminance signal processing system, a frame difference is obtained from the input/output signal of the first frame memory 603 by the first subtractor 1001. Since the color signal component is multiplexed in the high frequency range of this frame difference signal, the band is limited by the LPF 1002 to obtain the motion component of the image. The range of this signal is converted in the first nonlinear circuit 1003 so that it can be actually used.

In addition, in the color signal processing system, BPF1004 and color demodulation circuit 1
After converting into a baseband signal in step 005, two-frame delayed signals are created in first and second frame memories 1006 and 1007. 2 in the second subtractor 1008
A difference signal between frames is obtained, and similarly to the luminance signal processing system, a second non-linear conversion circuit converts the range so that it can be actually used, and obtains a motion component of the color signal.

The motion component of the luminance signal from the first nonlinear conversion circuit 1003 has only a low frequency motion component.

Further, the motion component of the color signal from the second nonlinear conversion circuit 1009 has a motion component in the color signal frequency band;
It has only slow frequency components of movement. Therefore, these two motion components are synthesized by a synthesis circuit 1010 and then used as an image motion signal.

FIG. 11 shows a motion processing circuit (6 in FIG. 7) used in the present invention.
This shows an example of 08).

In FIG. 11, 1101 is a wide converter 103
l102 is an input terminal for the color signal from the wide converter 103, 1103, 1105
．． 1106 are first, second, . The third selector, 1104, is a second LPF and is otherwise the same as the circuit of FIG.

First, the control signal from the input terminal 701 is the signal from the control circuit 111 shown in FIG.
Detecting when a signal is received, the first, second, . Third selector 1
103, 1105, and 1106.

When receiving an NTSC signal, the first, second, and third selectors 1
103, 1105, and 1106 are each connected to the a side, and operate exactly the same as the circuit shown in FIG.

When receiving the MUSE signal, the selectors 1103.1105.
1106 are each connected to the b side.

Since the signal from the wide converter 103 is a component signal, the color signal is input directly to the frame memory 1006 without passing through the BPFIOO 4 and the color demodulation circuit 1005. In the signal processing of the wide converter 103, the MUSE signal cannot be completely decoded.
Folding noise components are superimposed on the high frequency band, and an LPF is required for motion detection as in the case of NTSC signals.

Since the first LPF 1002 is set for motion detection of NTSC signals, the cutoff frequency is usually set around 2 MHz. In the MLISE signal converted into a standard signal by the wide converter 103, the information of the folded Takagi component is 1. There is a possibility that the frequency exists up to around 9 MHz, so it is preferable to select a cutoff frequency around 1.8 MHz for the second LPF 1104 in order to improve the performance of motion detection.

Therefore, in the example of FIG. 11, first and second LPFs 1002 and 1004 with different characteristics are prepared, and the second selector 11
05 allows switching between when receiving a MUSE signal and when receiving an NTSC signal. This example has a feature that optimal motion detection can be performed both when receiving a MUSE signal and when receiving an NTSC signal.

In addition, in order to simplify the circuit, the first. Second LPF1
002.1004 may be represented by one narrower frequency characteristic, and one LPF and the second selector 1105 may be omitted. Even in this case, although the characteristics are inferior to the circuit example shown in FIG. 11, there is an advantage that motion detection can be performed correctly for each of the luminance signal and chrominance signal of the MUSE signal.

FIG. 12 shows another specific example of the motion processing circuit 608.

In FIG. 12, 1201 is the first frame memory 6
A fourth selector tRH switches between the output signal of 03 and the output signal of the second frame memory 1006; l202 is a fifth selector that switches between the input signal of the first frame memory 603 and the second frame memory 10060; The other parts are the same as the circuit shown in FIG.

In this circuit, motion detection is performed using only the luminance signal. First, when an NTSC signal is input, each selector 1103, 1105, 1006, 1201.1202
is connected to the a side and operates in the same way as the circuit shown in FIG.

On the other hand, when the MUSE signal is input, each selector 1
103, 1105.1106, 1201.1202 is b
connected to the side. Therefore, the output signal of the second LPF 1104 becomes a motion signal derived from a one-frame difference in the luminance signal. The signals input to the second subtracter 1008 are the current signal of the luminance signal, that is, the input signal of the first frame memory 603 and the output signal of the third frame memory 1007.

Since the output signal of the first frame memory 603 is inputted to the third frame memory 1007 through the fourth selector 120l, the second subtracter 1008 obtains a signal representing a difference between two frames of the luminance signal. Since the MUSE signal is a signal processed by the encoder so that it goes around every two frames, the difference signal between two frames is always zero if it is a still image. Therefore, the output signal of the second subtracter 1008 does not need to be band limited.

In this way, the synthesis circuit 1010 obtains a motion signal obtained from the 1-frame difference signal and the 2-frame difference signal of the luminance signal. Some IDTVs do not perform interfield scanning line interpolation for color signals, but always perform intrafield scanning line interpolation. This type of IDT
In V, it is not necessary to perform motion detection of color signals. Therefore, if this circuit is used, wide converted MU
Optimal motion detection for SE signals can be performed.

Also, in the circuit of FIG. 12, one of the LPFs and the second
The selector 1l05 can be omitted.

As described above, according to the present invention, an NTSC signal, a wide aspect compatible NTSC compliant signal, and an MU
By performing optimal processing on the SE signal, it is possible to display the signal on a display having a wide aspect ratio and progressive scanning at double speed.

In this way, by using the present invention, it has become possible to display both the NTSC signal and the MUSE signal on a (16:9) wide display.

Next, for a special signal among NTSC signals, (
A case where a 16:9) wide display is used efficiently will be explained. FIG. 13(a) shows a CinemaScope size (hereinafter referred to as CinemaSco) signal, which is particularly used for movie software among NTSC signals.

As shown in FIG. 13(a), in a cinemaco-sized signal, planking is inserted at the top and bottom (shaded areas) of the screen to create a wide screen. When this signal is displayed on a (16:9) wide display using the above example,
Since it is displayed compressed in the horizontal direction, the image shown in Figure 13(b)
As shown in the figure, planking appears on the top, bottom, left and right of the screen, making it impossible to take advantage of the characteristics of the display (the screen cannot be used effectively). Also, if compression processing is not performed, Figure 13 (
This results in a distorted video signal that extends left and right as shown in c).

Therefore, if the horizontally extended video signal as shown in Figure 13(C) can be extended vertically as well, it would be possible to fill the screen with a wide aspect ratio of (16:9) as shown in Figure 13(d). This makes it possible to display images on the screen and make effective use of the screen.

In FIG. 13(C), the video signal is enlarged horizontally by 4/3 times and is distorted. Therefore, in order to obtain a distortion-free video signal in FIG. 13(d), it is necessary to also
Just enlarge it 3 times.

FIG. 14 shows the vertical expansion required in this way from a scanning line structure. The circle mark O in Fig. 14 indicates (the cross-section of) the scanning line, and
a) shows a cinemaco-sized scan line. Figure 14(b)
The number of scanning lines in FIG. 14(a) is increased by 4/3 times.

Therefore, if the scanning lines in FIG. 14(b) are displayed at the intervals shown in FIG. 14(a), the image can be enlarged by 4/3 in the vertical direction. That is, it is sufficient to create four scanning lines from three scanning lines, and it is sufficient to prepare a filter that creates new scanning lines at the rate shown by the numbers in FIG.

FIG. 15 shows the aspect ratio conversion circuit 10 in FIG.
6 is another example of the circuit.

In FIG. 15, 1501.1502 are first and second field memories, 1503 is 1H memory, 1504.
1507 is the first and second adders, 1505 and 1508 are the first and second coefficient multipliers, 1506 is the selector, l509 is the controller for the first and second field memories 1501 and 1502 and the selector 1506, etc. is the same as the circuit example shown in FIG.

The wide signal detection circuit l09 in the embodiment of FIG.
Detecting that it is a cinemaco size wide signal, the control circuit 111 supplies the control signal from the input terminal 307 to the circuit shown in FIG.

The cinematographic size can be determined, for example, by detecting planking at the top and bottom of the screen over several field periods.

The operation of field auctions 1501 and 1502 in FIG. 15 will be explained using the operation waveform diagram in FIG. 16. 16th
(A) in the figure shows the vertical synchronization signal of the input cinemasco size signal. (a) is a cinemaco-sized video signal (in this case, a ramp signal), (c) is a write control signal WEI of the first field memory 1501 supplied from the controller 1509, and (d) is a read control signal OE1.

Also, the second field memory 1502 contains (c), (
A control signal having a phase substantially opposite to that of the control signal WE2 and OE2 is supplied as WE2 and OE2. By using such a control signal and reading out the same line once every three lines, it is possible to obtain a vertically expanded signal without field shift as shown in (e).

Here, if the signal input to the line memory 1503 is B and the signal output from the line memory is A, the signal input to the a terminal of the selector 1506 is B, and the signal input to the b terminal is ( A+B)/2, the signal input to the C terminal is A. Therefore, the aspect ratio conversion circuit 106
The signal output from the output terminal 302 of the selector 150
When 6 is connected to terminal a, (A+3B)/4, b
When it is connected to the terminal, it is (A+B)/2, and when it is connected to the C terminal, it is (3A+B)/4.

Furthermore, if two lines of the same signal are read out from the field memory, A=B, so a signal A is output to the output terminal 302.

The controller 1509, as shown in FIG.
The same line is read out once every three lines from the second field memories 1501 and 1502, and the connection of the selector 1506 is changed as shown in the selector terminal names in FIG. 17 accordingly.

In this way, the aspect ratio conversion circuit shown in FIG. 15 can perform optimal filter processing to create new scanning lines as shown in FIG.
), it is possible to display a cinema-sized video signal on a wide screen.

Note that in the circuit shown in Figure 15, two field memories are used to simplify the explanation, but the same operation can be performed with a single memory as long as the memory can perform writing and reading independently. .

Furthermore, in FIG. 15, the horizontal compression operation in the circuit of FIG. 3 can also be performed by controlling the memory.

In other words, this circuit has the advantage that images can be reduced and enlarged freely.

[Effects of the Invention] According to the present invention, it is possible to display a high-definition television signal, an NTSC-compliant signal compatible with a wide aspect ratio, and an NTSC signal on a progressive-scan display having the same wide aspect ratio. becomes possible.

Furthermore, it is possible to convert high-definition television signals to the scanning speed of standard television signals relatively easily, and in order to improve the image quality of the signal, the image quality improvement circuit for NTSC signals can be shared, without increasing the circuit scale. High image quality can be achieved.

Further, the circuit for improving the image quality of NTSC signals can perform optimal signal processing and optimal motion detection when inputting a high-definition television signal, and can achieve high image quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a conventional down converter display method, and FIG.
The figure is a diagram showing the display method, circuit configuration, and timing of operation waveforms by the aspect ratio conversion circuit used in the present invention.
The figure is an explanatory diagram of a video signal with a wide aspect ratio.
The figure is a block diagram showing an example of the configuration of a wide converter.
7 is a block diagram showing a specific example of the IDTV processor used in the present invention. FIG. 8 is a block diagram showing a Y/C separation circuit in the IDTV processor. The diagram shows I used in the present invention.
A block diagram showing a specific example of a Y/C separation circuit of a DTV processor, Fig. 10 is a block diagram showing a motion processing circuit in an I DTV processor, and Figs. 11 and 12 respectively show the movement of an I DTV processor used in the present invention. A block diagram showing a specific example of a processing circuit, FIG. 13 is an explanatory diagram of a display method for a cinemaco-sized video signal, FIG. 14 is an explanatory diagram of a process for enlarging the screen in the vertical direction, and FIG. 15 is an aspect diagram used in the present invention. A block diagram showing another specific example of the ratio conversion circuit, FIG. 16 is a timing diagram of the operating waveforms of FIG. 15,
The 17th episode is an explanatory diagram of how to enlarge the screen. Explanation of symbols 101...NTSC compliant signal input terminal, 102...
・High-quality television signal input terminal, 103... wide converter, 104... selector, 105... ■
DTV processor, 106... Aspect ratio conversion circuit, 107... Selector, 108... Wide display, 109... Wide signal detection circuit, 110... Control method setting circuit, 111... Control circuit , 303, 30
4... Line memory, 305... Fixed level generation circuit, 306... Selector, 308... Controller,
504... Preprocessing circuit, 505... Scanning speed conversion circuit, 506... Interpolation filter, 507... Synchronization processing circuit, 508... High quality television signal detection circuit,
603...Frame memory, 604...Motion adaptation Y
/C separation circuit, 605...field memory, 606
. . . Motion adaptive scanning line interpolation circuit, 607 . . . Double speed conversion circuit, 608 . . . Motion processing circuit, 702 . , 806, 902... selector, 1001.
1008...Subtractor, 1002...Low pass filter, 10031009...Nonlinear conversion circuit, Engineering 004
... band pass filter, 1005 ... color demodulation circuit,
1006.1007...Frame memory, 1010.
...Synthesizing circuit 1103, 1105.1106...Selector, 1104...Low pass filter, 1201.12
02...Selector, 1501.1502...Field memory 1503...LH memory, 1504.150
7...Adder, 1505.1508...Coefficient unit, 1
506...Selector, 1509...Controller.

Claims (1)

[Claims] 1. A sequential scanning method with a wide aspect ratio is adopted by selectively switching between a high-definition television signal input from a first terminal and a standard television signal input from a second terminal. A high-definition television signal that detects whether or not there is a high-definition television signal as a signal input from the first terminal (102) in a high-definition/standard television shared receiving device that displays a screen on a common display. A wide receiver comprising: a detection circuit; and a scan conversion circuit that scan-converts the high-definition television signal input from the first terminal into a signal having a number of scan lines and a scan speed conforming to a standard television signal, and outputs the signal. a converter (103); and a wide signal detection circuit that detects a wide signal having a wide aspect ratio when a wide signal having a wide aspect ratio is added to the standard television signal inputted from the second terminal (101); (109), a standard television signal input from the second terminal (101) and a high-definition television signal after scan conversion from the scan conversion circuit are input, and one of them is selected. a selector (104) that outputs an output signal; and an IDTV processor (10) that receives an output signal from the selector (104), performs signal processing, doubles the speed, and outputs the signal.
5), an aspect ratio conversion circuit (106) that receives the output signal of the IDTV processor (105), converts the aspect ratio to a wide aspect ratio, and outputs the wide aspect ratio; bypass selection means (107) for outputting the output to the display through the ratio conversion circuit (106) or bypassing; and detection output from the high-definition television signal detection circuit and the wide signal detection circuit (109); ), and controls the selector (104), the bypass presence/absence selection means (107), and the IDTV processor (105) based on the detection output from the IDTV processor (105). A high-definition/standard television common receiving device. 2. In the high-definition/standard television shared receiving device according to claim 1, the wide converter (103) comprises:
a preprocessing circuit (504) that performs signal processing as preprocessing including A/D (analog/digital) conversion on the high-definition television signal input from the first terminal;
A scanning speed conversion circuit (505) converts the scanning speed and number of scanning lines of the preprocessed signal to those of a standard television signal and outputs the converted signal, and performs intra-field interpolation processing on the output signal of the scanning speed conversion circuit. Interpolation filter (5
06), and a synchronization processing circuit (507) that reproduces a synchronization signal from the preprocessed signal and supplies it to the interpolation filter.
), and a high-definition television signal detection circuit (5) that detects the presence or absence of a high-definition television signal from the preprocessed signal.
08) A high-definition/standard television common receiving device characterized by comprising: 3. The high-definition/standard television shared reception device according to claim 1, wherein the IDTV processor (105) includes a first frame memory (603) that delays an input signal by one frame period and outputs the delayed input signal; a motion processing circuit (608) that receives the input signal and output signal of the first frame memory and detects the motion of an image in the signal;
a motion adaptive Y/C separation circuit (604) that performs Y (luminance)/C (color) separation of the signal according to a motion detection output given from the motion processing circuit (608); and an input of the first frame memory. a selector (702) that switches between the signal and the output signal of the motion adaptive Y/C separation circuit and outputs either one;
Field memory that outputs after delaying the field period (
605), and a motion adaptive scanning line interpolation circuit (606) which receives the input signal and output signal of the field memory and creates and outputs an interpolated scanning line according to the motion detection output given from the motion processing circuit (608). and a double-speed conversion circuit (607) which receives the output signal of the selector (702) and the output signal of the motion-adaptive scanning line interpolation circuit, performs double-speed conversion to create a sequential scanning signal, and outputs the same. A high-definition/standard television shared receiving device, characterized in that the selector (702) is configured to switch between when receiving a high-definition television signal and when receiving a standard television signal. 4. The high-definition/standard television shared receiving device according to claim 3, wherein the motion adaptive Y/C separation circuit (60
4) is a first adder (803) that adds the input signal and output signal of the first frame memory (603) and outputs the result.
), a 1H delay memory (804) that delays and outputs the input signal of the first frame memory (603) by 1H (line) period, and adds the input signal and output signal of the 1H delay memory and outputs the result. a second adder (805), the input signal of the 1H delay memory and the second adder (805);
), and a second selector (902) that outputs either one by switching between the output signals of the first adder (803).
) and a third selector (806) that switches between the output signal of the second selector (902) and outputs either one of the output signals of the second selector (902). )
1. A high-definition/standard television shared receiving device, characterized in that the signal is switched between when receiving a high-definition television signal and when receiving a standard television signal. 5. In the high-definition/standard television shared receiving device according to claim 3, the motion processing circuit (608) calculates a difference between the input signal and the output signal of the first frame memory (603) and outputs the difference. a first subtractor (1001);
first and second low-pass filters (1002, 1104) that respectively apply different band limits to the output of the first subtracter and output the results; and the first low-pass filter (1002). output and the second low-pass filter (
a fourth selector (1105) that switches between the output of the fourth selector (1104) and outputs one of the outputs;
a first nonlinear converter (1003) that converts the range of the output signal of (105) and outputs it; and a bandpass filter that applies band limitation to the signal input from the standard television signal input terminal and outputs the resultant signal. (1004), a color demodulation circuit (1005) that demodulates and outputs a color signal from the output signal of the bandpass filter, and a color demodulation circuit (1005) that demodulates and outputs a color signal from the output signal of the bandpass filter, and a color signal that outputs the color signal from the color demodulation circuit and the wide converter (103). a fifth selector (
1106), a second frame memory (1006) that delays the output signal of the fifth selector (1106) by one frame period, and outputs the output signal after delaying the output signal of the fifth selector (1106);
6), a third frame memory (1007) which outputs the output signal after delaying it by one frame period, and an input signal of the second frame memory (1006) and an output signal of the third frame memory (1007). a second subtractor (1008) that calculates and outputs the difference;
8), a second nonlinear converter (1009) that converts the range of the output signal and outputs the output signal, and the first nonlinear converter (1009)
003) and the output of the second nonlinear converter (1009), and the fourth selector (1105) is configured to receive high-definition television signals. A high-definition/standard television common receiving device characterized in that the device is configured to switch depending on the time and standard television signal reception. 6. In the high-definition/standard television shared receiving device according to claim 3, the motion processing circuit (608) calculates a difference between the input signal and the output signal of the first frame memory (603) and outputs the difference. a first subtractor (1001);
first and second low-pass filters (1002, 1104) that respectively apply different band limits to the output of the first subtracter and output the results; and the first low-pass filter (1002). output and the second low-pass filter (
a fourth selector (1105) that switches between the output of the fourth selector (1104) and outputs either one;
1105) which converts the range and outputs the output signal.
a nonlinear converter (1003), a bandpass filter (1004) that performs band-limiting on a signal input from the standard television signal input terminal and outputs the resultant signal, and a chrominance signal from the output signal of the bandpass filter. a color demodulation circuit (1005) that demodulates and outputs the color signal, and a fifth selector that switches between the color signal from the color demodulation circuit and the color signal from the wide converter (103) and outputs either one. (1106), a second frame memory (1006) that delays the output signal of the fifth selector (1106) by one frame period, and outputs the output signal after delaying the output signal of the fifth selector (1106);
006) and the first frame memory (60
a sixth selector (1201) that switches between the output signals of 3) and outputs one of the output signals;
a third frame memory (1007) that delays the output signal of 01) by one frame period and outputs the same; an input signal of the first frame memory (603); and an input signal of the second frame memory (1006); a seventh selector (1202) that switches between the two and outputs either one;
a second subtracter (1008) that takes and outputs the difference between the output signal of the selector (1202) and the output signal of the third frame memory (1007);
8), a second nonlinear converter (1009) that converts the range of the output signal and outputs the output signal, and the first nonlinear converter (1009)
003) and the output of the second nonlinear converter (1009).
1201) and a seventh selector (1202) are configured to switch between when receiving a high-definition television signal and when receiving a standard television signal.