JPH03218541A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device (hereinafter referred to as RAM) in which data can be written and read at any time.
The present invention relates to a RAM in which stored data can be reset.

[Conventional technology]

FIG. 7 shows the circuit configuration of this type of conventional RAM, and FIG. 8 shows a circuit diagram of a memory cell 10d used therein. In FIG. 8, 11-15 are n-channel MOS transistors, 16-18 are inverting amplifiers, WD-WD is a write signal input terminal, RD is a read signal output terminal, AD is an address input terminal, and WEN is a write control signal input terminal. It is. In the RAM shown in FIG.
0d are arranged in a matrix. In the figure, 20 is an address decoder that selects word lines WAO to WAl from input signals input to address input terminals AO to An, and word lines WAO to WAn are address input terminals of memory cells in each column, respectively. Connected to AD. 30a is a data input terminal DinO~Dinm
receives data from the signal input terminal WD of each row of memory cells.
・Bit line WDO connected to WD・WDO~WD
A write data output buffer 40a that outputs write data to m-WDm is a write control signal input terminal W1.
A write control circuit 50 outputs a write signal to the memory cell lod from a signal input to the memory cell lod to the write lines WEO to WEm connected to the write signal input terminal WEN of the memory cell 10d in each row; This is a read data output buffer that receives signals from the read bit lines RDO to RDm connected to the read signal output terminal RD of the cell 10d and outputs read data to the data output terminals DoutO to Doutm. Further, 60b is a memory reset control circuit that outputs a signal for resetting the data stored in the memory cell 10d from the reset signal input to the reset signal input terminal CLR, and its output is output from the address decoder 20 and the write data output. It is connected to a buffer 30a and a write control circuit 40a.

This RAM reset operation is performed as follows. When a reset signal is input to its reset signal input terminal CLR, the memory reset control circuit 60b transmits a reset signal to the address decoder 20, write data output buffer 30a, and control circuit 40a. Upon receiving the signal from the control circuit 60b, the decoder 20 outputs the address input terminal AD.
O~? word lines WAO~W regardless of the input signal of Dn.
Activate all of l. In addition, the write data output buffer 30a predetermines its output signal, that is, write data to the memory cell lOd, in response to a signal from the control circuit 60b, regardless of the data input to the data input terminals Din■-Dinm. Fixed to the specified value. Furthermore, the write control circuit 40a also controls the control circuit 60b.
, and activates its output signal, that is, the write control signal to the memory cell lOd, regardless of the signal input to the write control signal input terminal Wπ. As a result, an active signal is input to the address input terminal AD and the write control signal input terminal WEN of all memory cells 10d, and the transistor 1 in the memory cell 10d is inputted with an active signal.
1, 12, 13, 14, and 15 are rendered conductive, and the reset data output from the write data output buffer 30a is written into all memory cells. Thereafter, when the reset signal to the reset signal input terminal CLR is completed, all the word lines, bit lines, and write lines complete the operation for resetting the memory and return to their original states. the result,
The reset data written to all memory cells is held, and the memory reset operation ends.

[Problem to be solved by the invention]

In the conventional RAM described above, upon reset, all word lines, of which only one is active during normal operation, are forcibly made active, and data from all memory cells is transferred via the write data output buffer. is being reset. Therefore, the write data output buffer is required to have a large drive capacity, but since this buffer only needs to drive one memory cell during normal operation, it has sufficient drive capacity for the reset operation. Not yet. Therefore, conventional RAM
In this case, especially when the number of words is large, it takes a long time to reset or an accident occurs in which the reset fails.

[Means to solve the problem]

The semiconductor memory device of the present invention has a plurality of memory cells arranged in a matrix, can read data of any memory cell among the plurality of memory cells at any time, and can detect the presence of a write permission signal issued by a write control circuit. In a semiconductor memory device in which data can be written into any memory cell at any time, each memory cell can be reset to the "1" or "OI" state by an external signal. An element capable of resetting a memory cell includes an element capable of resetting a memory cell that is connected between a particular point on the memory cell and a power supply and/or between another particular point on the memory cell and a ground point. This is a switching element that is

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram of a memory cell 10a used therein, and in these diagrams, parts common to the conventional parts in FIGS. 7 and 8 are given the same reference symbols. Therefore, duplicate explanations will be omitted.

In the memory cell 10a used in this embodiment, as shown in FIG. An n-channel MOS transistor la is connected between the ground point and the input terminal of the inverting amplifier l6, and an n-channel MOS transistor la is connected between the ground point and the input terminal of the inverting amplifier l6.
b is connected.

In FIG. 1, 30 is a data input terminal DinO~Di
Receives a signal on the bit line WDO/WDO~WDm-
A write data output buffer 40 that outputs write data to WDm receives a signal at a write control signal input terminal WE゜ and sends a control signal to each write line WEO to WEm via a write enable signal output buffer 4l. The control circuit can output a write permission signal to the memory cell only when the signal input to the reset signal input terminal CLR is at a high level. 60 is a reset terminal CLD, C of the memory cell based on a reset signal inputted to the input terminal CLR.
This is a memory reset control circuit that outputs complementary data to the LD via reset signal lines CL, CL.

Next, the reset operation of the circuit shown in FIG. 1 will be explained.

When a low level signal is input to the reset signal input terminal CLR, the memory reset control circuit 60 outputs a high level signal to the reset signal line OL and a low level signal to σT. Reset control circuit 6
The signal output from 0 is also input to the write control circuit 40, so that the write permission signal output from the buffer 41 is at a low level regardless of the signal input to the write control signal input terminal Wπ. As a result, the buffer 4l becomes write-inhibited.

The reset terminal CLD of each memory cell connected to the reset signal line OL becomes high level, and the reset terminal cLD of each memory cell connected to CL becomes low level, so that transistors lb and 1a are respectively turned on. become. When the transistor lb turns on, the inverting amplifier l
The input level of 6 moves to the lower side, and the transistor la
By turning on, the input level of the inverting amplifier l7 moves in the direction of increasing.

After the input level of the inverting amplifier l6 becomes sufficiently low and the input level of the inverting amplifier 170 becomes sufficiently high, when the signal input to the reset signal input terminal CLH is set to a high level, a low level signal is applied to the reset signal line CL. A high-level signal is output to each of the "σT" signals, and both transistors la.1b in each memory cell 10a connected to the reset signal lines CL and n are turned off, and the reset operation is completed. When the signal input to the reset signal input terminal CLR becomes high level, the write permission signal output from the buffer 4l is output from the write control signal input terminal WE.
It is possible to carry out vehicle control by a control signal input to the control signal.

As described above, in a conventional RAM with a reset function, all word lines are selected during a reset operation and reset data applied from a bit line is written to all memory cells, but in this embodiment, By providing a reset function to the memory cell itself, even when the number of words is large, the data can be stored quickly and reliably without increasing the driving force of the buffer for outputting data to the bit line. can be reset.

In the above embodiment, each memory cell is reset using two transistors la and lb, but it is also possible to use only one of the transistors. In that case, either of the reset signal lines CL, CL can be removed.

FIG. 3 is a block diagram showing a second embodiment of the invention. The difference from the first embodiment is that two types of memory cells, IOa and 10b, are used for storing data. 10a is the memory cell shown in FIG.
10b is a memory cell shown in FIG. The difference between memory cell lOb and memory cell 10a is that in IOb, n-channel MOS} transistor lb is replaced by an inverting amplifier 17.
p-channel MOS}
The transistor la is connected to the input terminal of the inverting amplifier l6 and the power supply VD.
This is the point inserted between D. For this purpose, memory cell 10
In memory cell 10b, the stored data was reset to "O" by inputting a reset signal, whereas in memory cell 10b
Then, when the reset signal is input, the stored data is reset to "1". Therefore, in the RAM shown in FIG. 3, by inputting a reset signal, the stored data is reset to "θ" where the memory cell 10a is used, and to "1" where the memory cell 10b is used. In this embodiment, by using the memory cells shown in FIG. 2 and the memory cells shown in FIG. 4, the stored data can be returned to any value determined at the design stage simply by inputting a reset signal to the RAM. I can do it.

In the memory cell used in the above embodiment, the transistors la,
Although the reset state is set using lb, the memory cell in FIG. 2 can be changed to the one in FIG. 9, and the memory cell in FIG. 4 can be changed to the one in FIG. 10. In FIG. 9, a NAND gate 90 is used in place of the inverter l6 of FIG. 2, and one input of the NAND gate 90 is connected to the reset terminal CLD. Therefore, when CLD becomes low level,
The output of the NAND gate 90 becomes high level, allowing resetting. On the other hand, in FIG. 10, a NAND gate 100 is used in place of the inverter 17 in FIG. 4, and operates in the same manner.

FIG. 5 is a block diagram showing a third embodiment of the present invention. In this embodiment, a memory cell lOc shown in FIG. 6 is used. In the memory cell 10c, as shown in FIG.
OS} transistor lbl is connected, and the inverting amplifier 17a
The gate is connected between the input terminal of CLD2 and the ground.
n-channel MOS} transistor lb2 is connected to. This memory cell has a reset terminal CLD
When a high level signal is input to I, it is reset to "0", and when a high level signal is input to reset terminal CLD2, it is reset to "L".

In FIG. 5, 60a is a reset signal input terminal CL.
When a low level signal is input to R, the switch circuit 6
This is a memory reset control circuit that sends a high-level reset signal to the write control circuit 40 and puts this circuit in a write-inhibited state. The switch circuit 61 outputs the output of the reset control circuit 60a to either of the reset signal lines CLZ and CL2 according to the signal input to the switch signal input terminal SW. Signal line CL
Reset terminals CLDI and CLD2 of the memory cell lOc are connected to I and CL2, respectively.

According to this embodiment, all memory cells can be reset to "0" or "1" by controlling the signal input to the switch signal input terminal SW.

〔Effect of the invention〕

As explained above, since the present invention incorporates a reset circuit having a reset terminal in the memory cell itself, according to the present invention, even in a RAM with a large number of words, data can be input to the write bit line. Memory contents can be reliably reset in a short time without increasing the driving force of the output write data output buffer.

[Brief explanation of drawings]

1, 3, and 5 are block diagrams showing embodiments of the present invention, and FIGS. 2, 4, and 6 are circuit diagrams of memory cells used in the embodiments of the present invention, respectively. Figure, 7th
The figure is a block diagram showing a conventional example, FIG. 8 is a circuit diagram of a memory cell used in the conventional example, and FIG. 9 and FIG. It is a circuit diagram.

Claims (4)

[Claims] (1) A plurality of memory cells are arranged in a matrix,
A semiconductor memory device that can read data from any memory cell among the plurality of memory cells at any time, and can write data to any memory cell at any time in the presence of a write permission signal issued by a write control circuit. A semiconductor memory device characterized in that each memory cell includes an element that can reset the respective memory cell to a "1" or "0" state by a signal applied from the outside. (2) An element that can reset memory cells is
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a switching element connected between a specific point of the memory cell and a power supply and/or between another specific point of the memory cell and a ground point. (3) The memory cell has a feedback loop for storing data, and this loop includes a gate circuit that generates a predetermined level at its output in response to the externally applied signal. 1. The semiconductor memory device according to 1. (4) The semiconductor memory device according to claim 1, 2 or 3, wherein the write control circuit does not issue a write permission signal when resetting the memory cell.