JPH03218577A - Picture processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device used for editing graphic image data.

[Conventional technology]

The process of displaying first image data read from a memory or the like at an arbitrary position on a graphic screen has conventionally been performed by software 1-. FIG. 11 shows a flowchart of image data synthesis processing. First, any first image data stored in a memory or the like is sequentially read for each transfer data length, which is a unit of processing (step),
This first image data is shifted bit by bit.
p2). What we need to do here is bit shift processing, in order to display it at the desired position on the graphic screen.
This is because bit-by-bit adjustment is required.

This bit-shifted first image data is stored in a graphic display storage device (hereinafter referred to as VRAM) corresponding to a graphic screen.
However, since this writing is performed for each transfer data length, unnecessary data may be included before and after the first image data. That part is VRA
It is necessary to replace it with the corresponding portion of the second image data already stored in the write position of M. Therefore, the second image data at the writing position is read in advance (step 3).
), after performing partial replacement with the first image data (step 4), the replaced first image data is written into the VRAM (step 5).

These processes are then repeated until all the first image data is read from the memory or the like (step 6). After all the first image data has been written, the image data in the VRAM is displayed on the graphic screen (step 7).
).

Conventionally, all such software processing was performed by instructions from a central processing unit (hereinafter referred to as CPU).

[Invention or problem to be solved]

Image data synthesis processing using such software is
The problem was that the CPU was monopolized throughout the process. In particular, the time spent on the CPU or bit manipulation processing was long.

Therefore, we improved the data bit shift processing and bit mask generation processing that were supported by software, and
The challenge was to reduce the load on U. The present invention solves these problems, and aims to reduce the load on the CPU by performing image data synthesis operations at a faster speed.

[Means to solve the problem]

In order to solve the above problems, an image processing device of the present invention includes:
an image data shift circuit section that shifts the first image data bit by bit in the horizontal direction in order to replace it with the second image data;
an image data synthesis circuit unit that replaces the image data with second image data read from the second storage device and stores it in an area of the second storage device where the second image data was stored;
It is comprised of a control device that issues a command to read first image data stored in a first storage device, process the data in an image data shift circuit section and an image data synthesis circuit section, and store it in a second storage device. There is.

[Effect]

According to the configuration of the present invention, the first image data is read from the first storage device and transferred to the image data shift circuit section according to a command from the control device. The image data shift circuit section shifts the first image data in the horizontal direction bit by bit. The first image data subjected to the shift processing is transferred to the data synthesis section, and is synthesized with the second image data read from the second storage device according to a command from the control device. The combined image data is stored in the second storage device according to a command from the control device.

〔Example〕

FIG. 1 is a block diagram of an image processing apparatus showing an embodiment of the present invention. This image processing device includes an image data memory device 100 storing first image data, a VRAMI 10 storing second image data, and horizontal adjustment of the first image data in order to replace it with the second image data. an image data shift circuit section 120 that performs the following operations; an image data synthesis circuit section 140 that replaces the first image data with the second image data and stores it in the VRAMI 10; and the image data shift circuit section 120 and the image data synthesis circuit section. 140, and a CPU 160 that controls data processing of 140. The image data shift circuit section 120 includes a bit shift section 121 that shifts the first image data by the necessary number of bits toward the end, a bit control circuit 131 that controls bit shift processing of the bit shift circuit section, and an image data synthesis circuit section. A shift bit storage section 132 storing information on the number of shift bits to be transferred to the shift bit storage section 140 and a delay element 133 are provided. In addition, the image data synthesis circuit section 140 includes a data synthesis section 1 that writes the first image data to the VRAMI 10.
41, and a data synthesis unit 141 that generates a mask pattern.
A mask generation unit 151 is provided for transmitting data to a mask. The bit shift unit 12] includes a rotation circuit 1.
22, first latch circuit 123, second latch circuit 124,
A selector circuit 125 is provided, a data synthesis section 141 is provided with a synthesis circuit 142 and a third latch circuit 143,
The mask generation section 151 includes a mask generation circuit 152 and an arithmetic circuit 153.

Next, an overview of the processing of this embodiment will be explained using FIG. 2. The display screen 190 in FIG. 2 is an image before the start of processing. The display screen 198 is an image after the processing is completed.

In the operation of this embodiment, the user first clicks the upper left point and lower right point of the butterfly with a mouse or the like to designate the image data 191b. Next, the destination image data 19
By specifying 2b with a mouse or the like, the butterfly flying in the upper left of the display screen 190 can be moved between the flowers in the lower right. To explain this moving process in detail, image data 191 stored in image data memory device 100 is read out and transferred to bit shift section 121. The bit shift unit 121 shifts the image data 1 so that it is between the butterfly picture and the flower picture of the image data 192.
Image data 194 is created by shifting 93 to the right.

The image data 194 created in this way is transferred to the data synthesis section 141. The data synthesis unit 141 uses the mask pattern 195 generated by the mask generation unit 151 to combine image data 1 read from the VRAMI ICl.
Combine with 96. Through this compositing process, the image data 19
7 is created. This image data 197 is transferred to VRAMI
By writing to the location where the image data 192 of 10 was stored, a display screen 198 is created in which the butterfly has moved among the flowers.

Is the data you want to read from the image data memory device 100 only 19 lb of image data?
Since data access to the image data memory device 100 is performed in transfer data length units, it is necessary to read out the entire image data 191 divided by transfer data length units. In addition, the area to be stored in the VRAM 110 is the image data 192.
Since the data access of VRAMI 10 is also performed in transfer data units, it must be written as image data 192 divided by transfer data length units. Therefore, image data [9] is converted into image data [19]
By writing in position 2, the butterfly picture (image data 1 9 1 b) is placed between the flower pictures (image data 192b).
I realized the process of moving it to .

By the way, the above-mentioned shift processing and combining processing are performed using the leading bit number information (D
BA), storage pointer information (SBA), and transfer bit length information (BLEN). Here, the leading bit number information (DBA) is the number of bits of the image data 192a, and is information for determining the leading position for moving the butterfly picture between the flower pictures. Also, storage pointer information (SB
A) is the number of bits of the image data 191a; This is information about the length from the beginning position of the data 191 to the area in which the butterfly is specified by the user. Additionally, transfer bit length information (B
LEN) is information about the width of the area containing the butterfly specified by the user.

Next, returning to FIG. 1, a detailed outline of the processing of this embodiment will be explained. First, according to a command from the CPU 160,
Information such as the number of leading bits, storage pointer, and transfer bit length, which are initial data necessary to write the first image data to VRAMI 10, is stored in the shift bit storage section 13.
2 is input.

Processing is then started in the image data shift circuit section 120 and the image data synthesis circuit section 140 based on these initial data. In response to a command to start processing from the CPU 160, the first image data stored in the image data memory device 100 is read for each transfer data length and transferred to the image data shift circuit section 120. This reading process from the image data memory device 100 is performed continuously until all the first image data has been read.

The first image data 171 transferred to the image data shift circuit section 120 is first given to the rotation circuit 122. The rotation circuit 122 includes a bit control circuit 13.
The number of rotations is given from 1, and rotation processing is performed for the number of rotations. The rotation number is determined by the bit system # circuit 131 reading the leading bit number information (DBA) and storage pointer information (SBA) stored in the shift bit storage section 132. The rotated first image data 172 is transferred to the first latch circuit 12.
Transferred to 3. In the first latch circuit 123, when the twelfth lock signal applied from the clock terminal 180 is applied through the delay element 133, the first image data 173 is sent to both the second latch circuit 124 and the selector circuit 125.
is transferred. The first data transferred to the second latch circuit 124
Image data 173 is transferred to selector circuit 125 in response to the next first clock signal. In the selector circuit 125, the first latch circuit 123 and the second latch circuit 124
The two first image data 173 and 174 transferred from the first image data 173 and 174 are synthesized bit by bit and transferred to the image data synthesis circuit section 140. Note that the compositing process here will be described later. The transferred first image data 175 is given to the synthesis circuit 142.

In addition to the first image data 175, the synthesis circuit 142 also receives third image data 175.
The second image data 176 stored in the latch circuit 143 is applied. This second image data 176 is stored in a desired address of VRAMI 10 to be written from now on, and the second image data 177 is transferred to the third latch circuit 143 at the timing of the second clock signal applied from the clock terminal 181. It is something. The first image data 175 and the second image data 176 are stored in the mask generation circuit 1.
The synthesis circuit 142 based on the mask information generated in 52
can be replaced with The first image data 178 replaced by the synthesis circuit 142 in this way is replaced by the second image data 17
The same address in the VRAM 110 where 7 was stored is overwritten.

Next, the operation of the mask generation circuit 152 will be explained using the circuit diagram of FIG. The mask generation circuit 152 is a register A2.
01, register B202, state generation circuit 203 and 1
It is composed of six selector circuits 204-208. The leading bit number information (DBA), storage pointer information (SBA), and transfer bit length information (BLEN) stored in the shift bit storage section 132 are input to the arithmetic circuit 153,
A mask pattern for creating a bit mask signal is generated. Each generated mask pattern is given to register A201 and register B202 of mask generation circuit 152, and transferred to 16 selector circuits 204-208. Each selector circuit has input terminals A-E and S, and input terminal A receives a mask pattern from register A201, and input terminal B receives a mask pattern from register B202.

Furthermore, mask pattern selection data is input to the input terminal S from the state generation circuit 203. Although the input terminal S is represented by one signal line in the figure, it actually consists of a plurality of signal lines. Furthermore, the bit-by-bit AND of the mask patterns stored in register A201 and register B202 is input to input terminal C, and +
A 5V power supply terminal is connected to the input terminal E, and GND is connected to the input terminal E. Then, each selector circuit selects from mask patterns A to E input to input terminals A to E based on instructions from the state generation circuit 203, and selects one from the mask patterns A to E input to the input terminals A to E,
Transfer to 2.

Next, data processing in each circuit will be explained using FIGS. 4 to 7. In this example, the first image data read with a transfer data length of 16 bits is transferred to VRAMI 1 0
This is a process in which 19 bits are written consecutively starting from the 7th bit of a desired address.

4A to 4C are conceptual diagrams of rotation processing of the first image data 170 in the rotation circuit 122. The leading bit number information (DBA) of the shift bit storage unit 132 is “7”, and the image data 302 is r01.
10010001011101" binary data is stored.

The rotation circuit 122 performs 7-bit clockwise rotation, and as a result, in the image data 303, the lower 9 bits and the upper 7 bits (lower bits from the left end of the data, upper bits from the right end) are exchanged.rl0111
The binary data is 01011001000J.

FIGS. 5(a) to 5(g) show the image data shift circuit section 12.
FIG. 2 is a conceptual diagram illustrating the synthesis of zero data.

Data rabcdJ is stored in the image data 402. Here, raJ and "c" represent 9-bit data, r
bJ and rdJ indicate 7-bit data. Therefore, the image data 402 has a total length of 32 bits. Since the data length of one transfer to the image data shift circuit section 120 is 16 bits, this image data 40
2 is transferred to the rotation circuit 122 in two parts.

Since "7" is stored in the leading bit number information (DBA), these image data 402 are subjected to 7-bit clockwise rotation and become data jbadcJ shown in image data 403. This data is the first latch circuit 1
23, the signal is transferred to the second latch circuit 124 at the timing of the first clock signal. The second latch circuit 124 at this time
, the data stored in the first latch circuit 123 one clock ago is transferred, and the image data of the rotation circuit 122 is transferred to the first latch circuit 123. In order to prevent data storage malfunctions in these latch circuits, a delay element 133 is used to delay the first latch circuit 123.
The timing of transfer to is delayed by about 2 ns. In this way, the first latch circuit 123 and the second latch circuit 124
The image data stored in is then synthesized by a selector circuit 125. Image data 404 is stored in the selector circuit 125.
, 405 is inputted from the bit control circuit 131, and the data indicated by diagonal lines among the image data 404 and 405 is selected to create image data 407. . This image data 4
07 is transferred to the image data synthesis circuit section 140.

FIGS. 6(a) to 6(g) are conceptual diagrams showing the generation of bit mask signals in the mask generation circuit 152. The bit mask signal is composed of a pattern string in which several mask patterns are arranged.

Mask pattern A502 is a mask pattern at the end of the pattern row. “1” is in the lower 10 bits, and the upper 6 bits are “1”
The bits are filled with "0", and if this mask pattern A502 is used, it is possible to combine the first image data 175 into the lower 10 bits and the second image data 176 into the upper 6 bits. This mask pattern A5
02 is formed by the arithmetic circuit 153 as follows. The arithmetic circuit 153 includes the leading bit number information (DBA) and the transfer bit length (BLEN) stored in the shift bit storage unit 132.
) is given. In this example, the leading bit number information (DBA
) is "7" and the transfer bit length (BLEN) is "19", so the arithmetic circuit 153 receives a command from the CPU 160 and starts from a position shifted by 7 bits from the beginning based on this information.
The first image data with a length of 9 bits is transferred to VRAMI 1 0
Form a mask pattern that can be stored in

Next, a mask pattern 8503 is a mask pattern at the beginning of the pattern sequence. The lower 7 bits are filled with "0" and the upper 9 bits are filled with "1". If this mask pattern 8503 is used, the lower 7 bits are filled with the second image data 176, and the upper 9 bits are filled with the first image data 175. It can be incorporated and synthesized.

Mask pattern C504 is a mask pattern used for image data with a data length of 16 bits or less, and one mask pattern constitutes a bit mask signal. In this case, since the leading portion and the trailing portion are provided before and after the mask pattern, mask pattern A502 and mask pattern B5
03 is logically ANDed for each bit. therefore,
Three bits from the seventh bit are set to "1", and the other bits are set to "0".

Mask pattern D505 is a mask pattern for selecting only the first image data, and is connected to a +5V power supply terminal, and all bits are filled with "1".

Mask pattern E506 is a mask pattern for selecting only the second image data, and is connected to GND and all bits are filled with "0".

According to instructions from the state generation circuit 203, mask pattern B503, mask pattern A502, and mask pattern E506 are selected in order from among these mask patterns.
A bitmask signal 507 is generated.

FIGS. 7(a) to 7(e) are conceptual diagrams showing data synthesis in the synthesis circuit 142. FIG. Image data synthesis circuit section 140
The first image data 602 transferred to the third latch circuit 143 and the second image data 603 stored in the third latch circuit 143 are synthesized at the timing of the second clock signal 606. The synthesis process uses the bit mask signal 60 generated by the mask generation circuit 152.
4, on a bit-by-bit basis. Specifically, the second image data 603 is selected when the bit of the bit mask signal 604 is "0", and the first image data 602 is selected when the bit of the bit mask signal is "1". As a result, the first 7 bits and the last 22 bits of the first image data 602 are replaced with the second image data 603, and the first image data 605 is generated.

Next, FIG. 8 shows an example of the data flow of this embodiment using different image data. In this example, the transfer data length is 1
6 bits, data of 39 bits from the second bit of the first image data read from the memory is transferred to the VRAMIIO.
The data is written continuously starting from the fifth bit of the desired address.

Since 39-bit image data is written 16 bits at a time, three write operations are required to write all the data.

First, when the first image data 701 read from the memory passes through the rotation circuit 122, the bit control circuit 1
31 instruction causes 3-bit rotation. Here, the 3 bits are from bit 5, which is the position to be written to VRAMI 1 0, to bit 2, which is the beginning of the first image data.
This is because the number of rotations minus the bits is required. The first image data 702 after rotation is stored in the first latch circuit 123 and the second latch circuit 124, respectively. Note that since the image data stored the first time in the second latch circuit 124 is undefined, it is marked with "x". The lower 3 of the control signal 704 generated by the bit control circuit 131
The bit is set to “1” and the second control signal 704 is applied to the selector circuit 125. This selector circuit 1
25, the first latch circuit 123 and the second latch circuit 1
The first image data 7 ('l
2 and the first image data 703 are combined.

This synthesized first image data 705 is continuously supplied to the synthesis circuit 142. Further, the second image data 706 stored in the third latch circuit 143 is supplied to the synthesis circuit 142 . These image data are sent to the mask generation circuit 152.
A necessary portion is replaced by a bit mask signal 707 given by The pattern of the bit mask signal 707 changes every time, the state to be masked is determined by the state generation circuit 203, and the bit mask signal 707 is sent to the selector circuits 204 to 20.
8 mask patterns ASD and B are selected in sequence. The first image data 708 replaced by the synthesis circuit 142 is
Data is written continuously from the fifth bit of an arbitrary address in the VRAM 110.

As an application example of this embodiment, FIG. 9 shows a block diagram of an image data shift circuit section 801 in which inverting circuits are inserted before and after the image data shift circuit section. The feature of this application example is that by inserting the first inversion circuit 802 and the second inversion circuit 803 to invert the image data, it is possible to not only write sequentially in the forward direction from the lower address to the higher address, but also to Continuous writing in the opposite direction from high to low is also possible. In this case, it is necessary to previously set in which direction the data should be transferred using the DIR signal 804.

Further, as another application example of this embodiment, FIG. 10 shows a circuit diagram of a mask generation circuit 152 that can generate various bit mask signals. The feature of this application example is that an arbitrary mask pattern is set in register D901 in advance, and this mask pattern and selector circuits 902 to 9
The logic elements 905 to 907 perform a logical sum with the output of 04, and use this data as a bit mask signal. In other words, the selector circuit 90 uses a separately set mask pattern.
It becomes possible to mask the data output from 2 to 904. Furthermore, the number of input terminals of the selector circuits 902 to 904 was increased to enable manual input from many registers. For example, as shown in the manual portion of the selector circuit 902, it is possible to generate a wide variety of bit mask signals by directly inputting mask patterns, inputting logical products, and inputting logical sums.

〔Effect of the invention〕

As explained above, according to the image processing device of the present invention,
Bit shift processing and bit mask processing are performed in each circuit away from the control of the CPU.

This control distribution reduces the load on the CPU. Therefore, processing speed can be increased.

In addition, by inserting inverting circuits before and after the image data shift circuit, it is possible to not only write sequentially in the forward direction from the lower address to the higher address, but also to write continuously in the reverse direction from the higher address to the lower address. Writing becomes possible.

Furthermore, by using a mask generation circuit that selects a desired mask pattern from among a plurality of mask patterns, it is possible to generate a wide variety of bit mask signals.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an image processing device showing an embodiment of the present invention, Fig. 2 is a conceptual diagram showing an overview of this embodiment, Fig. 3 is a circuit diagram of a mask generation circuit, and Fig. 4 is a rotation circuit. FIG. 5 is a conceptual diagram showing data synthesis in the image data shift circuit, FIG. 6 is a conceptual diagram showing bit mask signal generation in the mask generation circuit,
Figure 7 is a conceptual diagram showing the synthesis of data in the synthesis circuit;
Figure 9 is a conceptual diagram showing the data flow of this embodiment, Figure 9 is a block diagram showing an application example of this embodiment, Figure 10 is a circuit diagram showing an application example of this embodiment, and Figure 11 is a conventional example. FIG. 2 is a conceptual diagram showing the flow of processing. 100... Image data memory device, 110... VR
A.M. 120... Image data shift circuit section, 121.
...Bit shift section, 122... Rotation circuit, 123... First latch circuit, 124... Second latch circuit, 125... Selector circuit, 131... Bit control circuit, 132... Shift bit storage section, 133
...Delay element, 140... Image data synthesis circuit section,
141... Data synthesis section, 142... Synthesis circuit, 1
43...Third latch circuit, 151...Mask generation section, 152-Mask generation circuit, 153... Arithmetic circuit, 1
60...CPU, 171-175...First image data, 176, 177...Second image data, 178...
- First image data, 180, 181...clock terminal.

Claims (1)

[Scope of Claims] 1. In an image processing device that replaces first image data stored in a first storage device with second image data stored in a second storage device, in order to replace the second image data with the second image data, the an image data shift circuit that shifts the first image data horizontally bit by bit; and a second image that reads the first image data transferred from the image data shift circuit from the second storage device. replacing the data with the second
an image data synthesis circuit unit that stores the second image data in the area of the storage device where the second image data was stored; and an image data shift circuit unit that reads out the first image data stored in the first storage device; An image processing device comprising: a control device that issues a command to process data in a data synthesis circuit section and store it in the second storage device. 2. The image data shift circuit section shifts the first image data read out from the first storage device in units of transfer data length by the necessary number of bits toward the end, and then removes the protruding portion caused by the shift. a bit shift unit that replaces a portion of data lost due to shifting of the first image data to be read; a bit control circuit that controls bit shift processing of the bit shift circuit unit; the bit control circuit unit and the image data synthesis circuit unit; 2. The image processing apparatus according to claim 1, further comprising a shift bit storage section storing information on the number of shift bits to be transferred. 3. The image data synthesis circuit section reads second image data from the second storage device in transfer data length units;
Unnecessary data that may occur before and after the first image data transferred from the image data shift circuit section is replaced with a corresponding portion of this second image data, and the first image data after this replacement is stored in the second memory. 3. The image according to claim 2, further comprising: a data synthesis section that writes into the area where the second image data of the device was stored; and a mask generation section that generates a mask pattern and transfers it to the data circuit section. Processing equipment. 4. In order to invert the upper bits and lower bits of the first image data read in units of transfer data length and process them in the image data shift circuit, a pair is provided at the input and output parts of the image data shift circuit. 3. The image processing apparatus according to claim 2, further comprising a transfer data direction inversion circuit. 5. The mask generation unit selects a desired mask pattern from among a plurality of mask patterns, and uses a logical sum of this mask pattern and another mask pattern as a bit mask pattern to be used in data synthesis processing. The image processing apparatus according to claim 3.