JPH0321918B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer display synchronization signal generation device that is applied when output data from a microcomputer is displayed on a color CRT display.

Generally, when data is displayed on a CRT display, the data is converted into a dot display type video signal by a video RAM and a CRT display circuit. Dot clock frequency fdot at this time
Conventionally, this has been determined depending on whether dots are displayed on one line on one screen. Therefore, strictly speaking, the horizontal frequency of the converted video signal was slightly different from that of the standard television system. In the case of monochrome images, this shift is corrected by the receiver's AFC operation, so there is no problem. However, when generating three primary color data from a microcomputer, converting it into a standard color television signal such as the NTSC system, and displaying it on a color CRT display, the color subcarrier frequency fsc and the dot clock frequency are Due to the relationship with fdot, problems such as color shifts and uneven colors occur in the display dots, and these color shifts flow on the screen.

Therefore, the applicant can divide the output of the reference oscillator to obtain the color subcarrier frequency fsc and the dot clock frequency fdot, and furthermore,
We have previously proposed a display synchronization signal generating device that is improved so that color shifts and color unevenness do not occur in each display dot. This has the feature of selecting the value of each frequency as described below.

When the color subcarrier frequency is fsc, the horizontal scanning frequency is fH, and the dot clock frequency of display dots is fdot, fdot=n/mfsc fdot=fH, where, m and n satisfy the relationship of integers, and the above fdot In order to prevent frequency values that are integer multiples of from falling into the above fsc neighborhood range,
Select fdot.

The above frequency relationship will be explained in more detail. First, the frequency (highest frequency) of the output of the reference oscillator is set to n times the color subcarrier frequency fsc (n=1,
2, 3, ...), divide this frequency to generate fsc, and divide it by m (m = 1, 2, 3, ...).
) to obtain the dot clock frequency fdot, it is necessary to satisfy the relational expression fdot=n/mfsc...

Each dot must be arranged vertically on the screen, and one dot on the screen and the dot immediately above (or below) it are one horizontal scanning period (1H period).
Since it is displayed with a timing difference of, fdot=fH... However, the relational expression of =1, 2, 3,... can be obtained. Furthermore, the above fdot is
When in the vicinity of fsc, for example within the range of fsc±Δfsc, mutual interference occurs between these fdots and fsc, causing problems such as coloring of white dots. Furthermore, for example, when displaying (lighting up) and non-displaying (lighting out) in a 2-dot period, it is necessary that 1/2 fdot does not fall within the range of fsc±△fsc, and the 3-dot period In the display, 1/3fdot becomes..., and generally it is necessary to prevent 1/kfdot (k=1, 2, 3,...) from falling within the range of fsc±Δ. Here, in the standard color television signal of the NTSO system, the above fsc is approximately 3.58MHz, and the above △fsc is, for example,
It should be about 0.5MHz. From this point of view, the specific number of frequency bands that can be used is 4.08.
~6.16 (MHz), 8.16 ~ 9.24 (MHz), 12.24 ~ 12.32
There are three bands (MHz).

Also, if the number of dots in the horizontal direction of one displayed pixel is d, then the number of dots on one line is d.
The value divided by is the number of characters displayed on one line, so
If the character clock frequency is fe, then dfc=fdot... Also, if the number of characters displayed on one line is c, then fc=cfH... However, c, d, = 1, 2, 3, etc.

Specific numerical examples of each frequency in the NTSC system will be explained under the conditions of these formulas.

First, the above fsc and fH have the following relationship: fsc=455/2fH =5・7・13/2fH... Using this equation and the above equation, fdot=5・7・13・The formula n/2·mfH... is obtained. In order for the relational term of fH in this equation to be an integer, n must be an even number and m must be 5, 7,
13, or a factor of n/2. Furthermore, by substituting this equation into the above equation, it is necessary to satisfy the following equation: fc=5.7.13.n/2.d.mfH...

If each of the above conditions is satisfied, the number of horizontal dots d in one character is 6, and 80 characters are to be displayed on one line, specifically (m = 7) (n = 24),
The circuit configuration shown in FIG. 1 is used. In FIG. 1, 1 indicates a reference oscillator, and this reference oscillator 1
Frequency dividers 8 and 9 are connected to. The oscillation frequency of the reference oscillator 1 is 85.91MHz. m=
7, the frequency is divided into 1/7 by the frequency divider 8, and a dot clock signal of fdot (=12.27MHz) is taken out to the output terminal 2. Also,
The output of the frequency divider 8 is divided into 1/6 by the frequency divider 10, and a character signal of fc (2.05 MHz) is taken out to the output terminal 3. Furthermore, since n=24, a signal of the color subcarrier frequency fsc is obtained at the output terminal 4 by the frequency divider 9 of 1/12 and the frequency divider 11 of 1/2, and the signal of the color subcarrier frequency fsc is obtained from the frequency divider 12. By dividing the output of the frequency divider 9 to 1/455 by , a signal at the horizontal scanning frequency fH is obtained at the output terminal 5. By supplying each signal obtained at these output terminals 2, 3, 4, and 5, the three primary color signal data, and 2fH, fV (vertical scanning frequency) signals (not shown) to an NTSC encoder, A color television signal can be formed.

However, in the configuration shown in FIG. 1, since the oscillation frequency of the reference oscillator 1 is as high as 85.91MHz,
Problems were recognized in that the configurations of frequency dividers 8, 9, 10, 11, and 12 became complicated and unnecessary radiation occurred.

The present invention has a frequency that satisfies each of the above-mentioned conditions, and also allows the use of a lower frequency as the oscillation frequency of the reference oscillator 1.

Here, the dot clock frequency fdot and the character clock frequency fc in the configuration shown in FIG. 1 described above are as shown in FIG. 2A, fdot (=
12.27 mHz) itself and a 1/6 frequency divider 10. Also, fsc, fH, 2fH
Each frequency (equalized pulse frequency) is obtained by dividing the 4fsc frequency by 1/4 by the frequency divider 13 and by 1/455 by the frequency divider 12, as shown in FIG. 2B. The output of the frequency divider 12 is further divided by the frequency divider 14. This allows the maximum frequency to be lowered to 4fsc. However, it is meaningless unless 12.27MHz and 14.32MHz are synchronized.

In consideration of the above points, the present invention uses a reference oscillator with a frequency of 4 fsc, and generates a dot clock signal for a computer that is synchronized with the output of this reference oscillator and satisfies a predetermined frequency condition.
It is formed using a PLL circuit.

Hereinafter, this invention will be described as (d
An embodiment applied to the case where 80 characters are displayed on one line with the ratio 6) will be described with reference to FIG.

In FIG. 3, 15 indicates a reference oscillator with an oscillation frequency of 4fsc, and for the output of this reference oscillator 15, a frequency divider 13 of 1/4, a frequency divider 12 of 1/455, and a frequency divider 1/7 A frequency divider 16 is connected, and the above-mentioned 4fsc output is made into a frequency of (4fsc/7) by the frequency divider 16. Further, a 1/2 frequency divider 14 and a 1/525 frequency divider 17 are connected to the frequency divider 12.

The fsc signal obtained from the frequency divider 13 is taken out to the output terminal 4, the 2fH signal from the frequency divider 12 is taken out to the output terminal 6, and the 2fH signal from the frequency divider 17 is taken out to the output terminal 6.
A signal of fV is taken out to the output terminal 7.

In addition, 18 indicates a VCO (voltage controlled oscillator), whose center frequency is fdot (=((4fsc/7)×6))
It is said that The VCO 18 includes a phase comparator circuit 19,
Configures a PLL circuit together with a low-pass filter 20,
After the output of the VCO 18 is set to a frequency of (4fsc/7) by the 1/6 frequency divider 10, the phase comparison circuit 19
The signal is supplied to the frequency divider 16 and its phase is compared with the output of the frequency divider 16. Therefore, fdot obtained at the output of VCO18
Both the dot clock signal obtained at the output of the frequency divider 10 and the character clock signal obtained at the output of the frequency divider 10 are synchronized with the output of the reference oscillator 15.

In addition, as shown by the broken line in FIG. 3, by resetting the frequency divider 16 with the signal from the frequency divider 14, the horizontal synchronization signal and the character clock signal are synchronized, and the character display after the power is turned on. The position of the beginning of may be made constant.

As understood from the description of one embodiment above,
According to this invention, the oscillation frequency of the reference oscillator is
It is possible to display data in a dot pattern on a color CRT display without creating problems such as complicating the frequency divider configuration or generating unnecessary radiation.

Note that, unlike the above embodiment, when the number of dots in the horizontal direction of one pixel is 6 and 40 characters are displayed on one line, fdot=4fsc×3/7. Also, when displaying 40 characters with 8 dots, fdot = 4fsc x 4/7 Similarly, when displaying 80 characters with 8 dots, the frequency relationship is fdot = 4fsc x 8/7. . Even in these cases, the highest frequency used is
Since 4fsc is enough, the same effect as described above can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the display synchronization signal generator proposed earlier, FIG. 2 is a block diagram used to explain the present invention, and FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention. be. 1, 15...Reference oscillator, 2, 3, 4, 5,
6, 7...Output terminal, 18...VCO, 19...
Phase comparison circuit.

Claims (1)

[Scope of Claims] 1. In a computer display synchronization signal generator for converting dot display data into a standard color television signal and displaying it on a color CRT display, a reference oscillator having a frequency four times the color subcarrier frequency. A dot clock signal for the computer is generated in synchronization with the output of this reference oscillator by a PLL circuit, and the color subcarrier frequency is fsc, the horizontal operation frequency is fH, and the dot clock frequency of display dots is fdot. When. fdot=455/2・n/m・fH (where n is an even number, m is 5, 7, 13, or n/2
A computer display synchronization signal generator, characterized in that it satisfies the following conditions: fsc-0.5MHz<1/Kfdot<fsc+0.5MHz (where K is an integer of 1 or more).