JPH03219745A - Polarity discrimination circuit - Google Patents

Abstract

PURPOSE:To discriminate the polarity with simple constitution by sending a predetermined synchronizing word and an inverted synchronizing word while being included in a form of multiframe and detecting both the synchronization words from a received digital signal. CONSTITUTION:A synchronization word F1 decided in advance is included in a 1st frame of each multiframe of a time division multiplex digital signal and a synchronization word F being the inversion of the word F1 is included to other frame. When a communication section 11 receives the digital signal, word detection circuits 21, 22 of a polarity discrimination circuit 10 detect the words F1, F respectively synchronously with the clock signal. Every time the words are detected, a count circuit 23 counts the words and when number exceeds a prescribed number, discrimination result signals 16, 17 are outputted from the circuit 23. Thus, the polarity is discriminated with simple constitution and the received digital signal or its inverted signal is decoded via a decoder 33.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section. Regarding.

[Prior Art] The digital transmission network is typically an I5DN (Integrated Services Digital Network), and the transmission line is typically a two-wire metallic cable. The transmitter transmits the time division multiplexed digital signal to the transmission path.

The time division multiplexed digital signal may be a multilevel code signal.

In the time division multiplexed digital signal, each multiframe is
2nd, ..., and Nth (N is the first integer greater than or equal to 3)
Contains consecutive multi-frames including frames. The first frame of each multiframe includes a multiframe synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multiframe synchronization signal.

The first predetermined synchronization word consists of at least one symbol.

Each of the second to Nth frames of each multiframe is
A frame synchronization signal representing a second predetermined synchronization word and a transmit data signal following the frame synchronization signal are included. In I5DN, the second predetermined synchronization word is generally determined by inverting the first predetermined synchronization word.

The receiving unit receives the time division multiplexed digital signal from the transmission path as a received digital signal. The received digital signal has true polarity, which is equal to the polarity of the time division multiplexed digital signal, when the transmission line consisting of a two-wire metallic cable is connected in the correct polarity, that is, normally, between the transmitter and the receiver. have. When the transmission line is connected between the transmitting section and the receiving section in the wrong polarity, ie, in reverse, the received digital signal has a polarity that is inverted with respect to the true polarity.

[Problem to be Solved by the Invention] In order to correctly decode the transmitted data signal in the receiving section, regardless of whether the transmission line is connected between the transmitting section and the receiving section in the correct or incorrect polarity, A polarity determining circuit is required for the receiving section to determine whether the received digital signal has true polarity or inverted polarity.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a polarity determining circuit for use in a receiving section of a digital transmission network, which determines whether a received digital signal has a true polarity or an inverted polarity.

Another object of the present invention is to provide a polarity determination circuit that can determine whether a received digital signal has true polarity or inverted polarity using a frame synchronization signal.

Yet another object of the present invention is to provide a polarity determination circuit with a simple structure.

[Means for Solving the Problems] According to the present invention, there is provided a polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section. , the transmitter transmits a time-division multiplexed digital signal including consecutive multi-frames, each multi-frame including a first, second, ..., and N-th frame (N is a first integer of 3 or more). , the first frame of each multiframe includes a multiframe synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multiframe synchronization signal, Each of the second to Nth frames of the multiframe includes a frame synchronization signal representing a second predetermined synchronization word and a transmit data signal following the frame synchronization signal, The predetermined synchronization word is determined by inverting the first predetermined synchronization word, and the receiving section receives the time division multiplexed digital signal from the transmission path as a received digital signal, and the received digital signal is When the transmission path is connected between the transmitting section and the receiving section in the correct polarity, it has a true polarity equal to the polarity of the time division multiplexed digital signal, and the received digital signal is connected between the transmitting section and the receiving section. When the polarity is incorrectly connected to the digital signal, the polarity is reversed to the true polarity, and the polarity determining circuit determines whether the received digital signal has the true polarity or the reversed polarity, The polarity determination circuit thereby determines, respectively, that the received digital signal has a true polarity and that the received digital signal has an inverted polarity for the first and second determination result signals. When it is determined that
The first and second determination result signals are
A first predetermined polarity determining circuit receives the received digital signal and determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. a first synchronization word detection means for detecting a synchronization word and outputting a first detection pulse each time a first predetermined synchronization word is detected; a second synchronization word detection means for detecting a synchronization word and outputting a second detection pulse every time a second predetermined synchronization word is detected; connected to the first and second synchronization word detection means; , an initial value, and a value M preselected from the initial value.
(M is a second integer greater than or equal to 2) and a lower threshold that is lower than the initial value by the preselected value M, and in response to the first and second detection pulses. , respectively down and up the counts, said first and said second
A polarity determination circuit is obtained, comprising: a counting means for outputting a determination result signal when the count increases to an upper threshold value and when the count decreases to a lower threshold value, respectively.

The counting means increases and decreases the count, respectively, in response to the first and second detection pulses, and outputs the first and second determination result signals when the count decreases to a lower threshold and The output may be output when the count increases to an upper threshold value.

Further, in the above-mentioned polarity determination circuit according to the present invention, each of the frame synchronization signals of at least two frames of the second to Nth frames of each multiframe is a first predetermined signal represented by the multiframe synchronization signal. It is also applicable to the case where the second predetermined synchronization word is determined by inverting the same synchronization word.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

The polarity determination circuit 10 according to the first embodiment of the present invention shown in FIG. 1 is used in the first communication section 11 of the digital transmission network shown in FIG.

Referring to FIG. 2, it is assumed that the first communication section 11 is currently operating as a receiving section. The digital transmission network is typically ISDN and includes a second communication section 12 and a transmission path 13 between the first and second communication sections 11 and 12. Assuming that the second communication section 12 is currently operating as a transmitter, the second communication section 12 also has a similar polarity determination circuit that operates when the second communication section 12 acts as a receiver. Contains. Transmission line 12 is typically a two-wire metallic cable. The second communication unit 12 transmits the time division multiplexed digital signal to the transmission line 13.

Referring to FIG. 3, the time division multiplexed digital signal is SIG
and is shown on the top line.

A time division multiplexed digital signal includes consecutive multi-frames with a common multi-frame period. Each multiframe includes first, second, . . . , and Nth (N is a first integer greater than or equal to 3) frames having a common frame period. The first frame of each multiframe period includes a multiframe synchronization signal and a transmit data signal following the multiframe synchronization signal. The multi-frame synchronization signal and transmission data signal are Fl and DAT, respectively.
It is displayed as A. The multi-frame synchronization signal represents a first predetermined synchronization word consisting of at least one symbol.

Each of the second to Nth frames of each multiframe is
It includes a frame synchronization signal labeled F and a transmit data signal labeled DATA following the frame synchronization signal F. The frame synchronization signal represents a second predetermined synchronization word. Here, it is assumed that the second predetermined synchronization word is determined by inverting the first predetermined synchronization word.

Returning to FIG. 1, the first communication unit 11 receives the time division multiplexed digital signal from the transmission path 13 as a received digital signal. This received digital signal is transmitted through the transmission line 13 of the two-wire metallic cable to the first and second communication sections 11 and 12 (
When connected correctly, ie, normally, in polarity between FIG. 2), it has a true polarity equal to the polarity of the time division multiplexed digital signal. If the polarity of the transmission line 13 is incorrect between the first and second communication units 11 and 12 (FIG. 2),
That is, conversely, when connected, the received digital signal is
It has a polarity opposite to that of the tool.

The polarity determination circuit 10 is for determining whether a received digital signal has a true polarity or an inverted polarity. The polarity determination circuit 10 thereby receives the first and second determination result signals 16 and 17, respectively, to determine that the received digital signal has a true polarity and that the received digital signal has been inverted. This is what is output when it is determined that it has polarity. 1st and 2nd
The determination result signals 16 and 17 respectively indicate that the received digital signal has a true polarity and that the received digital signal has an inverted polarity.

The polarity determination circuit 10 includes first and second synchronization word detection means 21 and 22. First synchronization word detection means 21
receives the received digital signal and outputs the clock signal CLOCK.
detecting a first predetermined synchronization word in synchronization with;
A first detection pulse FIP is output every time a first predetermined synchronization word is detected. The second synchronization word detection means 22 receives the received digital signal and receives the clock signal CL.
A second predetermined synchronization word is detected in synchronization with OCK, and a second detection pulse FP is output every time the second predetermined synchronization word is detected.

The first and second detection pulses FIP and FP are shown in the second and third lines of FIG. 3, respectively, and the clock signal CLOCK is shown in the bottom line of FIG.

Continuing to refer to FIG. 1, the count circuit 23 includes a first
and an up/down counter 24 having countdown and countup terminals DOWN and UP connected to the second synchronization word detection means 21 and the second synchronization word detection means 22, respectively. up/down counter 24
has, for example, an initial value of 0 and an enable terminal ENABLE. Enable terminal ENABLE is logic “0”
'' level control signal 25, the up/down counter 24 changes the count to the clock signal CLOCK in response to the first and second detection pulses FIP and FP.
, respectively, and outputs the count as a count value. Enable terminal ENA
When the BLE receives the control signal 25 at the logic "1" level, the up/down counter 24 stops such counting operation and holds the count as it is.

The up/down counter 24 further includes an output terminal Q and positive and negative polarity terminals QHp and QHn. The up/down counter 24 outputs the absolute value of the count value to the output terminal Q. The up/down counter 24 outputs logic "1 level" signals to the positive and negative polarity terminals QHp and QHn, respectively, when the count value has positive and negative polarities.

As will become clear as the explanation progresses, the combination of the match gate 26 and the AND gate 27 is the combination of the up/down>counter 2
Determine the upper threshold for 4.

The upper threshold is a preselected value M (M is 2
higher than or equal to the second integer). The combination of match gate 26 and AND gate 28 determines the lower threshold for up/down counter 24, as will also become clear as the description proceeds. The lower threshold value is lower than the initial value by the preselected value M.

The coincidence gate 26 is connected to the output terminal Q and receives the absolute value of the count value and a preselected value M, and when this absolute value becomes equal to the preselected value M, it outputs a -1'' level signal. When this absolute value is not equal to a preselected value M, a logic "0" level signal is output.

AND gate 27 includes coincidence gate 26 and positive polarity terminal Q.
Hp, and outputs a logic "1" level signal as the first determination result signal 16 only when the AND gate 27 receives a logic "1" level signal from the coincidence gate 26 and the positive polarity terminal QHp. AND gate 28 is connected to coincidence gate 26 and negative polarity terminal QHn, and AND gate 28 is connected to coincidence gate 26 and negative polarity terminal QHn.
8 is a logic “1” from the coincidence gate 26 and the negative polarity terminal QHn.
Only when receiving a “level signal,” a logic “1” level signal is output as the second determination result signal 17.

In this way, the count circuit 23 is connected to the first and second synchronization word detection circuits 21 and 22, has an initial value, upper and lower threshold values, and has a first and second detection pulse F.
In response to IP and FP, the counts are down and up, respectively, and the first and second determination result signals 16 and 17 are output.
are output when the count increases to a lower threshold and when the count decreases to a lower threshold, respectively.

When the second integer M is equal to 8, the counting circuit 23
Works as shown. In this case, the initial values, upper and lower thresholds are 0, +8° and -8, respectively.

In FIG. 1, the count up and count down UP and DOWN of the up/down counter 24 may be connected to the first and second synchronization word detection circuits 21 and 22, respectively. In this case, the count circuit 23 increases and decreases the count in response to the first and second detection pulses FIP and FP, respectively, and outputs the first and second determination result signals 16 and 17 as the count decreases. When the count decreases to the upper threshold and when the count increases to the upper threshold, the count is output.

Continuing to refer to FIG. 1, count stop circuit 29 includes an OR gate 30 and a flip-flop 31. When the OR gate 30 receives one of the first and second judgment result signals 16 and 17 from the count circuit 23, it supplies the - one of the first and second judgment result signals 16 and 17 to the flip-flop 31, and outputs the first and second judgment result signals 16 and 17 to the flip-flop 31. Logic “1” in step 31
A level control signal 25 is output. As a result, the count circuit 23 receives the first and second determination result signals 16 and 17.
The above-mentioned - one will continue to be output continuously thereafter.

In this way, the count stop circuit 29
are connected to the first and second determination result signals 16 and 17.
In response to one of
7 to the first and second determination result signals 16 and 1.
Even after receiving the above-mentioned -1 of 7, the output is continued.

The first communication unit 11 further includes a synchronization confirmation detection circuit 32 connected to the first and second synchronization word detection circuits 21 and 22. The synchronization confirmation detection circuit 32 responds to the first and second detection pulses FIP and FP and outputs the clock signal CLOC.
K is received, synchronization confirmation is detected, and synchronization confirmation signal 5YNC is generated.
Output.

When the decoder 33 receives the first determination result signal 16 from the count circuit 23, it decodes the received digital signal into a decoded signal in synchronization with the clock signal CLOCK. When receiving the second judgment result signal 16 from the count circuit 23, the decoder 33 inverts the received digital signal as an inverted signal, synchronizes this inverted signal with the tarlock signal CLOCK, and converts it into a decoded signal. to decode.

Referring again to FIG. 3, the polarity determination circuit 1 shown in FIG.
0 is determined by each of the at least two frame synchronization signals F of the second to Nth frames of each multiframe inverting the first predetermined synchronization word represented by the multiframe synchronization signal F1. second
It is also applicable to the case where the synchronization word represents a predetermined synchronization word.

Referring to FIG. 5, a polarity determination circuit 40 according to a second embodiment of the present invention includes similar parts designated by the same reference numerals. This polarity determination circuit 40 is also used in the first communication unit 11 that receives different time division multiplexed digital signals from the transmission line 13 as received digital signals.

Returning to FIG. 2 again, this different time division multiplexed digital signal will be explained. For this different time division multiplexed digital signal, the first integer N is greater than or equal to 6. In these different time division multiplexed digital signals, each of the at least two frame synchronization signals F of the second to Nth frames of each multiframe is synchronized with the first predetermined synchronization signal F1 represented by the multiframe synchronization signal F1. represents a second predetermined synchronization word determined by inverting the word. 2nd to Nth of each multiframe
The frame synchronization signal F of at least one frame synchronization signal F of the second to Nth frames excluding the at least two of the frames of represents the word. Each of the frame synchronization signals F of at least two remaining frames of the second to Nth frames of each multiframe is
represents a fourth predetermined sync word determined by inverting the predetermined sync word of .

Returning to FIG. 5, the polarity determination circuit 40, similar to the polarity circuit 10 of FIG.
1 and 22. The polarity determination circuit 40 further includes:
It includes third and fourth synchronization word detection circuits 43 and 44. The third synchronization word detection circuit 43 receives the received digital signal, detects a third predetermined synchronization word, and outputs a third detection pulse every time it detects the third predetermined synchronization word. do. Similarly, the fourth synchronization word detection circuit 44 receives the received digital signal, detects a fourth predetermined synchronization word, and detects the fourth synchronization word every time it detects the fourth predetermined synchronization word. Outputs pulses.

The first count circuit 45 is connected to the first and second synchronization word detection circuits 21 and 22, and has a first initial value, a first upper threshold, and a first lower threshold. There is. 1st
The upper threshold of M is a preselected value M than the first initial value.
(M is a second integer greater than or equal to 2). The first lower threshold is lower than the first initial value by the preselected value M. The first count circuit 45 decreases and increases the first count, respectively, in response to the first and second detection pulses, and outputs first and second output signals such that the first count is the first count. When the first count increases to an upper threshold value and when the first count decreases to a first lower threshold value, the first count is output. Each of the first and second output signals has a logic "1" level.

The first count stop circuit 46 is the first count stop circuit 46.
5, and in response to one of the first and second output signals, stops the first counting circuit 45 and causes the first counting circuit 45 to output the first and second output signals. one of the first and second output signals;
Output continuously.

The second count circuit 47 is connected to the third and fourth synchronization word detection circuits 43 and 44, and has a second initial value, a second upper threshold, and a second lower threshold. There is. Second
The upper threshold value of is higher than the second initial value by the preselected value M. The second lower threshold value is lower than the second initial value by the preselected value M. The second count circuit 47 decreases and increases the second count, respectively, in response to the third and fourth detection pulses, and
output signals when the second count increases to a second upper threshold and when the second count decreases to a second lower threshold, respectively. Each of the third and fourth output signals has a logic "1" level.

The second count stop circuit 48 is the second count stop circuit 48.
7, and in response to one of the third and fourth output signals, stops the second counting circuit 47 and causes the second counting circuit 47 to receive the third and fourth output signals. one of the third and fourth output signals;
Output continuously.

Each of the first and second count circuits 45 and 47 is the same in structure as the count circuit 23 shown in FIG. Each of the first and second count stop circuits 46 and 48 is the same in structure as the count stop circuit 29 shown in FIG.

While receiving the first and third output signals, the first AND gate 49 generates the first determination result signal 16 at the logic '1' level.Similarly, the second AND gate 50
While receiving the second and fourth output signals, a second determination result signal 17 of logic "1 level" is generated.

In this way, the first and second AND gates 49 and 50
The combination of the first and second counting circuits 45 and 47
are connected to the first and second determination result signals 16 and 17.
while receiving the first and third output signals, and *2
While receiving the fourth output signal and the fourth output signal, the circuit functions as a determination result signal generation circuit.

In the illustrated first communication unit 11, the synchronization confirmation detection circuit 32 is connected to the first to fourth synchronization word detection circuits 21.22.
．． 43 and 44. In response to the first to fourth detection pulses, the synchronization confirmation circuit 32 detects synchronization confirmation and outputs a synchronization confirmation signal 5YNC.

When the decoder 33 receives the first determination result signal 16 from the count circuit 23, it decodes the received digital signal into a decoded signal in synchronization with the clock signal CLOCK. When receiving the second determination result signal 16 from the count circuit 23, the decoder 33 inverts the received digital signal as an inverted signal, synchronizes this inverted signal with the clock signal CLOCK, and converts it into a decoded signal. to decode.

Although the invention has been described in terms of several preferred embodiments, it will be readily apparent to those skilled in the art that the invention may be practiced in various other ways. For example, the first
A different counting circuit may be used instead of the counting circuit 45. The different counting circuits are responsive to first and second detection pulses to up and down counts, respectively, and to output first and second output signals when said counts have decreased to a first lower threshold. and when the first count increases to a first upper threshold value, the respective outputs are performed. Additionally, another different counting circuit may be used instead of the second counting circuit 47 shown in FIG. The another different counting circuit is responsive to the third and fourth detection pulses to up and down the count, respectively, and to output the third and fourth output signals so that the count decreases to a first lower threshold. and when the first count increases to the first upper threshold value, respectively. In Figure 5, the polarity determination circuit 40 detects the synchronization word detection circuit when the time-division multiplexed digital signal contains K (K is an integer of 3 or more) pairs of synchronization words with different polarities. vs. vs. vs.
It is also possible to include more than one count circuit.

[Effects of the Invention] As explained above, according to the present invention, there is obtained a polarity detection circuit that is used in a receiving section of a digital transmission network and determines whether a received digital signal has a true polarity or an inverted polarity. be able to. Further, according to the present invention, it is possible to obtain a polarity detection circuit that can determine whether a received digital signal has a true polarity or an inverted polarity using a frame synchronization signal and a multiframe synchronization signal. Furthermore, the polarity detection circuit of the present invention has a simple structure.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first communication unit having a polarity determination circuit according to a first embodiment of the present invention, and FIG. 2 is a block diagram of a digital transmission network including the first communication unit shown in FIG. 3 is a time chart for explaining the operation of the polarity determination circuit of FIG. 1, FIG. 4 is a diagram for explaining the operation of the count circuit of the polarity determination circuit of FIG. 1, and FIG. 5 is a time chart of the present invention. FIG. 7 is a block diagram of a first communication unit including a polarity determination circuit according to a second embodiment. 10 is a polarity determination circuit, 12 is a first and second communication section, 13 is a transmission line, 21 and 22 are first and second synchronization word detection circuits, 23 is a count circuit, 24 is an up/down counter, 25 is the control signal, 26 is the match date, 27
and 28 is an AND gate, 29 is a count stop circuit, 3
0 is an OR gate, 31 is a flip-flop, 32 is a synchronization confirmation detection circuit, 33 is a decoder, 40 is a polarity determination circuit,
43 and 44 are third and fourth synchronization word detection circuits;
5 and 47 are first and second count circuits, 46 and 4
8 is a first and second count ejection circuit, and 49 and 50 are AND gates. Figure 2 Figure 4 Signal valve

Claims (1)

[Claims] 1. A polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, wherein the transmitting section transmitting a time division multiplexed digital signal including consecutive multi-frames whose frames include first, second, ..., and N-th frames (N is a first integer of 3 or more) to a transmission path; The first frame of each multiframe includes a multiframe synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multiframe synchronization signal; Each of the N frames includes a frame synchronization signal representing a second predetermined synchronization word and a transmit data signal following the frame synchronization signal, the second predetermined synchronization word being different from the first one. The receiving section receives the time-division multiplexed digital signal from the transmission path as a received digital signal, and the received digital signal is determined by inverting a predetermined synchronization word of the transmission path. When the transmission line is connected correctly in polarity between the transmitter and the receiver, it has a true polarity equal to the polarity of the time division multiplexed digital signal; The polarity determination circuit determines whether the received digital signal has the true polarity or the inverted polarity, and the polarity determination circuit thereby determines whether the received digital signal has the true polarity or the inverted polarity. , the first and second determination result signals,
The first and second polarity determination circuits output when the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. In the polarity determination circuit, the determination result signals indicate that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. a first synchronization word detection means for detecting one predetermined synchronization word and outputting a first detection pulse every time the first predetermined synchronization word is detected; a second synchronization word detection means for detecting two predetermined synchronization words and outputting a second detection pulse every time the second predetermined synchronization word is detected; an upper threshold that is connected to the word detection means and is higher than the initial value by a preselected value M (M is a second integer greater than or equal to 2); and an upper threshold that is higher than the initial value by the preselected value M. and a low lower threshold, and in response to first and second detection pulses, the count is decreased and increased, respectively, and the first and second determination result signals are set such that the count increases to an upper threshold. 1. A polarity determination circuit comprising: a count means for outputting an output when the count decreases to a lower threshold value and when the count decreases to a lower threshold value. 2. connected to the counting means, in response to one of the first and second determination result signals, stopping the counting means, and transmitting the one of the first and second determination result signals to the counting means;
2. The polarity determination circuit according to claim 1, further comprising count stop means for continuously outputting the one of the first and second determination result signals even after receiving the one. 3. A polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, wherein the transmitting section determines whether each multiframe A time-division multiplexed digital signal containing consecutive multi-frames including 2, . The frames include a multi-frame synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multi-frame synchronization signal, and each of the second to Nth frames of each multi-frame , a frame synchronization signal representative of a second predetermined synchronization word and a transmitted data signal following the frame synchronization signal, the second predetermined synchronization word being representative of the first predetermined synchronization word. The receiving unit receives the time-division multiplexed digital signal from the transmission line as a received digital signal, and the received digital signal is determined by inverting the transmission line between the transmitting unit and the receiving unit in polarity. The received digital signal has a true polarity equal to the polarity of the time-division multiplexed digital signal when the The polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit thereby determines whether the received digital signal has a true polarity or an inverted polarity. The judgment result signal of
When the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, the polarity determination circuit outputs the polarity determination circuit. The second determination result signal indicates that the received digital signal has a true polarity and that the received digital signal has an inverted polarity. , first synchronization word detection means for detecting a first predetermined synchronization word and outputting a first detection pulse every time the first predetermined synchronization word is detected; , second synchronization word detection means for detecting a second predetermined synchronization word and outputting a second detection pulse every time the second predetermined synchronization word is detected; an upper threshold value higher than the initial value by a preselected value M (M is a second integer greater than or equal to 2), and the preselected value higher than the initial value; has a lower threshold value lower by M, and increases and decreases the count in response to first and second detection pulses, respectively, and outputs the first and second determination result signals when the count is lower than the lower threshold value. 1. A polarity determination circuit comprising: a count means that outputs an output when the count decreases to an upper threshold value and when the count increases to an upper threshold value. 4. connected to the counting means, in response to one of the first and second determination result signals, stops the counting means, and transmits the one of the first and second determination result signals to the counting means; Even after receiving the one of the first and second determination result signals,
4. The polarity determination circuit according to claim 3, further comprising count stop means for causing continuous output. 5. A polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, the transmitting section is configured to determine whether each multiframe A time-division multiplexed digital signal containing consecutive multi-frames including 2, . The frames include a multi-frame synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multi-frame synchronization signal, and each of the second to Nth frames of each multi-frame , a frame synchronization signal and a transmission data signal following the frame synchronization signal, and each of the at least two frame synchronization signals of the second to Nth frames of each multiframe has a first predetermined synchronization signal. The receiver receives the time division multiplexed digital signal from the transmission path as a received digital signal, and the received digital signal is transmitted as a received digital signal. When the transmission line is connected correctly in polarity between the transmitter and the receiver, it has a true polarity equal to the polarity of the time division multiplexed digital signal, and the received digital signal When the polarity is incorrectly connected, the polarity is reversed to the true polarity, and the polarity determination circuit determines whether the received digital signal has the true polarity or the reversed polarity. The polarity determination circuit thereby determines, respectively, that the received digital signal has a true polarity and that the received digital signal has an inverted polarity. The first and second determination result signals indicate that the received digital signal has the true polarity and that the received digital signal has the inverted polarity, respectively. The polarity determination circuit receives the received digital signal and detects a first predetermined synchronization word, and each time it detects the first predetermined synchronization word,
a first synchronization word detection means that outputs a detection pulse of the first synchronization word; A second synchronization word detection means outputs a detection pulse of a second integer) and a lower threshold that is lower than the initial value by the preselected value M, and in response to the first and second detection pulses, the count is down and down, respectively. and outputting the first and second determination result signals when the count increases to an upper threshold value and when the count decreases to a lower threshold value, respectively. polarity determination circuit. 6. connected to the counting means, in response to one of the first and second determination result signals, stopping the counting means and transmitting said one of the first and second determination result signals to the counting means;
6. The polarity determination circuit according to claim 5, further comprising count stop means for continuously outputting the one of the first and second determination result signals even after receiving the one. 7. A polarity determination circuit used in the receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, the transmitting section is configured to A time-division multiplexed digital signal containing consecutive multi-frames including 2, . The frames include a multi-frame synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multi-frame synchronization signal, and each of the second to Nth frames of each multi-frame , a frame synchronization signal and a transmission data signal following the frame synchronization signal, and each of the at least two frame synchronization signals of the second to Nth frames of each multiframe has a first predetermined synchronization signal. The receiver receives the time division multiplexed digital signal from the transmission path as a received digital signal, and the received digital signal is transmitted as a received digital signal. When the transmission line is connected correctly in polarity between the transmitter and the receiver, it has a true polarity equal to the polarity of the time division multiplexed digital signal, and the received digital signal When the polarity is incorrectly connected, the polarity is reversed to the true polarity, and the polarity determination circuit determines whether the received digital signal has the true polarity or the reversed polarity. The polarity determination circuit thereby determines, respectively, that the received digital signal has a true polarity and that the received digital signal has an inverted polarity for the first and second determination result signals. The first and second determination result signals are:
A first predetermined polarity determining circuit receives the received digital signal and determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. a first synchronization word detection means for detecting a synchronization word and outputting a first detection pulse each time a first predetermined synchronization word is detected; a second synchronization word detection means that detects a synchronization word and outputs a second detection pulse every time a second predetermined synchronization word is detected; and a second synchronization word detection means connected to the first and second synchronization word detection means. , an upper threshold that is higher than the initial value by a preselected value M (M is a second integer greater than or equal to 2), and a lower threshold that is lower than the initial value by the preselected value M. In response to the first and second detection pulses, the count is increased and decreased, respectively, and the first and second determination result signals are determined when the count decreases to a lower threshold value and when the count decreases to a lower threshold value. 1. A polarity determining circuit comprising: counting means that outputs an output when the polarity increases to an upper threshold value. 8. connected to the counting means, in response to one of the first and second determination result signals, stopping the counting means and transmitting said one of the first and second determination result signals to the counting means;
8. The polarity determination circuit according to claim 7, further comprising count stop means for continuously outputting the one of the first and second determination result signals even after receiving the one. 9. A polarity determination circuit used in the receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, the transmitting section is configured to A time-division multiplexed digital signal containing consecutive multi-frames including 2, . The frames include a multi-frame synchronization signal representing a first predetermined synchronization word and a transmit data signal following the multi-frame synchronization signal, and each of the second to Nth frames of each multi-frame , a frame synchronization signal and a transmission data signal following the frame synchronization signal, and each of the at least two frame synchronization signals of the second to Nth frames of each multiframe has a first predetermined synchronization signal. the second to Nth frames, excluding said at least two of the second to Nth frames of each multiframe, representing a second predetermined synchronization word determined by reversing the word; at least one frame synchronization signal representing a third predetermined synchronization word that is different from both the first and second predetermined synchronization words, and the at least one frame synchronization signal of each of the at least two remaining frame synchronization signals representing a fourth predetermined synchronization word determined by inverting the third predetermined synchronization word; A time division multiplexed digital signal is received as a received digital signal from a transmission line, and when the transmission line is connected correctly between the transmitting part and the receiving part in polarity, the received digital signal has a true value equal to the polarity of the time division multiplexed digital signal. When the transmission line is connected between the transmitting section and the receiving section in the wrong polarity, the received digital signal has a polarity that is inverted from the true polarity, and the received digital signal has a polarity that is inverted from the true polarity. determines whether the received digital signal has true polarity or inverted polarity, and the polarity determination circuit thereby converts the first and second determination result signals into, respectively,
When the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, the polarity determination circuit outputs the first and second polarity. receiving the received digital signal in the polarity determining circuit, wherein the determination result signals indicate that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively;
first synchronization word detection means for detecting a first predetermined synchronization word and outputting a first detection pulse each time the first predetermined synchronization word is detected; receiving a received digital signal; second synchronization word detection means for detecting a second predetermined synchronization word and outputting a second detection pulse each time the second predetermined synchronization word is detected; receiving a received digital signal; third synchronization word detection means for detecting a third predetermined synchronization word and outputting a third detection pulse each time the third predetermined synchronization word is detected; receiving a received digital signal; a fourth synchronization word detection means for detecting a fourth predetermined synchronization word and outputting a fourth detection pulse every time the fourth predetermined synchronization word is detected; A first initial value and a value M(
M is a second integer greater than or equal to 2);
a first lower threshold value that is lower than a first initial value by the preselected value M, and in response to first and second detection pulses, the first count is down and up, respectively. , a first output signal for outputting first and second output signals when the first count increases to a first upper threshold and when the first count decreases to a first lower threshold, respectively.
a counting means connected to the first counting means, said first and said second counting means;
in response to one of the first and second output signals, stopping the first counting means and transmitting the one of the first and second output signals to the first counting means. The first output signal continues to be output even after receiving the one of the output signals.
a second initial value and a second upper threshold value which is connected to the third and fourth synchronization word detection means and which is higher than the second initial value by the preselected value M; , a second lower threshold that is lower than the second initial value by the preselected value M;
In response to third and fourth detection pulses, a second count is down and up, respectively, and a third and fourth output signal is output when the second count increases to a second upper threshold; a second counting means for respectively outputting when the second count decreases to a second lower threshold;
in response to one of the output signals of the third and fourth output signals. A second output signal that continues to be output even after receiving the one of the output signals of
and a count stop means connected to the first and second counting means, and transmitting the first and second determination result signals while receiving the first and third output signals and the second counting means. and a determination result signal generating means that generates each determination result signal while receiving the fourth output signal. 10. A polarity determination circuit used in a receiving section of a digital transmission network including a transmitting section, a receiving section, and a transmission path between the transmitting section and the receiving section, wherein the transmitting section determines whether each multiframe is first,
A time division multiplexed digital signal containing consecutive multi-frames including the second, ..., and N-th frames (N is a first integer of 3 or more) is transmitted to the transmission path, and the One frame includes a multiframe synchronization signal representing a first predetermined synchronization word and a transmission data signal following the multiframe synchronization signal, and each of the second to Nth frames of each multiframe includes a frame synchronization signal and a transmission data signal following the frame synchronization signal, and each of the at least two frame synchronization signals of the second to Nth frames of each multiframe is
representing a second predetermined synchronization word determined by inverting the first predetermined synchronization word, excluding said at least two of the second to Nth frames of each multiframe; , at least one frame synchronization signal of the second to Nth frames is
representing a third predetermined synchronization word different from any of the predetermined synchronization words of the frame synchronization signals of at least two remaining frames of the second through Nth frames of each multiframe; determined by inverting a third predetermined synchronization word,
The reception section receives the time division multiplexed digital signal from the transmission path as a reception digital signal, and the reception section receives the reception digital signal from the transmission path between the transmission section and the reception section. When connected correctly, the received digital signal has a true polarity equal to the polarity of the time-division multiplexed digital signal, and when the transmission line is connected incorrectly in polarity between the transmitter and the receiver, The polarity determination circuit determines whether the received digital signal has a true polarity or an inverted polarity, and the polarity determination circuit thereby determines whether the received digital signal has a true polarity or an inverted polarity. and a second determination result signal when the polarity determination circuit determines that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively. It is a thing,
In the polarity determination circuit, the first and second determination result signals indicate that the received digital signal has a true polarity and that the received digital signal has an inverted polarity, respectively; first synchronization word detection means that receives the received digital signal, detects a first predetermined synchronization word, and outputs a first detection pulse every time the first predetermined synchronization word is detected; a second synchronization word detection means that receives the received digital signal, detects a second predetermined synchronization word, and outputs a second detection pulse every time the second predetermined synchronization word is detected; third synchronization word detection means that receives the received digital signal, detects a third predetermined synchronization word, and outputs a third detection pulse every time the third predetermined synchronization word is detected; fourth synchronization word detection means that receives the received digital signal, detects a fourth predetermined synchronization word, and outputs a fourth detection pulse every time the fourth predetermined synchronization word is detected; is connected to the first and second synchronization word detection means, and is connected to the first initial value and a value M (M
is a second integer greater than or equal to 2), and a first upper threshold value that is lower than the first initial value by the preselected value M.
a lower threshold of , and in response to the first and second detection pulses, respectively up and down the first count;
The first count outputs the first and second output signals.
a first counting means that outputs an output when the first count decreases to a lower threshold value and when the first count increases to a first upper threshold value, respectively; 2
in response to one of the first and second output signals, stopping the first counting means and transmitting the one of the first and second output signals to the first counting means. The first output signal continues to be output even after receiving the one of the output signals.
a second initial value;
a second upper threshold that is higher than the second initial value by the preselected value M, and a second lower threshold that is lower than the second initial value by the preselected value M; 2 counts up and down, respectively, and third and fourth output signals when the second count decreases to a second lower threshold and when the second count increases to a second upper threshold. a second counting means that outputs an output when the third and fourth counting means are connected to the second counting means,
in response to one of the output signals of the third and fourth output signals. A second output signal that continues to be output even after receiving the one of the output signals of
counting stop means connected to the first and said second counting means;
and said second determination result signal to said first and said third determination result signal.
and a determination result signal generating means that generates a determination result signal while receiving the output signal and while receiving the second and fourth output signals, respectively.