JPH0321996U - - Google Patents
Info
- Publication number
- JPH0321996U JPH0321996U JP1989079532U JP7953289U JPH0321996U JP H0321996 U JPH0321996 U JP H0321996U JP 1989079532 U JP1989079532 U JP 1989079532U JP 7953289 U JP7953289 U JP 7953289U JP H0321996 U JPH0321996 U JP H0321996U
- Authority
- JP
- Japan
- Prior art keywords
- equalizer amplifier
- gain
- feedback loop
- equalizer
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Electric Motors In General (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は本考案の映像再生回路への適用例を示す
ブロツク図、第３図は本考案のＰＬＬ回路への適
用例を示すブロツク図、第４図は従来のサーボ回
路を示すブロツク図である。
１，５……減算器、２，４，６，７，８……イ
コライザアンプ、３……加算器。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a block diagram showing an example of application of the present invention to a video playback circuit, Fig. 3 is a block diagram showing an example of application of the invention to a PLL circuit, and Fig. 4 is a block diagram showing a conventional servo circuit. be. 1, 5...subtractor, 2, 4, 6, 7, 8...equalizer amplifier, 3...adder.
Claims (1)
のフイードバツクループを有し、上記第２のフイ
ードバツクループで検出した残留エラーを上記第
１のフイードバツクループに加算することにより
上記第１のフイードバツクループの残留エラーを
相殺することを特徴とするサーボ回路。 (2) 上記第１のフイードバツクループはゲイン
Ｇ１の第１のイコライザアンプとゲインＧ２の第
２のイコライザアンプとを有し、上記第２のフイ
ードバツクループはゲインＧ３の第３のイコライ
ザアンプとゲインＧ４の第４のイコライザアンプ
とを有し、上記第３のイコライザアンプの出力を
ゲインＧ５の第５のイコライザアンプを介して上
記第１のイコライザアンプの出力と加算して上記
第２のイコライザアンプに入力し、上記第２乃至
第５のイコライザアンプのゲインを「Ｇ２×Ｇ３
×Ｇ５≒１＋Ｇ３×Ｇ４」なる関係に設定するこ
とを特徴とする請求項１記載のサーボ回路。[Claims for Utility Model Registration] (1) First and second claims having the same structure
, and the residual error detected by the second feedback loop is added to the first feedback loop to offset the residual error of the first feedback loop. A servo circuit characterized by: (2) The first feedback loop has a first equalizer amplifier with a gain of G1 and a second equalizer amplifier with a gain of G2 , and the second feedback loop has a first equalizer amplifier with a gain of G2 . 3 and a fourth equalizer amplifier with a gain of G4 , and the output of the third equalizer amplifier is added to the output of the first equalizer amplifier via a fifth equalizer amplifier with a gain of G5 . and input it to the second equalizer amplifier, and the gains of the second to fifth equalizer amplifiers are calculated as "G 2 × G 3
2. The servo circuit according to claim 1, wherein the servo circuit is set to the following relationship: xG5 ≒ 1 + G3xG4 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989079532U JPH0321996U (en) | 1989-07-07 | 1989-07-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989079532U JPH0321996U (en) | 1989-07-07 | 1989-07-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0321996U true JPH0321996U (en) | 1991-03-06 |
Family
ID=31623771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989079532U Pending JPH0321996U (en) | 1989-07-07 | 1989-07-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0321996U (en) |
-
1989
- 1989-07-07 JP JP1989079532U patent/JPH0321996U/ja active Pending
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