JPH0322032A - Program exception code control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to enable a program exception code control circuit that notifies a program of a detected exception code to appropriately respond even when two or more types of completion type exceptions are detected. A latch means for temporarily holding the exception code by using a code indicating that there is no exception code as an initial code, a memory means for storing the exception code, and a detected exception code and data held by the latch means. As human data, when a general exception code is detected, select it,
-i When no exception code is detected and a completion type exception code is detected, if the retained data is an initial code, selects the detected completion type exception code, and if it is a completion type exception code, it is retained. If no exception code is detected, if the held data is a completion type exception code, select it, and if it is an initial code, select the one with higher priority. The latch means inputs the output of the selection means and updates the held data according to a predetermined cycle during instruction execution, and the memory means updates the held data according to a predetermined cycle during execution of the instruction. Care is taken to remember the exception code of this retained data that was finally updated during processing.

[Industrial Application Field] The present invention relates to a program exception code control circuit that processes a general exception code and a completion type exception code indicating the interrupt type detected during the execution of a program instruction so as to notify the program. This invention relates to a program exception code control circuit that allows a circuit to be implemented with a limited number of gates, and also allows for appropriate handling of cases where two or more types of completion type exceptions are detected in the same instruction.
The program exception code control circuit is a control circuit that stores an exception code representing the interrupt type detected when a program instruction is executed at a fixed address in memory, and the detected exception code suppresses or invalidates the program instruction. - If it is a general exception code that specifies interruption, the detected exception code is processed so as to be stored at a fixed address in order to immediately enter interrupt processing, and the detected exception code is not allocated until the program instruction is completed. If it is a completion-type exception code that specifies entry into processing, the exception code is detected after waiting for the program instruction to complete and is processed to be stored at a fixed address. In recent years, additional functions such as address expansion, new VM mechanisms, expanded storage, etc. have been considered, and new exception codes have been defined accordingly. From now on, an increase in the amount of hardware required for program exception code control circuits as the number of focus points increases has become a problem. Also, depending on the additional features,
For programs where two or more types of completion type exceptions are detected in the same instruction, it is becoming impossible to execute the instructions in the priority order of the completion type exceptions, and the program exception code control circuit There is a growing need for the government to be organized to deal with this.

[Conventional technology]

FIG. 4 shows the configuration of a conventional program exception code control circuit according to the write stage, which is the last stage of the pipeline. In FIG. 4(a), 10 is a general exception detection circuit, which detects a general exception of a program and outputs the general exception code, and 1l is a completion type exception detection circuit, which detects a general exception of a program and outputs the general exception code. 12 is CMPL X which detects an exception and outputs its completion type exception code.
A V latch which is set when a completion type exception is detected by the completion type exception detection circuit 1l and outputs a Hl output (CMPL XV signal in the figure), 13 is a CM
PL XC register, completion type exception detection circuit 1
1 stores the completion-type exception code to be output, and 14 is an exception code selection circuit that refers to the valid signal of the exception code to output the general exception code of the general exception detection circuit 10 and the completion type of the CMP LXC register 13. 15 is a PGM XC register which is selected by the exception code selection circuit 14. 16 is an OR gate that stores the exception code, and when the END OP signal indicating the completion of a program instruction is issued,
17 is an OR gate that resets the Hl output of the CMPL XV latch 12 when the STATE signal is output, and when the completion type exception detection circuit 11 outputs a valid signal of the completion type exception code, the CMPL XV latch 12 18 is an AND gate, and OR gate 17 outputs an I{I output when outputs an Hl output.
19 is an OR gate which outputs a Hl output when the AND gate 18 outputs an Hl output, and when the AND gate 18 outputs an Hl output, the general exception detection circuit 10 detects a general exception. 20 is an AND gate that outputs Hl output when outputting a code valid signal, and PGMR that is output when OR gate 19 outputs }II output and machine check is not performed.
21 is a PGM RUPT latch that outputs Hl output (SET PGM LCH signal in the figure) when there is an U P T E N B L signal;
Latch the Hl output of the ND gate 20 (PGM in the figure)
RUPT LCH signal).

The double line in the figure represents an exception code signal, and the solid line represents a detection signal. Further, the general exception detection circuit 10 and the completion type exception detection circuit 1l actually exist in each stage of the pipeline, and the general exception detection circuit 10 and the completion type exception detection circuit 11 of each stage detect the The exception code is detected by the general exception detection circuit 10 of the write stage.
and is sent to the completion type exception detection circuit 1l, but is shown here in a simplified manner for convenience of explanation.

As shown in FIG. 4(b), the CMPL Xc register l
CMPL XC to enable 3
The CLK ENBL signal is 7cM according to buffer 22.
It will be output when the PL XV latch 12 is outputting the LO output, and the PGM RUPT launch 2
PGM RUPT to enable l
LCH CLK ENBL signal is OR gate 2
3, the PROCESS STATE signal or ST
It will be output when either one of the OP STATE signals is output, and the PGM XC register l
PGM XC C to enable 5
The LK ENBL signal, according to AND gate 24,
PGM RUPT LCH CLK ENBL
Under the condition that the signal is output, and from the AND gate 20
It will be output when the ET PGM LCH signal is output. RESTO which is the human power of OR gate 16 explained above
RE STATE signal, PROCESS STATE signal and STOP which are human power of OR gate 23
The STATE signal is the output signal of the state machine. Figure 5 shows the transition diagram of this state machine. Next, the operation processing of the conventional program exception code control circuit that is tlffled in this way will be explained. When the general exception detection circuit 10 detects the occurrence of a general exception and outputs a general exception code, the exception code selection circuit 14 selects the CMP
Regardless of the presence or absence of the completion type exception code of the LXC register l3 or the completion type exception code of the completion type exception detection circuit 1l,
Select this general exception code to be output, and
The ND gate 20 outputs the SET PGM LCH signal. When the SET PGM LCH signal is output, the AND gate 24 outputs the PROCESS STA signal.
PGM XC CLK according to AND with TE signal
Outputs ENBL signal and registers PGM
5 is enabled according to this PGM XC CLK ENBL signal and the exception code selection circuit l
4 stores the selected general exception code. And S.E.
When the T PGM LCH signal is output, the state transitions from the PROCESS state to the RESTORE state according to logic not shown.
The GM xC CLK ENBL signal disappears in one machine cycle. In this way, as shown in FIG. 5, the general exception code stored in the PGM is stored at a fixed address in memory, and processed to notify the program of the general exception code.

On the other hand, the completion type exception detection circuit 1l detects a completion type exception in the middle of a program instruction consisting of multiple flows (when multiple flows occur, the program instructions are configured so that the one with the highest priority is placed first) CMPL Xv latch 1, which detects the occurrence of the
2 indicates that a completion type exception has occurred by outputting the CMPL XV signal, and the CMPL Process to retain the completion type exception code.

According to this process, the exception code selection circuit 14 selects the completion type exception code of the CMPL XC register 13 on the condition that the general exception detection circuit 10 does not output a general exception code. Then, AND gate 18 is E
When the completion of the program instruction that caused the completion type exception is confirmed according to the ND OP signal, the AND gate 20
outputs the SET PGM LCH signal.

In this way, when the SET PGM LCH signal is output, the generated completion-type exception code is converted to
By storing the data at a fixed address in the memory via the C, M XC register 15, it is processed so as to be notified to the program.

On the other hand, when the completion-type exception detection circuit 11 detects the occurrence of a completion-type exception in the final flow of a program instruction and outputs a completion-type exception code, the exception code selection circuit l4 detects that the general exception detection circuit lO detects the general exception code. This completion type exception detection circuit 1 is not output and the CMPL XC register 13 does not hold a completion type exception code.
Select completion type exception code 1. And the above C
Following the same processing as the completion type exception code held in the MPL XC register l3, the generated completion type exception code is stored in the memory via the PC; By storing it at the fixed address above, it will be processed to notify the program.

As mentioned above, by transitioning to the ENDPROC state for interrupt processing via the RESTORE state, P
When the exception code stored in the GM MC register 15 is expanded to the memory, in this ENDPROC state, a new PSW for program interrupt is further set, and then, via the next START state, PROCES
By entering the S state, processing is performed to enter execution of the interrupt routine.

Figure 6 shows a time chart when a completion type exception is detected in the middle of a program instruction flow. This time chart shows an example where a completion type exception is detected in the first flow. In addition, as shown in this figure, PGM
RUPT Lunch 21 is PROCESS STAT
PGM RUPT LC sent out according to E signal
The SET PGM from AND gate 20 is enabled by the H CLK ENBL signal.
The LCH signal outputs the PGM RUPT LCt{ signal, and the PGMRU becomes disabled by transitioning to the RESTORE state.
Hold PT LCH signal and PROCESS
By transitioning to the state, the PGM RUPT LCH signal becomes enabled again and the PGM RUPT LCH signal is processed to disappear.

[Problem to be solved by the invention]

However, such a conventional program exception code control circuit has a problem in that the number of gates increases because the CMPL XC register l3 is a register having an output function. This problem becomes more serious as the number of required bits increases as the number of completion type exception types increases.

In the conventional program exception code control circuit, the exception code selection circuit 14 selects the CMPL XC register 1
Since the completion type exception code of 3 was selected with priority over the completion type exception code of the completion type exception detection circuit 1l, the program detected two or more types of completion type exceptions with the same instruction. For instructions, it is necessary to define an execution procedure so that a completion type exception with a high priority is detected first, but depending on the newly added function, such an execution procedure may be adopted. However, there are cases where program instructions that cannot be executed are generated, and this has become a problem that cannot be dealt with. Moreover, in the conventional program exception code control circuit, P
GM There was also the problem that it gave rise to a misunderstanding that a program exception had occurred due to the executed instruction.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a new program exception code control circuit that can solve the problems of the prior art.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle structure of the present invention.

In the figure, 1 is a general exception detection means that detects a general exception in a program and outputs the general exception code;
2 is a completion type exception detection means that detects a completion type exception of a program and outputs the completion type exception code;
3 is a completion type exception code display means for displaying that a completion type exception has been detected by the completion type exception detection means 2; 4 is an exception code latch means for displaying a code indicating that there is no exception code; 5 is an exception code selection means which is used as an initial code to temporarily hold an exception code detected during the execution of a program instruction while updating it according to a predetermined cycle. The detected general exception code, the completion type exception code detected by the completion type exception detection means 2, and the exception code held by the exception code latch 4 are input data, and one of them is selected according to a predetermined selection procedure. 6 is an exception code memory means which selects one exception code and outputs it to the exception code latch stage 4, which stores the exception code of the exception code latch means 4 that is finally updated at the end of program interrupt processing. , 7 is an interrupt processing requesting means, which stores a valid signal of the general exception code generated by the general exception detection means 1, a valid signal of the completion type exception code generated by the completion type exception detection means 2, It receives the display signal generated by the completion type exception code display means 3 and the END OP signal as input, and outputs an interrupt request signal for entering interrupt processing.

Here, the exception code selection means 5 specifies that the state machine is S.
Processing is performed to select the data held by the exception code latch means 4 on the condition that no exception code is detected in the TOP state.

[Effect]

In the present invention, the exception code selection means 5 processes so as not to select any manual data when a general exception and a completion type exception are not detected, so the exception code latch means 5
will continue to retain the initial code indicating that there is no exception code. At this time, when the general exception detection stage 1 detects a general exception, the exception code selection means 5 selects the general exception code output by the general exception detection stage 1 regardless of other manual data, and selects the general exception code output by the general exception detection stage 1, Process to set it to 4. When the interrupt processing request stage 7 detects the valid signal of the general exception code from the general exception detection means 1, it completes the update process of the exception code latch means 40 and outputs an interrupt request signal. In this way, when the interrupt processing is started, the general exception code stored in the exception code latch means 4 is notified to the program, and the exception code memory 6 is used for interrupt processing. Processing is performed to store the general exception code of the exception code latch means 4 notified to the program at the time of termination.

Further, the exception code selection means 5 includes the completion type exception detection stage 2.
When detects a completion type exception, the process selects the completion type exception code of this completion type exception and sets it in the exception code latch means 4, provided that no general exception is detected. Thereafter, when the exception code selection means 5 is not notified of a new completion type exception code from the completion type exception detection means 2, the exception code selection means 5 selects the completion type exception code held by the exception code latch means 4. process so that it retains the intact completion type exception code. on the other hand,
When a new completion type exception code is notified from the completion type exception detection means 2, the exception code selection means 5 selects the priority of the completion type exception code held by the exception code latch means 4 and the newly notified completion type exception. The priorities of the codes are compared, and the completion type exception code with the higher priority is selected and set in the exception code latch means 4. In this way, the exception code latch 4 is configured to hold the completion type exception code while updating it to a completion type exception code with a higher priority when a completion type exception is detected without an In exception being detected. Process.

When the interrupt processing request means 7 detects the completion of the instruction related to the completion type exception code according to the END OP signal, it completes the update processing of the exception code latch 4 and outputs an interrupt request signal. . In this way, when the interrupt processing is started, the completion type exception code stored in the exception code latch means 4 is notified to the program, and the exception code memory means 6 is used for interrupt processing. Processes to store the completion type exception code of exception code latch 4, which was notified to the program at the time of termination. In this way, in the present invention, the exception code latch means 4
Since we take care to preserve the completion type exception code with the highest priority while looping back, we can respond appropriately to program instructions that cannot be detected so that the completion type exception with the highest priority is detected first. become able to. Furthermore, while the CMPL XC register 13 of the prior art is a register with an output function, the exception code memory means 6 can be a register without an output function, so that it can be implemented with a small number of gates.

Moreover, if the instruction ends normally according to the start of the interrupt process, an initial code indicating that there is no exception code is set in the exception code latch means 4, so that a program exception occurs with the currently executed instruction. Such misunderstandings can be avoided, and it is also ensured that the exception code used for interrupt processing can be known in accordance with the exception code memory means 6. Then, in the exception code selection stage 5, the state machine is S
When the CPU is in the TOP state and no exception code is detected, the data held in the exception code latch 4 is looped back, so the CPU takes over the processing of the service processor. This also makes it possible to implement processing in which the service processor takes over the processing of program interruptions caused by CPU commands and their exceptions.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 shows the configuration of an embodiment of the program exception code control circuit of the present invention according to the write stage, which is the last stage of the pipeline. In the figure, the same parts as shown in FIG. 4 are indicated by the same symbols. In FIG. 2(a), 15a is a PGM
14a is an exception code selection circuit according to the present invention, which uses 0"' as an initial code and temporarily stores an exception code detected during execution of a program instruction while updating it according to a predetermined cycle. , the general exception code from the general exception detection circuit lO and the PGM X that is looped back.
Using the completion type exception code of the C register 15a, the completion type exception code from the completion type exception detection circuit 11, and the ALL "0" code as input codes, the valid signal of the exception code and the PGM XC register 15a hold the input code. One input code is selected by referring to the priority of the completion type exception code. 30 is a RETAIN register, and the PGM XC register 15a which is finally updated at the end of program interrupt processing It stores exception codes. As shown in FIG. 2(b), PGM XC register 1
PGM XC to enable 5a
CLK ENBL signal and PGM RUPT to enable PGM RUPT latch 21
The LCH CLK ENBL signal is either the PROCESS STATE signal or the S
It will be output when either one of the TOP STATE signals is output, and the RETAIN register 3
RETAIN CL to enable 0
The K ENBL signal, according to AND gate 32,
It will be output under the conditions that the GM RtJPT LCH signal is output and when the STRAT STATE signal is output.

Next, the operation processing of the program exception code control circuit of the present invention configured as described above will be explained. When the general exception detection circuit 10 does not detect a general exception and the completion type exception detection circuit l1 does not detect a completion type exception, the exception code selection circuit 14a selects the input data of ALL "0", PGM MC in enabled state according to PROCESS STATE signal
Processing is performed to set it in the register 15a. In this way, when neither a general exception nor a completion type exception is detected,
The PGM XC register 15a continues to hold ALL "0" indicating that there is no exception code.

On the other hand, when the general exception detection circuit 10 detects the occurrence of a general exception and outputs a general exception code, the exception code selection circuit 1
4a selects this general exception code to be output, regardless of the completion type exception code of the completion type exception detection circuit 1l, the hold code of the PGM MC register 15a to be looped back, or the input code of ALL゛0゛゜. At the same time, the AND gate 20 outputs the SET PGM LCH signal, which is an interrupt request signal. At this time, as in the prior art, PGM RUPT
By setting the latch 21, PGM RUPT
LCH signal is output. In this way, SET
When the PGM LCI{ signal is output, the state transitions from the PROCESS state to the RESTORE state according to the logic not shown and enters interrupt processing, so the PGM XC register 15a becomes disabled and the general exception code is output. PGM XC
It will be held in the register 15a.

By starting the interrupt processing according to the SET PGM LCH signal, the E
When the interrupt processing microprogram is activated by transitioning to the NDPROC state, the PGM XC register 15
The general exception code stored in a is stored at a fixed address in memory, and the general exception code is processed to be notified to the program. and,
After the interrupt processing is finished, the execution of the interrupt routine begins.<ST
When the ART STATE signal is output, the RETAIN CLK is output from the AND gate 32 according to the AND with the output PGM RUPT LCH signal.
When the ENBL signal is output, the RETAIN register 30 is enabled, and the general exception code stored in the PGM XC register 15a is set to RETAIN.
It will be stored in the IN register 30. On the other hand, when the completion type exception detection circuit 1l detects the occurrence of a completion type exception and outputs a completion type exception code, the exception code selection circuit 14a detects the completion type exception code that is output on the condition that the general exception code is not output. Select the type exception code and
PC in the enabled state: Processes to set it in the M
Outputs CH signal. The CMPL XV latch 12 then outputs the CMPL XV signal to indicate that a completion type exception has occurred.

In this way, when the completion type exception code is held in the PGM XC register 15a, the exception code selection circuit 14a
When a general exception code is not notified from the general exception detection circuit 10 and a new completion type exception code is not notified from the completion type exception detection circuit l1, the completion type exception code held in the PGM Output. According to this selection process, the PGMMC register 15
a is PGM until the END OP signal is output.
Processing is performed so that it continues to be held by updating the same completion type exception code while looping back in synchronization with the clock cycle of the XC CLK ENBL signal. The exception code selection circuit 14a selects the CMPL during this holding process.
When it is learned that a notification of a new completion type exception code will be received from the completion type exception detection circuit 1l according to the display of the XV latch l2, the priority of the held completion type exception code (priority between completion type exception codes) is determined. ) and the priority of the new completion type exception code that is notified, and selects and outputs the completion type exception code with the higher priority. According to this selection process, the PGM XC register 15a is
When a completion-type exception code with a higher priority than the completion-type exception code held by the completion-type exception detection circuit l1 is notified, the completion-type exception code is continued to be held while updating to the new completion-type exception code. It will be processed as follows.

Then, when the END OP signal of the program instruction that generated the completion type exception code is output, the AND gate 20
When the SET PGM LCH signal is output from
According to the same process as when a general exception code is output, the PGM The completion-type exception code with the highest priority that has completed is stored at a fixed address in memory, and processing is performed so that the program is notified of the completion-type exception code. Then, when the interrupt processing is completed, the RETAIN CLK ENBL signal is output and the RETAIN register 3o is enabled, so that the completion type exception code of the PGM XC register 15a that has entered the interrupt processing is stored in the RETAIN register 3o. It will be done. FIG. 3 shows a time chart when a completion type exception is detected in the flow of a program instruction. As can be seen by comparing this time chart with the time chart in FIG. 6, in the conventional technology, the PGM XC register 15 retains the exception code that entered the interrupt process until the next program exception occurs. In contrast, in the present invention, the RETATN register 30 holds the exception code that entered the interrupt process, and the PGM XC register 1
5a clears the exception code and does not retain it when the normal state is restored. From now on, in the present invention, from the service processor to the PGM XC register 1
When scanning out RETAIN register 30, it is possible to prevent the misunderstanding that a program exception has occurred due to the currently executed instruction. It also ensures that you know the exception code.

Then, when the state machine is in the STOP state and no exception code is detected, the exception code selection circuit 14a processes the data held in the PGM XC register 15a to loop back. According to this process, it becomes possible to realize a function in which the CPU performs service processor processing such as changing registers during the STOP state, and also enables the service processor to perform program interrupts caused by CPU instructions and their exceptions on behalf of the CPU. become. Although the illustrated embodiment has been described above, the present invention is not limited thereto. For example, in the embodiment, the exception code selection circuit 14a is configured to select the initial code ALL "O" by forcing it to be input, but when a general exception or a completion type exception is not detected, any input If you take care not to select any data, ALL “0”
This means that equivalent processing can be achieved without inputting ``.

〔Effect of the invention〕

As described above, according to the present invention, the PGM It will be possible to respond appropriately to program instructions that cannot be made as desired.

And, while the CMPL XC register 13 of the prior art is a register with an output function, the RETAI
Since the N register 30 is a register that does not have an output function, it can be implemented with a small number of gates. Furthermore, even if an instruction completes normally, it does not give rise to the misunderstanding that a program exception has occurred due to the currently executed instruction, and it is also ensured that the exception code that handled the interrupt can be known. be. Furthermore, the SET PGM LCH signal is a PGM signal generated through a gate circuit for machine check.
Since it is generated via the RUPT ENBL signal, it is an unavoidable signal that is delayed, but in the present invention, the PGM
This SET sets the PGM XC CLKENBL signal to enable the XC register 15a.
Since the interrupt processing can be performed regardless of the PGM LCH signal, there is an advantage that the responsiveness of interrupt processing can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle structure of the present invention, FIG. 2 is an embodiment of the program exception code control circuit of the present invention, FIG. 3 is a time chart of the program exception code control circuit of the present invention, and FIG. 4 is a conventional example. FIG. 5 is a state machine transition diagram, and FIG. 6 is a time chart of a conventional program exception code control circuit. In the figure, 1 is a general exception detection means, 2 is a completion type exception detection means, 3 is a completion type exception code display means, 4 is an exception code latch means, 5 is an exception code selection means, 6 is an exception code memory means, and 7 is a completion type exception detection means. Interrupt processing request means; 10 is a general exception detection circuit; 1l is a completion type exception detection circuit; 12 is a CMPL
V latch, l3 is CMPL XC register, 14 and 14a are exception code selection circuits, 15 and 15a are PGM
The XC register, 21 is the PGM RUPT register, and 30 is the RETAIN register.

Claims (2)

[Claims] (1) In the program exception code control circuit that notifies the program of the general exception code and completion type exception code that represent the interrupt type detected during execution of a program instruction, a code indicating that there is no exception code is used as the initial code, Exception code latch means (4) for temporarily holding a detected exception code; exception code memory means (6) for storing the exception code held by the exception code latch means (4); and a general exception to be detected. code, the detected completion type exception code, and the data held by the exception code latch means as input data,
When a general exception code is detected, select the general exception code, and when the general exception code is not detected and a completion type exception code is detected, and the retained data holds the initial code, the completion type to be detected. In addition to selecting an exception code, if the retained data holds a completion type exception code, select the completion type exception code that has a higher priority between the held completion type exception code or the detected completion type exception code. Then, when a general exception code and a completion type exception code are not detected, if the held data holds a completion type exception code, select the completion type exception code, and if the held data holds an initial code, select the completion type exception code. exception code selection means (5) for processing so as not to select any input data; In addition to updating the held data using the selection output as input, the exception code memory means (6) also updates the data during program interrupt processing.
A program exception code control circuit characterized in that it stores the finally updated exception code of the exception code latch means (4). (2) In the program exception code control circuit according to claim (1), the exception code selection means (5) is provided when the state machine is in the stop state and no exception code is detected. A program exception code control circuit characterized in that the program exception code control circuit performs processing to select the data held by the exception code latch means (4).