JPH03220633A - Emulator for read only memory - Google Patents
Emulator for read only memoryInfo
- Publication number
- JPH03220633A JPH03220633A JP2017099A JP1709990A JPH03220633A JP H03220633 A JPH03220633 A JP H03220633A JP 2017099 A JP2017099 A JP 2017099A JP 1709990 A JP1709990 A JP 1709990A JP H03220633 A JPH03220633 A JP H03220633A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- emulator
- storage device
- external storage
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 19
- 230000010365 information processing Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は読み出し専用メモリのエミュレータに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a read-only memory emulator.
従来、この種のエミュレータは、対象とする読み出し専
用メモIJ(ROM)を含むCPU部分を擬次的な内部
回路で置き換え、本エミュレータを通して、端末等性の
情報処理装置から制御及び主要制御信号やレジスタ等の
状態を知ることが出来るようになっている。Conventionally, this type of emulator replaces the CPU part including the target read-only memory IJ (ROM) with a pseudo internal circuit, and receives control and main control signals from an information processing device such as a terminal through this emulator. This allows you to know the status of registers, etc.
上述した従来のエミュレータは、CPU部分を入れ換え
るため、CPUがない情報処理装置、すなわちROM内
のプログラムに従って順次に制御される装置やCPUの
性能・形状等が異なる場合使用出来ず、また端末等性の
情報処理装置を使用して制御するため、他の情報処理装
置がなければエミュレータの機能を使用出来ないという
欠点がある。Since the conventional emulators described above replace the CPU part, they cannot be used in information processing devices without a CPU, that is, devices that are sequentially controlled according to programs in ROM, or in cases where the CPUs have different performance, shape, etc. Since the emulator is controlled using one information processing device, it has the disadvantage that the functions of the emulator cannot be used without another information processing device.
本発明のROMエミュレータは、外部よりデータプログ
ラム等を内部の書き換え可能なメモリーに取り込む為の
外部記憶装置用インターフェース部と、
対象装置である読み出し専用メモリと差し換え可能なコ
ネクタ部と、
予め格納している前記ROMのピン数やピンアサイン情
報により、前記取り込んだデータプログラム等を前記コ
ネクタ部に選択的に供給する信号線線択回路とを有する
ことを特徴とする。The ROM emulator of the present invention has an interface section for an external storage device for importing data programs etc. from the outside into the internal rewritable memory, a connector section that can be replaced with the read-only memory that is the target device, and a ROM emulator that is stored in advance. The present invention is characterized by comprising a signal line selection circuit that selectively supplies the loaded data program, etc. to the connector section depending on the number of pins of the ROM and pin assignment information.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
外部記憶装置インタフェース部2は外部記憶装置1から
必要なプログラムのファイルを取り出す為の制御部であ
る。The external storage device interface section 2 is a control section for retrieving necessary program files from the external storage device 1.
主制御回路部3は本装置がエミエレートすべきROMの
ピン数・ビシアサインによって、メモリ[110と情報
処m**のパスの整合のm書及び外部記憶装置1から読
み込んだプログラムをメモリ部10上に展開しかつコネ
クタ部11からプログラムを情報処理装置に出力する為
の制御を行なう。信号線選択回路7は、この制御により
、信号制御回路5からの信号を振向ける信号線を選択す
る。外部記憶装置1には、これらに必要な情報が予め格
納されており、主制御回路3に読み取られて余支上の制
御のベースとなる。The main control circuit section 3 transfers the program read from the external storage device 1 and the matching path between the memory [110 and the information processing m** to the memory section 10 according to the number of pins and the visa sign of the ROM to be emulated by this device. It performs control for expanding the program into the program and outputting the program from the connector section 11 to the information processing device. Through this control, the signal line selection circuit 7 selects the signal line to which the signal from the signal control circuit 5 is directed. Necessary information is stored in the external storage device 1 in advance, and is read by the main control circuit 3 and becomes the basis for controlling the rest.
メモリ部10は外部記憶装置用インターフェース部2か
ら送られてくるプログラムを主制御回路部3の動作にに
よってメモリー6に保持し、コネクタ部11を通してメ
モリの内容を目的の情報処理i置(図示省略)に出力す
る。The memory unit 10 stores the program sent from the external storage device interface unit 2 in the memory 6 through the operation of the main control circuit unit 3, and transfers the contents of the memory to a target information processing device (not shown) through the connector unit 11. ).
なお、信号制御回路4および5は、メモリー6に対する
信号制御、すなわちアクセス、データ書込み、データ読
み出し等と、信号線選択回路7へのタイミング制御を行
なう。Note that the signal control circuits 4 and 5 perform signal control for the memory 6, ie, access, data writing, data reading, etc., and timing control for the signal line selection circuit 7.
以上説明したように本発明は、対象装置のROMと本a
teを差し携える形管をとる為、ROMを持つ装置であ
れば殆どの装置にも使用出来ることや、本装置を単体で
使用できることなどの効果がある。As explained above, the present invention provides the ROM of the target device and the book a.
Because it uses a tube that carries the TE, it has the advantage that it can be used with most devices that have ROM, and that this device can be used alone.
第1図は本発明のブロック図である。
1・・・外部記憶装置、2・・・外部記憶装置用インタ
ーフェース部、3・・・主制御回路部、4,5・・・信
号制御回路、6・・・メモリー、7・・・信号線選択回
路、8・・・ROMソケット用コネクタ、9・・・入出
力インターフェース部、10・・・メモリ部、11・・
・コネクタ部。FIG. 1 is a block diagram of the present invention. DESCRIPTION OF SYMBOLS 1... External storage device, 2... Interface section for external storage device, 3... Main control circuit section, 4, 5... Signal control circuit, 6... Memory, 7... Signal line Selection circuit, 8... ROM socket connector, 9... Input/output interface section, 10... Memory section, 11...
・Connector part.
Claims (1)
モリーに取り込む為の外部記憶装置用インターフェース
部と、 対象装置である読み出し専用メモリと差し換え可能なコ
ネクタ部と、 予め格納している前記ROMのピン数やピンアサイン情
報により、前記取り込んだデータプログラム等を前記コ
ネクタ部に選択的に供給する信号線線択回路とを有する
ことを特徴とする読み出し専用メモリのエミュレータ。[Scope of Claims] An interface section for an external storage device for importing data programs, etc. from the outside into an internal rewritable memory, and a connector section that can be replaced with the read-only memory that is the target device, which are stored in advance. A read-only memory emulator comprising: a signal line selection circuit that selectively supplies the loaded data program, etc. to the connector section according to the number of pins of the ROM and pin assignment information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017099A JPH03220633A (en) | 1990-01-25 | 1990-01-25 | Emulator for read only memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017099A JPH03220633A (en) | 1990-01-25 | 1990-01-25 | Emulator for read only memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220633A true JPH03220633A (en) | 1991-09-27 |
Family
ID=11934565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017099A Pending JPH03220633A (en) | 1990-01-25 | 1990-01-25 | Emulator for read only memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220633A (en) |
-
1990
- 1990-01-25 JP JP2017099A patent/JPH03220633A/en active Pending
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