JPH03220711A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPH03220711A
JPH03220711A JP1479290A JP1479290A JPH03220711A JP H03220711 A JPH03220711 A JP H03220711A JP 1479290 A JP1479290 A JP 1479290A JP 1479290 A JP1479290 A JP 1479290A JP H03220711 A JPH03220711 A JP H03220711A
Authority
JP
Japan
Prior art keywords
layers
layer
thickness
active layer
ceramic capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1479290A
Other languages
Japanese (ja)
Inventor
Takaaki Nakanishi
中西 崇晶
Toru Mori
透 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1479290A priority Critical patent/JPH03220711A/en
Publication of JPH03220711A publication Critical patent/JPH03220711A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To provide a large electric capacity per unit volume and to prevent a delamination, a crack during manufacturing steps by forming a protective layer which does not contribute to the capacity and an active layer which contributes to an electric capacity in a dielectric ceramic layer, and dividing the active layer into two or more layers by the protective layer having a thickness of 100mum or larger. CONSTITUTION:In a laminated ceramic capacity in which dielectric ceramic layers and inner electrodes are alternately laminated, protective layers 1, 3, 5 which do not contribute to an electric capacity and active layers 2, 4 which contribute to an electric capacity are formed in the ceramic layer, and the layers 2, 4 are divided into two or more parts by a plurality of the layers 3 each having 100mum of larger of thickness. In this case, stresses are alleviated by the layers 1, 5 in a state that the number of the inner electrodes is not so many, but many inner electrodes can be laminated as a whole. Thus, the capacity per unit volume can be increased; delamination, and crack during manufacturing steps are eliminated to enhance its reliability.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は積層セラミックコンデンサに関し、特に信頼性
の高い積層セラミックコンデンサに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic capacitor, and particularly to a highly reliable multilayer ceramic capacitor.

[従来の技術] 近年、各種機器の小型軽量化の要求が高まり、電子回路
の高密度化、電子部品の基板上への実装密度が高まるに
つれ、コンデンサも小型高容量化が急速に進んでいる。
[Conventional technology] In recent years, the demand for smaller and lighter equipment has increased, and as the density of electronic circuits and the density of electronic components mounted on circuit boards has increased, capacitors have also become smaller and have higher capacitance. .

この要求を充たすためには、誘電材料の高誘電率化、電
極有効面積比率の改善、誘電体層の薄層化が有効である
。その中でも誘電体層の薄層化、すなわち内部電極間距
離の短縮化は内部電極層数を増やすことができるため、
結局、距離の二乗に反比例して単位体積当たりの容量が
向上するため最も有効であり、グリーンシート作製プロ
セス、装置の改善、高機能化等により各種の試みがなさ
れている。
In order to meet this requirement, it is effective to increase the dielectric constant of the dielectric material, improve the electrode effective area ratio, and make the dielectric layer thinner. Among these, thinning the dielectric layer, that is, shortening the distance between internal electrodes, can increase the number of internal electrode layers.
After all, it is most effective because the capacity per unit volume increases in inverse proportion to the square of the distance, and various attempts have been made to improve the green sheet production process, improve the equipment, and increase functionality.

[発明が解決しようとする課題] 第3図は通常の積層セラミックチップコンデンサの構造
を示したもので、第3図(a)は斜視図、(b)は一対
の内部電極の素子底面への投影図、(C)は素子の長さ
方向の断面図、(d)は素子の幅方向の断面図である。
[Problems to be Solved by the Invention] Figure 3 shows the structure of a typical multilayer ceramic chip capacitor, with Figure 3 (a) being a perspective view and Figure 3 (b) showing the connection of a pair of internal electrodes to the bottom surface of the element. A projection view, (C) a cross-sectional view in the length direction of the element, and (d) a cross-sectional view in the width direction of the element.

同図に示すように、積層セラミックコンデンサは、下部
保護層5上に誘電体セラミック11と内部電極12が交
互に積層され、最上部には上部保護層1が形成されてい
る。各内部電極2a、2bは外部電極10a 、 10
bに接続するようになっている。
As shown in the figure, in the multilayer ceramic capacitor, dielectric ceramics 11 and internal electrodes 12 are alternately laminated on a lower protective layer 5, and an upper protective layer 1 is formed at the top. Each internal electrode 2a, 2b is an external electrode 10a, 10
b.

内部電極間距離を短縮するには誘電体セラミック11と
なるグリーンシートの厚みを薄くする必要があるが、グ
リーンシートの厚みが2071m以下になると従来構造
の素子では以下に述べる事情でコンデンサの製造時に、
剥がれ、クラックなどの不都合が発生する。すなわち、
内部電極は銀パラジウムなど貴金属粉末を有機バインダ
、有機溶媒と混合してペース1〜化し、スクリーン印刷
によりグリーンシート上に形成されるが、その塗布厚み
は通常2〜3朔であり、2μm以下にすることは困難で
ある。従ってこのようなグリーンシートを50〜100
枚積層、熱圧着、一体止すると、内部電極の形成された
部分とその周辺の内部電極が形成されていない部分の間
で厚みの差が積算され、内部電極端部において大きな応
力集中が発生ずる。バインダの熱分解時や焼結時にこの
応力集中が原因となり、デラミネーションやクラックが
発生する。
In order to shorten the distance between internal electrodes, it is necessary to reduce the thickness of the green sheet that becomes the dielectric ceramic 11. However, when the thickness of the green sheet becomes 2071 m or less, it is difficult to manufacture capacitors for devices with conventional structures due to the reasons described below. ,
Inconveniences such as peeling and cracking occur. That is,
The internal electrodes are formed by mixing noble metal powder such as silver palladium with an organic binder and an organic solvent to form paste 1 and screen printing on a green sheet. It is difficult to do so. Therefore, 50 to 100 such green sheets
When laminating, thermocompression bonding, or integrally bonding, the difference in thickness is accumulated between the part where the internal electrode is formed and the surrounding part where the internal electrode is not formed, and a large stress concentration occurs at the end of the internal electrode. . This stress concentration during thermal decomposition or sintering of the binder causes delamination and cracks.

このような問題は、グリーンシートの膜厚が薄くて内部
電極の塗布厚みがグリーンシートの厚みに対して無視で
きない場合に発生する。また、このような場合でも内部
電極の枚数が10〜20枚と少ないときは上下の保護層
部分において前記の応力が緩和され、上記のような不都
合は発生しない。
Such a problem occurs when the thickness of the green sheet is so thin that the coating thickness of the internal electrode cannot be ignored relative to the thickness of the green sheet. Further, even in such a case, when the number of internal electrodes is small, such as 10 to 20, the stress described above is relaxed in the upper and lower protective layer portions, and the above-mentioned inconvenience does not occur.

この場合は、グリーンシー1〜1枚当たり2〜3mの厚
みの差が素子全体で高々20〜60脚であり、通常、片
側で100脚以上、上下合わせて200珈以上設けられ
る保護膜部においてこの厚みの差が吸収されるためであ
る。
In this case, the difference in thickness of 2 to 3 meters per green sea sheet is at most 20 to 60 legs for the entire element, and usually in the protective film part where there are more than 100 legs on one side and more than 200 legs in total on the top and bottom. This is because this difference in thickness is absorbed.

本発明は以上述べたような従来の事情に鑑みてなされた
もので、内部電極間距離が短く、かつ多数積層されてい
るため単位体積当たりの容量が大きく、かつデラミネー
ション、タラツクなどの欠陥のない信頼性に優れた積層
セラミックコンデンサを提供することを目的とする。
The present invention has been made in view of the conventional circumstances as described above, and has a short distance between internal electrodes and a large number of laminated layers, so it has a large capacity per unit volume and is free from defects such as delamination and tartar. The purpose is to provide a multilayer ceramic capacitor with excellent reliability.

[課題を解決するための手段] 本発明は、誘電体セラミック層と内部電極を交互に積層
してなる積層セラミックコンデンサにおいて、誘電体セ
ラミック層が電気容量に寄与しない保護層と電気容量に
寄与する活性層からなり、かつ該活性層が1つまたは複
数の厚さ100柳以上の保護層により2つ以上の部分に
分割されていることを特徴とする積層セラミックコンデ
ンサである。
[Means for Solving the Problems] The present invention provides a multilayer ceramic capacitor in which dielectric ceramic layers and internal electrodes are alternately laminated, in which the dielectric ceramic layers do not contribute to the capacitance and the protective layer contributes to the capacitance. A multilayer ceramic capacitor comprising an active layer, the active layer being divided into two or more parts by one or more protective layers having a thickness of 100 yen or more.

[作用] 誘電体セラミック層として、内部電極の形成されたグリ
ーンシートを多数枚積層すると、上述したように、内部
電極が形成された箇所と形成されていない箇所とでその
厚みの差により、応力集中が発生し、デラミネーション
やクラックの原因となる。
[Function] When a large number of green sheets with internal electrodes are laminated as a dielectric ceramic layer, stress is generated due to the difference in thickness between areas where internal electrodes are formed and areas where they are not formed, as described above. Concentration occurs, causing delamination and cracks.

本発明においては、内部電極を形成して電気容量に寄与
すべき誘電体セラミック層、即ち、活性層を2つ以上に
分割し、その間に厚さ100 /!m以上の保護層を設
ける。このようにすると、内部電極の枚数がそれほど多
くない状態で上下の保護層により応力がそれぞれ緩和さ
れつつ、全体としては多数枚の内部電極を積層すること
ができる。このため、単位体積当たりの電気容量が大き
く、かっ製造工程中のデラミネーションやクラックのな
い信頼性の高い積層セラミックコンデンサが得られる。
In the present invention, the dielectric ceramic layer that forms the internal electrode and contributes to the capacitance, that is, the active layer, is divided into two or more parts with a thickness of 100/! A protective layer of m or more is provided. In this way, even if the number of internal electrodes is not so large, stress can be relaxed by the upper and lower protective layers, and a large number of internal electrodes can be laminated as a whole. Therefore, a highly reliable multilayer ceramic capacitor with a large capacitance per unit volume and no delamination or cracking during the manufacturing process can be obtained.

[実施例] 以下、本発明の実施例について、詳細に説明する。[Example] Examples of the present invention will be described in detail below.

マグネシウム・タングステン酸鉛(Pb(Mに11/2
 Wl/2 ) 03 ) 、ニッケル・ニオブ酸鉛(
Pb(N ! 173 N b273 > 03 > 
、チタン酸鉛(PbTi03>からなる三成分系誘電体
材料の予焼粉末を有機バインダ、有機溶剤、有機可塑剤
と混合し、泥漿を作製した。この泥漿をドクタブレード
法によりポリエステル製ベースフィルム上にキャスティ
ング、乾燥し、15胸の厚さのグリーンシートを作製し
た。次いでポリエステル製ベースフィルムから剥離し、
所定の形状に切断した。得られた切断済みグリーンシー
トの一部に内部電極材料として銀パラジウムペース1〜
を厚さ3脚でスクリーン印刷した。
Magnesium lead tungstate (Pb (11/2 to M)
Wl/2) 03), Nickel lead niobate (
Pb(N! 173 N b273 > 03 >
A pre-fired powder of a three-component dielectric material consisting of lead titanate (PbTi03) was mixed with an organic binder, an organic solvent, and an organic plasticizer to prepare a slurry. This slurry was coated on a polyester base film by a doctor blade method. A green sheet with a thickness of 15 mm was prepared by casting and drying.Then, it was peeled off from the polyester base film.
It was cut into a predetermined shape. A part of the obtained cut green sheet is coated with silver palladium paste 1 to 1 as an internal electrode material.
was screen printed with a thickness of 3 feet.

これらのグリーンシートを用い、表−1に示すような所
定枚数および順序で積層、熱圧着して一体化し、実施例
2種類、比較例2種類の合計4種類の成形体を作製した
。得られたそれぞれのグリーンシート戒形体をダイシン
グソーによりチップ形状に切断し、生チップを得た。
Using these green sheets, they were laminated in a predetermined number and order as shown in Table 1 and integrated by thermocompression bonding to produce a total of four types of molded bodies, two types of Examples and two types of Comparative Examples. Each of the obtained green sheet shaped bodies was cut into chip shapes using a dicing saw to obtain raw chips.

第1図はこのようにして作製した本発明の実施例の積層
セラミックコンデンサ用生チップの幅方向の断面図であ
る。図中、第1図(a)は実施例1に相当するもので、
活性層が上部活性層2と下部活性層4に分けられ、その
間に、中間保護層3が形成されている。また、第1図(
b)は実施例2に相当するもので、活性層が上部活性層
2、中間活性層7および下部活性層4に分けられ、その
間に、中間保護層3a、3bが形成されている。
FIG. 1 is a cross-sectional view in the width direction of a raw chip for a multilayer ceramic capacitor according to an embodiment of the present invention manufactured in this manner. In the figure, FIG. 1(a) corresponds to Example 1,
The active layer is divided into an upper active layer 2 and a lower active layer 4, and an intermediate protective layer 3 is formed between them. Also, Figure 1 (
b) corresponds to Example 2, in which the active layer is divided into an upper active layer 2, an intermediate active layer 7, and a lower active layer 4, with intermediate protective layers 3a and 3b formed therebetween.

第2図に同じく比較のため作製した比較例の積層セラミ
ックコンデンサ用生チップの幅方向の断面図を示す。第
2図(a)は比較例1の場合、第2図(b)は比較例2
の場合を示す。
FIG. 2 shows a cross-sectional view in the width direction of a raw chip for a multilayer ceramic capacitor of a comparative example, which was also produced for comparison. Figure 2 (a) is Comparative Example 1, Figure 2 (b) is Comparative Example 2.
The case is shown below.

これらの生チップを600℃で8時間、空気中で処理し
て有機バインダを熱分解・除去し、外観検査によりデラ
ミネーションの発生したチップの個数を数えた。次に、
空気中、950℃で1時間焼成して得た焼結チップを切
断し、内部を観察してクラックの発生数を調べた。表−
1に観察結果を示す。従来の構造の積層セラミックコン
デンサにおいては、内部電極の数が多くなるとバインダ
熱分解工程あるいは焼成工程においてデラミネーション
やクラックが高い確率で発生し、内部にクランクが存在
する場合には耐電圧が低下し、耐湿試験中に抵抗の低下
、ショートなどの特性不良が発生することが知られてい
る。それに対し、本発明の構造により1つ以上の厚さ1
001IIn以上の保護層を活性層の中間に設けた場合
には、内部電極の厚みの積算による積層体内部の応力が
効果的に緩和され、デラミネーションやクラックの発生
が全く見られないことがわかる。
These raw chips were treated in air at 600° C. for 8 hours to thermally decompose and remove the organic binder, and the number of chips with delamination was counted by visual inspection. next,
The sintered chips obtained by firing in air at 950° C. for 1 hour were cut, and the inside was observed to determine the number of cracks. Table -
1 shows the observation results. In multilayer ceramic capacitors with a conventional structure, when the number of internal electrodes increases, there is a high probability that delamination and cracks will occur during the binder pyrolysis process or firing process, and if there is a crank inside, the withstand voltage will decrease. It is known that characteristic defects such as a decrease in resistance and short circuits occur during moisture resistance tests. In contrast, the structure of the present invention provides one or more thicknesses of 1
It can be seen that when a protective layer of 001IIn or more is provided between the active layers, the stress inside the laminate due to the cumulative thickness of the internal electrodes is effectively alleviated, and no delamination or cracks occur at all. .

(以下余白〉 [発明の効果] 以上説明したように、本発明の積層セラミックコンデン
ザは、単位体積当たりの電気容量が大きく、かつ製造工
程中にデラミネーションやクラックが発生しないため、
製造上問題がなく、かつ高い信頼性が期待できる。
(Margins below) [Effects of the Invention] As explained above, the multilayer ceramic capacitor of the present invention has a large capacitance per unit volume, and no delamination or cracks occur during the manufacturing process.
There are no manufacturing problems and high reliability can be expected.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による積層セラミックコンデンサ用生チ
ップの一例の幅方向の断面図、第2図は比較のため作製
した積層セラミックコンデンサ用生チップの一例の幅方
向の断面図、第3図は通常の積層セラミックチップコン
デンサの斜視図(a)、一対の内部電極の素子底面への
投影図(b)、長さ方向の断面図(C)および幅方向の
断面図(d)をそれぞれ示す。 1・・・上部保護層   2・・・上部活性層3.3a
、3b・・・中間保護層 4・・・下部活性層   5・・・下部保護層7・・・
中間活性層   9・・・活性層10a 、 10b・
・・外部電極 0 11・・・誘電体セラミック 2a 2b ・・・内部電極
FIG. 1 is a cross-sectional view in the width direction of an example of a raw chip for a multilayer ceramic capacitor according to the present invention, FIG. 2 is a cross-sectional view in the width direction of an example of a raw chip for a multilayer ceramic capacitor manufactured for comparison, and FIG. A perspective view (a) of a typical multilayer ceramic chip capacitor, a projection view (b) of a pair of internal electrodes onto the bottom surface of the element, a longitudinal cross-sectional view (C), and a cross-sectional view (d) in the width direction are shown, respectively. 1... Upper protective layer 2... Upper active layer 3.3a
, 3b... Intermediate protective layer 4... Lower active layer 5... Lower protective layer 7...
Intermediate active layer 9...active layer 10a, 10b...
...External electrode 0 11...Dielectric ceramic 2a 2b...Internal electrode

Claims (1)

【特許請求の範囲】[Claims] (1) 誘電体セラミック層と内部電極を交互に積層し
てなる積層セラミックコンデンサにおいて、誘電体セラ
ミック層が電気容量に寄与しない保護層と電気容量に寄
与する活性層からなり、かつ該活性層が1つまたは複数
の厚さ100μm以上の保護層により2つ以上の部分に
分割されていることを特徴とする積層セラミックコンデ
ンサ。
(1) In a multilayer ceramic capacitor formed by alternately laminating dielectric ceramic layers and internal electrodes, the dielectric ceramic layer consists of a protective layer that does not contribute to capacitance and an active layer that contributes to capacitance, and the active layer A multilayer ceramic capacitor characterized by being divided into two or more parts by one or more protective layers having a thickness of 100 μm or more.
JP1479290A 1990-01-26 1990-01-26 Laminated ceramic capacitor Pending JPH03220711A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1479290A JPH03220711A (en) 1990-01-26 1990-01-26 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1479290A JPH03220711A (en) 1990-01-26 1990-01-26 Laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH03220711A true JPH03220711A (en) 1991-09-27

Family

ID=11870907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1479290A Pending JPH03220711A (en) 1990-01-26 1990-01-26 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH03220711A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212527A (en) * 2009-05-22 2009-09-17 Murata Mfg Co Ltd Method of manufacturing multilayer ceramic electronic capacitor
JP2010153935A (en) * 2010-04-09 2010-07-08 Murata Mfg Co Ltd Multilayered capacitor
JP2010177696A (en) * 2010-04-09 2010-08-12 Murata Mfg Co Ltd Multilayer capacitor
JP2013004549A (en) * 2011-06-13 2013-01-07 Ngk Spark Plug Co Ltd Electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212527A (en) * 2009-05-22 2009-09-17 Murata Mfg Co Ltd Method of manufacturing multilayer ceramic electronic capacitor
JP2010153935A (en) * 2010-04-09 2010-07-08 Murata Mfg Co Ltd Multilayered capacitor
JP2010177696A (en) * 2010-04-09 2010-08-12 Murata Mfg Co Ltd Multilayer capacitor
JP2013004549A (en) * 2011-06-13 2013-01-07 Ngk Spark Plug Co Ltd Electronic component

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