JPH0322087A - Logic simulator - Google Patents
Logic simulatorInfo
- Publication number
- JPH0322087A JPH0322087A JP1157709A JP15770989A JPH0322087A JP H0322087 A JPH0322087 A JP H0322087A JP 1157709 A JP1157709 A JP 1157709A JP 15770989 A JP15770989 A JP 15770989A JP H0322087 A JPH0322087 A JP H0322087A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- logic
- signal lines
- values
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 claims abstract description 11
- 238000004088 simulation Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 235000019557 luminance Nutrition 0.000 abstract 3
- 239000003086 colorant Substances 0.000 abstract 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は論理シミュレータに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a logic simulator.
従来の論理シミュレー夕は、人出力端子と一部の観測点
の信号の値を時刻と信号値との組合せで第4図の表示図
のようなパターンあるいは論理値により表現していた。In conventional logic simulation systems, the values of signals at human output terminals and some observation points are expressed by combinations of time and signal values in a pattern or logical values as shown in the display diagram of FIG. 4.
上述した従来の論理シミュレータは、信号値の変化と論
理回路図が同時に見れないため、論理の間違っている箇
所を発見するのに時間がかかる点と、テストパターンあ
るいは論理値とそれらが出現する論理回路図上の位置と
の照合が容易でない点の二つの欠点があった。The conventional logic simulators mentioned above cannot see changes in signal values and logic circuit diagrams at the same time, so it takes time to discover logic errors, and test patterns or logic values and the logic in which they appear There were two drawbacks: it was not easy to check the position on the circuit diagram.
本発明の信号値識別表示式論理シミュレー夕は、論理値
を算出する機構と、論理値を信号線の色あるいは、輝度
のデータに変換する機構および信号線を画面上に表示す
る機構とを有して構或されている。The signal value identification and display type logic simulator of the present invention has a mechanism for calculating logical values, a mechanism for converting the logical values into signal line color or brightness data, and a mechanism for displaying the signal lines on the screen. It is structured as follows.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一例のブロック図である。FIG. 1 is a block diagram of an example of the present invention.
信号値識別表示式の論理シミュレータは、全信号線の信
号値の算出の機構1、信号値から信号線の色あるいは輝
度データへの変換機構2、信号線を画面上に表示する機
構3を有している。The signal value identification and display type logic simulator has a mechanism 1 for calculating the signal values of all signal lines, a mechanism 2 for converting the signal values into signal line color or luminance data, and a mechanism 3 for displaying the signal lines on the screen. are doing.
第2図は第l図のブロックの表示3のディスプレイ画面
上に描かれたシミュレーションの結果の表示図である。FIG. 2 is a display diagram of the simulation results drawn on the display screen of block display 3 in FIG.
入力端INI,IN2より同時に入力された信号が出力
側の○UTI,OUT2では遅延のために、同時には信
号が得られていない事がわかる。It can be seen that the signals inputted at the same time from the input terminals INI and IN2 are not obtained at the same time at the output side UTI and OUT2 due to a delay.
第3図は第4図の従来の論理シミコレータの表示図に対
応する本発明による表示図である。FIG. 3 is a display diagram according to the present invention corresponding to the display diagram of the conventional logic simulator of FIG. 4.
第4図の出力結果の画面では論理回路図とタイミングチ
ャートとの比較を要したが、第3回の本実施例では、時
間とともに信号線の色あるいは輝度を変えるので、簡単
にしかも確実に信号値を調べる事ができる。On the output result screen in Figure 4, it was necessary to compare the logic circuit diagram and the timing chart, but in this third embodiment, the color or brightness of the signal line changes over time, so it is easy and reliable to compare the signal line. You can check the value.
以上説明したように本発明は、全ての信号線の信号値を
その信号の色や輝度で表示する事で、論理が間違ってい
る点を可視的に早く発見でき、タイミングがずれている
所に遅延素子を容易に挿入することが可能な点と、信号
線自身で信号値を表現するので信号線とその上で変化す
る出力パターンとの対応を取る必要がない点の以上2点
で、論理シミュレーション工程の時間の短縮と作業を簡
略化できる効果がある。As explained above, the present invention displays the signal values of all signal lines using the color and brightness of the signal, so that it is possible to quickly and visually detect faulty logic, and to correct timing deviations. The above two points are that delay elements can be easily inserted, and since the signal value is expressed by the signal line itself, there is no need to correspond between the signal line and the output pattern that changes on it. This has the effect of shortening the simulation process time and simplifying the work.
【図面の簡単な説明】
第l図は本発明の一実施例のブロック図、第2図及び第
3図は第l図の表示図、第4図は従来の論理シミコレー
タの一例の表示図である。
l・・・・・・全信号線の信号値の算出、2・・・・・
・信号値から信号線の色あるいは輝度データへの変換、
3・・・・・・信号線を画面上に表示。[Brief Description of the Drawings] Figure 1 is a block diagram of an embodiment of the present invention, Figures 2 and 3 are illustrations of Figure 1, and Figure 4 is an illustration of an example of a conventional logic simulator. be. l...Calculation of signal values of all signal lines, 2...
・Conversion from signal value to signal line color or brightness data,
3...Display the signal line on the screen.
Claims (1)
化させてディスプレイ画面に信号値識別を表示すること
を特徴とする論理シミュレータ。A logic simulator characterized by displaying signal value identification on a display screen by changing the color, brightness, etc. of signal lines in a logic circuit diagram depending on the signal value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157709A JPH0322087A (en) | 1989-06-19 | 1989-06-19 | Logic simulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1157709A JPH0322087A (en) | 1989-06-19 | 1989-06-19 | Logic simulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322087A true JPH0322087A (en) | 1991-01-30 |
Family
ID=15655660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1157709A Pending JPH0322087A (en) | 1989-06-19 | 1989-06-19 | Logic simulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322087A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007284824A (en) * | 2006-04-18 | 2007-11-01 | Nisshinbo Ind Inc | Knitted fabric containing elastic fibers |
| JP2011191921A (en) * | 2010-03-12 | 2011-09-29 | Fujitsu Ltd | Program, apparatus and method for supporting design |
-
1989
- 1989-06-19 JP JP1157709A patent/JPH0322087A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007284824A (en) * | 2006-04-18 | 2007-11-01 | Nisshinbo Ind Inc | Knitted fabric containing elastic fibers |
| JP2011191921A (en) * | 2010-03-12 | 2011-09-29 | Fujitsu Ltd | Program, apparatus and method for supporting design |
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