JPH03222199A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To confirm the quality of plural bits data processed in parallel through a small number of output terminals by exclusive-OR-processing the prescribed bit of the plural bits data processed in parallel, and outputting it to a required output terminal. CONSTITUTION:The same data DI1 to DIn of the prescribed bit of the plural bits data processed in parallel is processed by an exclusive OR circuit 1, and is outputted to the output terminal TO1 through a transfer circuit 2 made conductive by a test signal TST. At that time, each output circuit 41 to 4n is deactivated through a data output control circuit 3 to respond to the signal TST, and the data DI1 to DIn are not outputted to the terminals TO1 to TOn. Accordingly, the data of 16 bits or 32 bits, etc., can be processed by an 8-bit test circuit, and the quality of the plural bits data processed in parallel can be confirmed though a small number of the terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory configured to process multiple bits of data in parallel.

[Conventional technology]

Conventionally, this type of semiconductor memory has been mainstream up to 8 bits, and multi-bit systems of 9 bits or more are currently being produced in small numbers.

One of the factors that determines the number of bits of a semiconductor memory is the bit matching with a microcomputer, and currently the mainstream of microcomputers has already shifted to 16 bits. Therefore, it is assumed that semiconductor memories will soon shift to 16-bit or 32-bit multi-bit systems.

For multi-bit semiconductor memory of 9 bits or more, it is a good idea to manufacture data input/output terminals according to the number of bits of the microcomputer. For example, a 16-bit microcomputer has terminals for data input and output. Each terminal is provided with 16 terminals.

[Problem to be solved by the invention]

In the conventional semiconductor memory mentioned above, the number of data input/output terminals is determined according to the number of bits of the microcomputer, and the mainstream of microcomputers has changed from 8 bits to 16 bits, so it is currently in use. There is a problem in that the test equipment for 8-bit semiconductor memory cannot be used, and a new test equipment for 16-bit semiconductor memory must be installed, which increases manufacturing costs.

The purpose of the present invention is to
It is an object of the present invention to provide a semiconductor memory that can be tested using an existing 8-bit test device and that can suppress an increase in manufacturing costs.

[Means to solve the problem]

The semiconductor memory of the present invention has the same number of output terminals as the number of bits of the data for outputting parallel-processed multi-bit data, and exclusive use of a predetermined plurality of bits of the multi-bit data. an exclusive OR circuit that performs logical OR processing; a transfer circuit that transmits output data of the exclusive OR circuit to a predetermined output terminal of the plurality of output terminals in accordance with a test signal; and a plurality of output circuits whose activation is controlled by the output control signal and which transmits the plurality of bits of data to the corresponding output terminals.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment performs exclusive OR processing of the n-bit data with the same number of output terminals TOI to Ton as the number of bits of the data for correspondingly outputting the n-bit data processed in parallel. It includes an exclusive OR circuit 1, an inverter and a transfer gate, and a test signal TS.
A transfer circuit 2 transmits the output data of the exclusive OR circuit 1 to a predetermined output terminal TO1 of the output terminals TOI to Ton according to T, and a data output control signal DOE according to the test signal TST. Output control circuit 3
and a plurality of outputs, each of which is provided with data amplifiers 51 to 5n and output buffers 61 to 6n, and whose activation is controlled by an output control signal DOE and which transmits multiple bits of data to the corresponding output terminals (To1 to Ton), respectively. The configuration includes circuits 41 to 4n.

Next, the operation of this embodiment will be explained.

First, parallel-processed n-bit data DII to DIn
is processed by the exclusive OR circuit 1.

Next, when the signal TST is at a low level, the transfer circuit 2 is turned off and the output data of the exclusive OR circuit 1 is not transmitted to the output terminal TO1, and the data output control circuit 3 transmits the output control signal DOE. The output circuits 41 to 4n are activated by setting it to a high level. Therefore, the normal operating state is reached, and the parallel-processed n-bit data D11 to DIn are output to the output terminals TO1 to Ton via the output circuits 41 to 4n.
Communicate to.

Next, when the test signal TST is at a high level, the transfer circuit 2 is turned on and transmits the output data of the exclusive OR circuit 1 to the output terminal TOI. At this time, the output control signal DOE output from the data output control circuit 3 becomes low level, the output circuits 41 to 4n become inactive, and therefore the data D11 to D to the output terminals TO1 to TOn are output.
The transmission of In is cut.

Therefore, for example, by writing each bit of data as the same logic level in advance, reading it out, passing it through this circuit and checking the level of the output terminal TO1, it is possible to check whether the writing and reading operations of this semiconductor memory are good or not. can do.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, n-bit data D11 is processed in parallel.
~ D engineering n, DI 1 ~ DIk, DI (k+1) ~ D
In is divided into two groups, and exclusive OR circuits LA and IB are provided which perform exclusive OR processing on these two groups, respectively, and these exclusive OR circuits IA and I
The output data of B is transmitted to output terminals TOI and TO2 in correspondence with each other.

This embodiment has the advantage that, if there is a malfunction, the range of the portion where the malfunction has occurred can be limited to a narrow range. This advantage increases as the number of groups increases.

〔Effect of the invention〕

As described above, the present invention provides at least one exclusive OR circuit that performs exclusive OR processing on predetermined multiple bits of multiple bits of data processed in parallel, and transmits this output to a predetermined output terminal. With this configuration, it is possible to determine the quality of multiple bits of data subjected to exclusive OR processing based on the level of this output terminal.
The quality of parallel-processed data can be checked using a small number of output terminals, so the conventional 8-bit test equipment can be used for multi-bit semiconductor memories such as 16-bit and 32-bit. This has the effect of suppressing an increase in manufacturing costs.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing first and second embodiments of the present invention, respectively. 1, LA, 1B...exclusive OR circuit, 2.2A...
・Transfer circuit, 3...Data output control circuit, 4
1 to 4n...output circuit, 51 to 5n...data amplifier, 61 to 6n...output buffer, TOI to Ton.
...Output terminal.

Claims (1)

[Claims] The number of output terminals is the same as the number of bits of the data for outputting multiple bits of data processed in parallel, and the exclusive OR processing of a predetermined multiple bits of the multiple bits of data is performed. a transfer circuit that transmits output data of the exclusive OR circuit to a predetermined output terminal of the plurality of output terminals in response to a test signal; and a transfer circuit that transmits an output control signal in response to the test signal. A semiconductor memory comprising: a data output control circuit for outputting data; and a plurality of output circuits whose activation is controlled by the output control signal and transmits the plurality of bits of data to the corresponding output terminals.