JPH03222333A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electrical short-circuit between wirings or a leakage current from being generated by a method wherein an exposed multilayer film is etched using an etching method to act selectively on the exposed multilayer film and the side surfaces of first conductive films are made to retrogress to the inner side more than second conductive films. CONSTITUTION:An anisotropic etching treatment is performed on a multilayer film, the multilayer film is left only on prescribed regions and wirings 5 and 6 consisting of the multilayer film, whose whole side surfaces are exposed, are formed. Subsequently, the side surfaces of first conductive films 3 are etched for a prescribed time using an etching method to act selectively on the films 3 and are made to retrogress to the inner side more than second conductive films 4. Then, an alloying heat treatment is performed at 430 deg.C for 30 minutes and after that, a passivation film 7 consisting of Si3N4 is deposited by a plasma CVD method in a film thickness of 10000Angstrom and moreover, an annealing treatment is performed at 430 deg.C for 30 minutes to complete a wiring structure.

Description

DETAILED DESCRIPTION OF THE INVENTION B) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device that prevents electrical short-circuits or leakage current between wiring lines due to lateral hillocks. Regarding the manufacturing method.

(Background Art) In recent years, as semiconductor integrated circuits have become more highly integrated, the dimensions of interconnections have become smaller and finer.

For example, the minimum width and spacing of wiring used in a 1 megabit dynamic RAM is approximately 1 μm.

By the way, in general wiring, aluminum and aluminum alloys (Al-5i, Al-Cu-5i alloy) are mainly used in consideration of the uniformity and reproducibility of wiring films on semiconductor substrates.
is used. Alternatively, considering electromigration and stress migration resistance, a laminated film (Ti
W/Al-Cu-5i/Tiw, A1-5i/Ti
N, etc.) are used.

This A1 or A1 alloy is heat treated at approximately 400°C or higher after wiring formation to form hillocks (A1 due to crystallization of AI).
1 protrusion) occurs. In particular, hillocks (referred to as lateral hillocks) occur on the side walls of wiring films. ), the wiring spacing becomes narrower, resulting in a problem of leakage current or electrical short-circuiting between the wirings.

In this regard, conventional techniques include a method of suppressing hillocks by ion-implanting arsenic or nitrogen, etc. into the surface of the wiring film, a method of providing the above-mentioned barrier material (TiW, TiN, etc.) on the upper layer of the wiring film, or a method of suppressing hillocks by ion-implanting arsenic or nitrogen into the surface of the wiring film; heat treatment temperature of 400°
There is a way to lower it below C.

(c) Problems to be Solved by the Invention The former two methods according to the above-mentioned prior art are methods that mainly act on the upper surface of the wiring layer, and prevent hillocks (referred to as vertical hillocks) that occur on the upper surface of the wiring film. ), but it has little effect on horizontal hillocks.

In addition, as for the method of lowering the heat treatment temperature, although it has a certain effect on lateral hillocks, the degree of freedom in heat treatment temperature such as alloying heat treatment after wiring formation and passivation film annealing is reduced, and There was a drawback that heat treatment was not possible.

The present invention was created in view of the problems of the prior art, and is capable of reducing electrical shorts or leakage currents between interconnects due to lateral hillocks without reducing the degree of freedom in heat treatment temperature after interconnect formation. An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents the above problems.

(2) Means for Solving the Problems In the method for manufacturing a semiconductor device of the present invention, in the step of forming wiring on a semiconductor substrate, as shown in FIGS. A step of forming a multilayer film by alternately stacking a first conductive film and a second conductive film made of a barrier metal material, and performing an anisotropic etching treatment on the multilayer film so that only predetermined areas are etched. a step of leaving the multilayer film and exposing all sides of the multilayer film; etching using an etching method that selectively acts on the multilayer film exposed in the step, and etching the side surfaces of the first conductive film; The method is characterized in that it includes a step of retreating to the inside of the second conductive film, and by such a manufacturing method, a wiring made of a multilayer film is formed.

(E) Effect According to the present invention, the side surface of the first conductive film has a step of retreating from the second conductive film, and the wiring interval when lateral hillocks occur in the first conductive film due to heat treatment. can have a large margin.

Therefore, by controlling the amount of retreat according to the etching conditions according to the size of the hillock that occurs, it is possible to ensure the wiring spacing at a predetermined distance or more and prevent electrical shorts or leakage current between the wirings.

(F) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, an insulating film (2) is formed on a semiconductor substrate (1), followed by a first conductive film (3) made of Al-5i and a second conductive film (3) made of IiN. A multilayer film is formed by alternately depositing 2,000 conductive films (4) each to a thickness of 100 OA.

In this example, the first conductive film <3> has two layers, and the second conductive film <3> has two layers.
Although the conductive film (4) has three layers, it goes without saying that the number of layers may be increased or decreased.

Next, as shown in FIG. 1B, the multilayer film is subjected to an anisotropic etching process (BCl3, C12,5iC14 plasma, etc.) to leave the multilayer film only in predetermined areas and to remove the entire multilayer film. Wiring with exposed sides (5), (
6) Form.

Subsequently, as shown in FIG. 1C, the first conductive film (3
) using an etching method that selectively acts on (for example, a wet etching method using a hot sulfuric acid aqueous solution),
The side surface of the first conductive film (3) is etched for a predetermined period of time to retreat further inward than the second conductive film (4).

Next, as shown in the first diagram, alloying heat treatment was performed at 430°C.
5i by plasma CVD method.
Passivation film made of sNa (7〉 to 10,000
The wiring structure is completed by depositing the film to a normal thickness and then performing N2 annealing at 430° C. for 30 minutes.

According to such a manufacturing method, even if lateral hillocks (8) occur in the first conductive film (3) during the alloying heat treatment and the annealing process of the hypopassivation film, the first conductive film (3) Since the side surface 3) is set back inward from the second conductive film (4), the margin for the wiring spacing can be increased.

Actually, the size of hillocks that will occur can be predicted in advance by the heat treatment temperature, so by controlling the amount of retraction described above and the processing time according to the predicted size of hillocks, the wiring spacing can be kept above a certain level. Secure and wire (5
) and (6) can be prevented from electrical short or leakage current.

The second conductive layer (4) made of TiN is formed on the top layer of the multilayer film to prevent vertical hillocks, and is formed on the bottom layer to act as a barrier layer against the diffusion layer. It is something to do.

In addition, by forming at least one second conductive layer (4) in the middle layer of the multilayer film, the first conductive layer (3) is formed.
) can be made into a thin film of about 2000A or less, which has the effect of reducing the size of the lateral hillock itself compared to the conventional one.

(g) As described in detail, according to the present invention, even if hillocks occur due to heat treatment after wiring formation, the wiring spacing can be maintained at a predetermined distance or more, thereby preventing electrical shorts or leaks between wirings. It is possible to manufacture semiconductor devices with high yield and high reliability without any flow.

[Brief explanation of drawings]

FIGS. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Claims (4)

[Claims] (1) After forming an insulating film on a semiconductor substrate, a first conductive film and a second conductive film made of a different material from the first conductive film are formed on the insulating film.
a first step of forming a multilayer film by alternately stacking conductive layers; and performing an anisotropic etching treatment on the multilayer film to leave the multilayer film only in predetermined areas; a second step of exposing all side surfaces; etching all the side surfaces of the multilayer film exposed in the step using an etching method that acts selectively on the first conductive film; A method for manufacturing a semiconductor device, comprising: a third step of recessing a side surface of the film further inward than the second conductive film. (2) The first conductive film is made of aluminum or an aluminum alloy, and the second conductive film is made of TiN, Ti.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is made of W or Mo. (3) The semiconductor according to claim 1 or claim 2, characterized in that, in the first step, the second conductive layer is formed on the uppermost layer or the lowermost layer of the multilayer film. Method of manufacturing the device. (4) In the first step, at least one layer of the second conductive film is formed in the middle layer of the multilayer film. A method for manufacturing a semiconductor device according to section 1.