JPH03225904A - Applying method of conductive paste onto multilayer chip - Google Patents

Applying method of conductive paste onto multilayer chip

Info

Publication number
JPH03225904A
JPH03225904A JP2021825A JP2182590A JPH03225904A JP H03225904 A JPH03225904 A JP H03225904A JP 2021825 A JP2021825 A JP 2021825A JP 2182590 A JP2182590 A JP 2182590A JP H03225904 A JPH03225904 A JP H03225904A
Authority
JP
Japan
Prior art keywords
conductive paste
grooves
cutting
laminate
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021825A
Other languages
Japanese (ja)
Inventor
Akira Takahashi
彰 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2021825A priority Critical patent/JPH03225904A/en
Publication of JPH03225904A publication Critical patent/JPH03225904A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To enable efficient and reliable application of conductive paste for forming an outer electrode even onto a small multilayer chip by cutting grooves, for separating into individual ships, into a laminate and then filling the grooves with the conductive paste thereafter cutting the laminate in the center of the conductive paste. CONSTITUTION:Grooves 11, 11... are cut, by means of a diamond blade 30, into a laminate 10 having rear surface being held by an adhesive tape 20. Conductive paste 12 is then applied on the cutting grooves 11, 11... and filled, therein. The conductive paste 12 is then baked and hardened. Cutting grooves 13, 13... are then made, by means of the diamond blade, in the center of the conductive paste 12. Consequently, the conductive paste 12 filled in the initially cut grooves 11 is separated from the opposite sides of the grooves 11, 11 by means of the later cut grooves 13. Thereafter, grooves 14, 14... are cut to separate the laminate into individual chips 50, 50.... According to this method, the conductive paste 12, 12 is applied accurately and simultaneously onto the opposite ends of a large number of multilayer chips 50, 50... and outer electrodes 15, 15 are formed.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、セラミックグリーンシート等の絶縁シートを
積層してなる積層電子部品の製造方法に関し、特に、積
層電子部品を構成する積層チップの端面に導電ペースト
を塗布する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a laminated electronic component formed by laminating insulating sheets such as ceramic green sheets, and in particular, to a method for manufacturing a laminated electronic component formed by laminating insulating sheets such as ceramic green sheets, and in particular to a method for manufacturing a laminated electronic component formed by laminating insulating sheets such as ceramic green sheets. The present invention relates to a method of applying conductive paste to.

[従来の技術] 積層コンデンサや積層コイル等の、積層電子部品は、表
面に電極パターンを形成したセラミックグリーンシート
等の絶縁シートを積層した積層体を構成し、この積層体
を個々の積層チップに切断、分離すると共に、この積層
チップに外部電極を形成することにより製造される。
[Prior Art] Multilayer electronic components such as multilayer capacitors and multilayer coils are composed of a laminate made of insulating sheets such as ceramic green sheets with electrode patterns formed on their surfaces, and this laminate is assembled into individual multilayer chips. It is manufactured by cutting, separating, and forming external electrodes on this stacked chip.

この場合従来では、以下に述べる方法で、外部電極を形
成するための導電ペーストが積層チップの両端に塗布さ
れていた。すなわち、第4図(a)に示す様に、複数の
孔1.1・・・を育するゴム等の弾性体2.2を、アル
ミ製等の枠体3に取り付けた治具4を用意する。そして
、同図(b)に示すように、個々に切断された積層チッ
プ5をこの弾性体2.2の複数の孔1.1・・・に挿入
し、導電ペーストを塗布しようとする端部を所定の高さ
に揃える。そして、これら挿入固定された積層チップ5
の端部を、ペースト槽6の導電ペースト7に浸漬して導
電ペーストを塗布する。さらに、積層チップ5の他方の
端部にも導電ペーストを塗布する場合は、前記積層チッ
プ5を前記ゴムプレート4の反対側に押− し出し、第4図(b)に破線で示すように、積層チップ
5の他端を突出させる。その後、同様にしてこの他端側
に導電ペースト7を塗布する。
In this case, conventionally, a conductive paste for forming external electrodes was applied to both ends of the laminated chip by the method described below. That is, as shown in FIG. 4(a), a jig 4 is prepared in which an elastic body 2.2 made of rubber or the like for growing a plurality of holes 1.1 is attached to a frame 3 made of aluminum or the like. do. Then, as shown in FIG. 2B, the individually cut laminated chips 5 are inserted into the plurality of holes 1.1 of this elastic body 2.2, and the ends on which the conductive paste is to be applied are inserted. Align the height to the specified height. Then, these inserted and fixed laminated chips 5
The end portion of the conductive paste is dipped into the conductive paste 7 in the paste tank 6 to apply the conductive paste. Furthermore, if the conductive paste is to be applied to the other end of the laminated chip 5, the laminated chip 5 is pushed out to the opposite side of the rubber plate 4 as shown by the broken line in FIG. 4(b). , the other end of the laminated chip 5 is made to protrude. Thereafter, conductive paste 7 is applied to the other end in the same manner.

そして、これら塗布された導電ペーストを焼き付けるこ
とにより、外部電極が形成される。
Then, external electrodes are formed by baking these applied conductive pastes.

[発明が解決しようとする課題] しかしながら、前記の従来技術による積層チップの導電
ペースト塗布方法では、前記弾性体2.2の複数の孔1
11・・・に挿入して、積層チップ5の先端の突出する
高さを一定に揃える、いわゆるレベリングが難しく、そ
のため、先端に付着する導電ペーストの量が不均一とな
ってしまう。特に、小形の積層チップ5は、前記の様な
ゴムプレート4の孔1. 1・・・に確実に保持するこ
とがきわめて困難ある。このため、寸法称呼1608と
いうような、長さ1. 6mm5幅0.8mmの小さな
積層電子部品用の積層チップには、前記従来の方法で、
正確かつ確実に導電ペーストを塗布することが困難であ
った。
[Problems to be Solved by the Invention] However, in the method for applying conductive paste for laminated chips according to the prior art, the plurality of holes 1 of the elastic body 2.2
It is difficult to perform so-called leveling, in which the protruding height of the tip of the laminated chip 5 is made constant by inserting it into the stacked chips 5, and as a result, the amount of conductive paste that adheres to the tip becomes uneven. In particular, the small laminated chip 5 can be inserted into the hole 1 of the rubber plate 4 as described above. 1... It is extremely difficult to hold it securely. For this reason, the length 1. A laminated chip for a small laminated electronic component with a width of 6 mm and a width of 0.8 mm is prepared using the conventional method described above.
It was difficult to apply the conductive paste accurately and reliably.

また、この従来の方法では、個々に切断分離3− された積層チップ5を前記弾性体2.2の複数の孔1、
■・・・に挿入しなければならないが、その作業は自動
化に適せず、また、両方の外部電極を一度に形成するこ
とが出来ない。そのため、人手による工数が多くかかり
、生産性が悪いという課題があった。
Furthermore, in this conventional method, the laminated chips 5, which have been individually cut and separated, are separated into a plurality of holes 1 of the elastic body 2.2.
(2)... However, this work is not suitable for automation, and it is not possible to form both external electrodes at once. Therefore, there was a problem that a large amount of manual labor was required, resulting in poor productivity.

そこで、本発明の目的は、前記従来の問題点に鑑み、小
形の積層チップでも確実かつ能率的に外部電極用の導電
ペーストが塗布出来る方法を提供することにある。
SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, an object of the present invention is to provide a method that can reliably and efficiently apply a conductive paste for external electrodes even to a small multilayer chip.

[課題を解決するための手段] すなわち、前記の目的を達成するため、本発明では、積
層体から分離される個々の積層チップに導電ペーストを
塗布する方法において、前記積層体を個々の積層チップ
に分離するための切断溝を形成し、次いでこの切断溝に
導電ペーストを塗布、充填し、この導電ペーストの中央
部を切断する積層チップへの導電ペースト塗布方法を提
供する。
[Means for Solving the Problems] That is, in order to achieve the above object, the present invention provides a method for applying a conductive paste to individual laminated chips separated from a laminated body. A method for applying conductive paste to a laminated chip includes forming a cutting groove for separating the chips, then applying and filling the cutting groove with conductive paste, and cutting the center portion of the conductive paste.

[作   用コ 4− 前記本発明による導電ペースト塗布方法によれば、積層
体を個々の積層チップに切断分離するための切断溝に導
電ペーストを塗布、充填することにより、個々の積層チ
ップの端面に導電ペーストが塗布される。しかし、この
導電ペーストは、前記切断溝で分離されるべき2つの積
層チップの端面に跨って塗布されるため、この導電ペー
ストの中央部を切断することにより、導電ペーストが個
々の積層チップの端面に付着する層として分離される。
[Function 4- According to the conductive paste application method according to the present invention, the end faces of the individual laminated chips are coated and filled with the conductive paste into the cutting grooves for cutting and separating the laminated body into individual laminated chips. conductive paste is applied to the However, since this conductive paste is applied across the end faces of the two laminated chips that should be separated by the cutting groove, by cutting the conductive paste in the center, the conductive paste can be applied to the end faces of the individual laminated chips. separated as a layer that adheres to the surface.

また、これらの工程は、積層体の裁断と導電ペーストの
所定の部分への塗布という工程からなり、これらは何れ
も自動化に適している。
Furthermore, these steps consist of cutting the laminate and applying conductive paste to predetermined portions, and both of these steps are suitable for automation.

[実 施 例コ 以下、本発明の実施例について、図面を参照しながら説
明する。
[Embodiments] Examples of the present invention will be described below with reference to the drawings.

第1図(a)に、導電ペースト等により電極パターンが
形成されたセラミックグリーンシートを複数枚積層した
積層体10が示されている。
FIG. 1(a) shows a laminate 10 in which a plurality of ceramic green sheets on which electrode patterns are formed using conductive paste or the like are laminated.

この積層体10は、切断溝を格子状に形成して相互に切
断、分離され、個々のの積層チップに分離される。この
とき、前記積層体10の下面には、粘着テープ20が貼
られ、切断溝で相互に分離しないよう保持されている。
This stacked body 10 is cut and separated from each other by forming cutting grooves in a grid pattern, and is separated into individual stacked chips. At this time, an adhesive tape 20 is attached to the lower surface of the laminate 10, and the laminate 10 is held so as not to be separated from each other by the cut grooves.

第1図(b)は、前記粘着テープ20によって下面が保
持された積層体10に、例えばダイシングマシーンのダ
イヤモンドブレード30によって、切断溝11.11・
・・を入れた状態を示している。例えば、寸法称呼16
08の積層セラミックコンデンサの製造工程の場合、こ
の溝1.1.11・・・は、溝幅0. 6mm、  溝
のピッチ1゜7關とする。
FIG. 1(b) shows cutting grooves 11, 11,
... is shown. For example, dimension designation 16
In the manufacturing process of the multilayer ceramic capacitor No. 08, the grooves 1, 1, 11... have a groove width of 0. 6mm, groove pitch 1°7 steps.

次いで、第1図(C)に示す様に、例えばスキージゴム
を用いて前記切断溝II、11・・・に導電ペースト1
2を塗布し、充填する。その後、この導電ペース)12
を、例えば800°C程度の温度で焼付け、硬化させる
。その後、第2図(d)に示す様に、ダイシングマシー
ンのダイヤモンドブレードによって、前記導電ペースト
12の中央部に15J断溝13.13・・・を入れる。
Next, as shown in FIG. 1(C), conductive paste 1 is applied to the cutting grooves II, 11, etc. using, for example, a squeegee rubber.
Apply 2 and fill. After that, this conductive paste)12
is baked and hardened, for example, at a temperature of about 800°C. Thereafter, as shown in FIG. 2(d), 15J grooves 13, 13, . . . are formed in the center of the conductive paste 12 using a diamond blade of a dicing machine.

この時、この溝13.13・・・の溝幅は、前記切断溝
IL]、I・・・の溝幅よりも狭クシ、例えば切断溝1
1、II・・・の幅が0.6m+nの場合、0゜1闘程
度の幅とする。この結果、第2図に示す様に、最初の切
断溝11の中に充填された導電ペースト12は、後に形
成される切断溝13によって、前記最初の切断溝ILI
Iの両側の切断面に付着した層が互いに分離される。
At this time, the groove width of the grooves 13, 13... is narrower than the groove width of the cutting grooves IL], I..., for example, the cutting groove 1.
If the width of 1, II... is 0.6m+n, the width should be about 0°1. As a result, as shown in FIG. 2, the conductive paste 12 filled in the first cutting groove 11 is transferred to the first cutting groove ILI by the cutting groove 13 formed later.
The layers deposited on both sides of the cut surface of I are separated from each other.

次ぎに、第1図(d)に示す様に、前記他の切断溝13
、IS・・・に対して直角な方向に他の切断溝14.1
4・・・を形成し、積層体を個々の積層チップ50.5
0・・・に分離する。例えば寸法称呼1608の積層セ
ラミックコンデンサの製造工程の場合、前記切断溝14
.14・・・の溝幅は、0. 1mm、溝のピッチは0
.9−=Iとする。
Next, as shown in FIG. 1(d), the other cutting groove 13
, IS... in the direction perpendicular to the other cutting groove 14.1.
4... and the stacked body into individual stacked chips 50.5
Separate into 0... For example, in the manufacturing process of a multilayer ceramic capacitor with a nominal size of 1608, the cutting groove 14
.. The groove width of 14... is 0. 1mm, groove pitch is 0
.. Let 9-=I.

以上に述べた方法により外部電極15.15が形成され
た積層チップ50が第3図に示されている。その寸法は
、前記称呼寸法1608のものでは、長さI=1.1+
u+、幅w=0. 8mmの積層形電子部品の両端に、
厚さd=0.25闘の外部電極15.15が形成され、
全体の長さL”1.6州となっている。この大きさの積
層チップは、既に述べた従来の方法では、導電ペースト
を確実に塗布することが困難であった。
A laminated chip 50 with external electrodes 15.15 formed by the method described above is shown in FIG. Its dimensions are the nominal dimension 1608, length I=1.1+
u+, width w=0. At both ends of the 8mm laminated electronic component,
An external electrode 15.15 with a thickness d=0.25 is formed,
The overall length is L"1.6 mm. It is difficult to reliably apply conductive paste to a laminated chip of this size using the conventional method described above.

本発明の方法によれば、−度に多数の積層チップ50.
50・・・の両端に導電ペースト12.12を正確に塗
布して外部電極15.15を形成することが司能である
。そして、既に述べたように、その方法は自動化に適し
ている。
According to the method of the invention, a large number of stacked chips 50.
The task is to accurately apply conductive paste 12.12 to both ends of the electrodes 50 to form external electrodes 15.15. And, as already mentioned, the method is suitable for automation.

このように両端に外部電極を形成した積層チップは、焼
成され、さらに必要に応じて絶縁塗装やメツキ処理等を
経て、両端に外部電極を存する積層チップ形セラミック
コンデンサが完成する。
The laminated chip with external electrodes formed on both ends is fired, and further subjected to insulating coating, plating, etc. as necessary, to complete a laminated chip type ceramic capacitor having external electrodes on both ends.

前記の実施例では、積層コンデンサの製造工程を例とし
て説明したが、本発明はこれに限られることなく、例え
ば積層インダクタ等、積層体を切断、分離した積層チッ
プの両端に導電ペーストを塗布する工程に広く適用する
ことが出来る。
In the above embodiment, the manufacturing process of a multilayer capacitor was explained as an example, but the present invention is not limited thereto. For example, a conductive paste may be applied to both ends of a multilayer chip such as a multilayer inductor, which is obtained by cutting and separating a multilayer body. It can be widely applied to processes.

[発明の効果コ 以上の説明からも明らかな様に、本発明による積層チッ
プへの導電ペースト塗布方法によれば、従来の方法では
不可能であった小形の積層チップでも、その両端に導電
ペーストを確実かつ能率よく塗布することが出来、しか
も自動化に適した方法が提供できる。
[Effects of the Invention] As is clear from the above explanation, the method of applying conductive paste to laminated chips according to the present invention allows conductive paste to be applied to both ends of even small laminated chips, which was impossible with conventional methods. can be applied reliably and efficiently, and can provide a method suitable for automation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明による積層チップへの導
電ペースト塗布方法を示す積層体の斜視図、第2図は前
記導電ペースト塗布方法の詳細を示す一部拡大断面図、
第3図は前記方法によって外部電極が形成された積層チ
ップの一例を示す斜視図、第4図(a)は従来用いられ
ている治具の要部破断斜視図、同図(b)はこれを用い
た導電ペースト塗布方法を示す要部断面図である。 lO・・・積層体 11.13.14・・・切断溝 1
2・・・導電ペースト 15・・・外部電極 50・・
・積層チップ 9− 手 続 補 正 書 事件の表示 平成 2年特許願第21825号 発明の名称 積層チップへの導電ペースト塗布方法 補正をする者 事件との関係  特許出願人 住 所  東京都台東区上野6丁目16番20号氏  
名   太  陽  誘  電  株  式  会  
社代  理  人 住 所  茨城県水戸市五軒町三丁目3番40号補正命
令の日付 (自 発) 補正の対象 図 面 補正の内容 1(
1(a) to (d) are perspective views of a laminate showing a method of applying a conductive paste to a multilayer chip according to the present invention; FIG. 2 is a partially enlarged sectional view showing details of the method of applying the conductive paste;
FIG. 3 is a perspective view showing an example of a laminated chip with external electrodes formed by the method described above, FIG. FIG. 2 is a cross-sectional view of a main part showing a method of applying a conductive paste using a method for applying a conductive paste. lO...Laminated body 11.13.14...Cutting groove 1
2... Conductive paste 15... External electrode 50...
・Laminated chip 9 - Display of procedural amendment case No. 1990 Patent Application No. 21825 Title of invention Method of applying conductive paste to laminated chip Relationship with the person who amends the case Patent applicant address 6-chome, Ueno, Taito-ku, Tokyo Mr. 16 No. 20
Taiyo Yuden Co., Ltd.
Company representative Personal address 3-3-40 Gokenmachi, Mito City, Ibaraki Prefecture Date of amendment order (voluntary) Contents of amendment to drawings subject to amendment 1 (

Claims (1)

【特許請求の範囲】[Claims]  積層体から分離される個々の積層チップに導電ペース
トを塗布する方法において、前記積層体を個々の積層チ
ップに分離するための切断溝を形成し、次いでこの切断
溝に導電ペーストを塗布、充填し、この導電ペーストの
中央部を切断することことを特徴とする積層チップへの
導電ペースト塗布方法。
A method of applying conductive paste to individual laminated chips separated from a laminate includes forming cutting grooves for separating the laminate into individual laminated chips, and then applying and filling the cutting grooves with conductive paste. A method for applying conductive paste to a laminated chip, the method comprising cutting the conductive paste at the center.
JP2021825A 1990-01-31 1990-01-31 Applying method of conductive paste onto multilayer chip Pending JPH03225904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021825A JPH03225904A (en) 1990-01-31 1990-01-31 Applying method of conductive paste onto multilayer chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021825A JPH03225904A (en) 1990-01-31 1990-01-31 Applying method of conductive paste onto multilayer chip

Publications (1)

Publication Number Publication Date
JPH03225904A true JPH03225904A (en) 1991-10-04

Family

ID=12065839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021825A Pending JPH03225904A (en) 1990-01-31 1990-01-31 Applying method of conductive paste onto multilayer chip

Country Status (1)

Country Link
JP (1) JPH03225904A (en)

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* Cited by examiner, † Cited by third party
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EP0535995A3 (en) * 1991-10-03 1993-05-12 Murata Manufacturing Co., Ltd. Method of manufacturing electronic components
JPH05198460A (en) * 1992-01-21 1993-08-06 Tdk Corp Manufacture of surface mount part
EP0582881A1 (en) * 1992-07-27 1994-02-16 Murata Manufacturing Co., Ltd. Multilayer electronic component, method of manufacturing the same and method of measuring characteristics thereof
JPH07192960A (en) * 1993-12-27 1995-07-28 Murata Mfg Co Ltd Multilayer electronic device, production thereof and characteristics measuring method
EP0637828A3 (en) * 1993-08-05 1997-05-14 Murata Manufacturing Co Multilayer electronic component, its manufacturing method and method of measuring its characteristics.
US5635669A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component
JP2006352020A (en) * 2005-06-20 2006-12-28 Tateyama Kagaku Kogyo Kk Manufacturing method of miniaturized electronic part
JP2010272793A (en) * 2009-05-25 2010-12-02 Murata Mfg Co Ltd Coil device array and manufacturing method thereof
JP2012109336A (en) * 2010-11-16 2012-06-07 Murata Mfg Co Ltd Method for manufacturing electronic component, and electronic component manufacturing device
JP2013165178A (en) * 2012-02-10 2013-08-22 Tdk Corp Multi-layered capacitor
JP2014187216A (en) * 2013-03-23 2014-10-02 Kyocera Corp Method of manufacturing multilayer ceramic capacitor
JPWO2020184652A1 (en) * 2019-03-12 2020-09-17

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EP0535995A3 (en) * 1991-10-03 1993-05-12 Murata Manufacturing Co., Ltd. Method of manufacturing electronic components
JPH05198460A (en) * 1992-01-21 1993-08-06 Tdk Corp Manufacture of surface mount part
US5635669A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component
EP0582881A1 (en) * 1992-07-27 1994-02-16 Murata Manufacturing Co., Ltd. Multilayer electronic component, method of manufacturing the same and method of measuring characteristics thereof
US5635670A (en) * 1992-07-27 1997-06-03 Murata Manufacturing Co., Ltd. Multilayer electronic component
EP0637828A3 (en) * 1993-08-05 1997-05-14 Murata Manufacturing Co Multilayer electronic component, its manufacturing method and method of measuring its characteristics.
JPH07192960A (en) * 1993-12-27 1995-07-28 Murata Mfg Co Ltd Multilayer electronic device, production thereof and characteristics measuring method
JP2006352020A (en) * 2005-06-20 2006-12-28 Tateyama Kagaku Kogyo Kk Manufacturing method of miniaturized electronic part
JP2010272793A (en) * 2009-05-25 2010-12-02 Murata Mfg Co Ltd Coil device array and manufacturing method thereof
JP2012109336A (en) * 2010-11-16 2012-06-07 Murata Mfg Co Ltd Method for manufacturing electronic component, and electronic component manufacturing device
JP2013165178A (en) * 2012-02-10 2013-08-22 Tdk Corp Multi-layered capacitor
JP2014187216A (en) * 2013-03-23 2014-10-02 Kyocera Corp Method of manufacturing multilayer ceramic capacitor
JPWO2020184652A1 (en) * 2019-03-12 2020-09-17
WO2020184652A1 (en) * 2019-03-12 2020-09-17 Tdk株式会社 Laminated all-solid secondary cell and method for manufacturing same
US12537228B2 (en) 2019-03-12 2026-01-27 Tdk Corporation Laminated all-solid secondary cell and method for manufacturing same

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