JPH03225950A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of pattern-designing freedom of an Al interconnection by a method wherein dummy patterns by a polycrystalline semiconductor film are arranged, via an insulating film, or respective diffused resistors which form a pair. CONSTITUTION:A polycrystalline silicon film is formed on an insulating film 14 by a CVD method; it is patterned via a resist mask. Dummy patterns 15 and 16 by the polycrystalline silicon film are formed to be symmetric on both diffused resistors 12 and 13. When they are arranged symmetrically, a stress exerted on a passivation film and the diffused resistors 12 and 13 at an assembly and molding operation is relaxed; an irregularity in the resistance ratio depending on whether an Al interconnection exists on the diffused resistors 12, 13 or not and a change in the absolute value of a resistance can be improved. Since the stress is relaxed, the Al interconnection can be formed freely on the diffused resistors 12, 13, and the degree of pattern-designing freedom of the Al interconnection is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, such as an LSI (Large Scale Integrated Circuit), having a pair of diffused resistors.

[Summary of the invention]

In a semiconductor device having a pair of diffused resistors, the present invention improves the resistance ratio of the pair of diffused resistors (i.e., the bare We aim to improve the variation in the ratio) and the variation in the absolute value of the resistance, and further improve the diffusion resistance!
This is intended to increase the degree of freedom in pattern design of Al wiring by making it possible to form wiring.

[Conventional technology]

In LST etc., a pair of diffused resistors (
In some cases, a resistor using a diffusion layer formed in a semiconductor substrate is required. The absolute value and resistance ratio (pair ratio) of this pair of diffused resistances vary depending on the passivation film, stress during assembly (molding), and the like. In particular, regarding the resistance ratio, as shown in FIG.
In the pair of first and second diffused resistors (2) and (3) connected to the I electrode (1), one of the diffused resistors (3)
When the Al wiring (4) is formed across only the top,
The variation in the resistance ratio further increases. For this purpose, conventionally, for example, as shown in FIG. 10, Al wirings (41) and (4□) are arranged symmetrically with respect to the first and second diffused resistors (2) and (3). Or, as shown in Figure 1, one diffused resistor (3) is connected to the other diffused resistor (2) and an equivalent IV dummy pattern (5) is connected to the Al wiring (4). In order to improve the resistance ratio.

[Problem to be solved by the invention]

However, in the configurations shown in FIGS. 10 and 11 described above, there is no degree of freedom in the Al wiring (4), (4,L (4□)), and various considerations must be made when designing the pattern.

In view of the above-mentioned points, the present invention provides a semiconductor device that can improve the variation in the resistance ratio of a pair of diffused resistors and the variation in the absolute value of the resistance, and can expand the degree of freedom in pattern design of Al wiring. .

(Means for Solving the Problems) The present invention provides a semiconductor device having a pair of diffused resistors (12) and (13).
Dummy patterns (15) and (16) made of polycrystalline semiconductor films are arranged on 2) and (13) with an insulating film (11) interposed therebetween.

[Effect]

According to the configuration of the present invention, the pair of diffused resistors (12) and (1
3) Since the dummy patterns (15) and (16) made of polycrystalline semiconductor films are placed on top of each other through the insulating film (11), the passivation film and during assembly (for example, during molding)
The stress on the diffused resistors (12) and (13) is alleviated, and fluctuations in the absolute value of the diffused resistors and variations in the resistance ratio are reduced. Furthermore, it becomes possible to form Al wiring that passes over the diffused resistors (12) and (13), increasing the degree of freedom in pattern design of the Al wiring.

[Example] An example of a semiconductor device having a pair of diffused resistors according to the present invention will be described with reference to FIG. 1, together with a manufacturing method thereof.

In this example, as shown in FIG. 1 A1 and A2, a pair of parallel and close to each other is formed on the main surface of one first conductivity type island region (11) formed on a semiconductor substrate by a conventional method. Resistors, that is, diffused resistors (12) and (13) are formed using the second conductivity type diffusion layer. (14) is an insulating film of 5in2 or the like formed on the island region (11).

Next, as shown in FIGS. 1B and B2, an insulating film (14
) A polycrystalline silicon film is formed on the re-diffusion resistors (12) and (13) by CVD (chemical vapor deposition) and patterned through a resist mask to form dummy patterns of polycrystalline silicon films on the re-diffusion resistors (12) and (13), respectively. (15) and (16)
) is formed symmetrically.

Here, when the length and width of the re-diffusion resistors (12) and (13) are the same, the dummy patterns (15) and (16) thereon are formed to have the same size. However, when the lengths and widths of the re-diffusion resistors (12) and (13) are different from each other, the dummy patterns (15) and (16) are
so that it is placed.

In addition, a dummy pattern (1
5) and (16), for example, form a polycrystalline silicon film in the opening for forming an emitter in another island region, form an emitter region by diffusing impurities from this polycrystalline silicon film, and also form the emitter region with the impurity-doped polycrystal. It can be formed in the same process as a polycrystalline silicon film when forming a bipolar transistor having a so-called polysilicon washed emitter structure in which a silicon film is used as an emitter extraction electrode.

After that, as shown in FIG. 1 and C2, an insulating film (17) such as SiO□ is deposited on the entire surface including the dummy patterns (15) and (16), and contact holes are formed to connect each diffusion layer. A pair of A! on both ends of resistors (12) and (13), respectively. Electrode (18A) (18B) and AI electrode (19A
) Connect (19B). In this way, dummy patterns (15) and (16) made of the polycrystalline silicon film are formed.
A target semiconductor device (20) having a pair of diffused resistors (12) and (13) arranged therein is obtained.

According to the above configuration, the pair of diffused resistors (12) and (13)
) by symmetrically arranging dummy patterns (15) and (16) made of polycrystalline silicon films through an insulating film (14), the passivation film and assembly (mold) are formed.
The stress exerted on the diffused resistors (12) and (13) at the time is alleviated, and the variation in resistance ratio and the variation in the absolute value of resistance due to the presence or absence of At wiring on the diffused resistors (12) and (13) are improved. I can do it. In addition, since the stress is alleviated, Al wiring can be freely performed on the diffused resistors (12) and (13), and the degree of freedom in designing the At wiring pattern is improved.

On the other hand, in recent years, LSIs including vertical bipolar transistors
In recent years, bipolar transistors are becoming faster and faster due to miniaturization of elements including self-line processes and shallower junctions.

However, even by making the emitter region and the heath region shallower, the peak concentration in the heath region must be increased in order to prevent punch-through between the emitter and collector, which has a considerable effect on transistor characteristics. ing.

That is, for example, as shown in FIG.
), a heath region (25) and an emitter region (26), the emitter region (26) being a polycrystalline silicon film (2
7), the impurity-topped polycrystalline silicon film (27) becomes the emitter extraction electrode, and the At electrode (28) is formed on top of the so-called vertical polysilicon won't emitter structure. In the type bipolar transistor (29), since the part A facing the interface with the insulating film (30) of the emitter junction is a junction with a very high concentration, the emitter-to-hose breakdown voltage V EEO is determined here. Ru. That is, since the concentration is high, the breakdown voltage V11° becomes small.

In addition, high concentrations on the emitter and heather surfaces generate burst noise in the collector current 1c.
This is especially a problem in linear audio applications.

In addition, as a low-noise transistor, it is necessary to prevent high concentration collision in the A section, and in recent years L E C (
Loiy Emitter Concentration
Although transistors having the n) structure are attracting attention, these structures result in an increase in the overall cell size, and at the same time, it is difficult to approach increasing the speed.

In this way, high speed and low noise of bipolar transistors are difficult to achieve, and it is difficult to provide a device that has both characteristics, especially since the approach to emitter concentration profile design is significantly different. .

The embodiment shown in FIG. 2 improves this point, and shows a semiconductor device and its manufacturing method in which a high-speed bipolar transistor and a low-noise transistor are simultaneously mounted, and each transistor can have desired characteristics in the circuit.

In this example, as shown in FIG. 2, n-type collector buried layers (32) and (33) are formed on the main surface of a first conductivity type, for example, a p-type silicon substrate (3), by a normal process.
) and a p' layer (34) for element isolation, an I] type epitaxial layer (35) is formed, and then a field insulating layer (SiOz) (36) is formed by selective oxidation to form a p' layer (34). 34) and a field insulating layer (36) to form an element isolation region (37). In the first element region (41) in which a low-noise transistor is to be formed, an n-type collector region (43) formed by an epitaxial layer is formed with a p-type heath region (44) and a collector buried layer (32).
form an n4 plug-in area (45) that reaches
Second element region (42) in which a high-speed transistor is to be formed
In the n-type collector region (4
8) has a p-type base region (49) and a collector buried layer (
A plug-in region 50) reaching 33) is formed.

In this example, p-type head regions (44) and (49) are formed at the same time, and n' plug-in regions (45) and (50) are formed at the same time.

Next, as shown in FIG. 2B, the first element region (41)
A relatively lightly doped n-type emitter region (46) is selectively formed in the side heath region (44) by ion implantation. After that, an insulating film (53
) is deposited and densified (including activation annealing).

Next, as shown in FIG. 2C, the insulating film (53) on the first and second element regions (41) and (42) is provided with a portion corresponding to the emitter and a collector extraction portion, respectively. Openings (54), (55) and (56) in the parts, respectively.
) (57). Here, the first element region (41
), the opening (54) corresponding to the emitter is formed to have a width smaller than the width of the lightly doped emitter region (46). Then, a polycrystalline silicon film (58) doped with n-type impurities in each of the openings (54) to (57) by a normal method,
After selectively forming (59) (60) and (61) and further depositing an insulating film (62) such as SiO□ on the upper surface, each polycrystalline silicon film (58), (59), (60
) and (61), an n-type high-concentration emitter region (47) and an n+ plug-in region (45) having a narrower width than the n-type low-concentration emitter region (46) are formed in the first element region (41). ) reaches the n-type collector extraction area (6
3), and an n-type collector extraction region (64) reaching the n-type emitter region (51) and n' plug-in region 50) in the second element region (42).

Next, contact balls corresponding to the emitter, base, and collector, respectively, are formed on the insulating film (62L (53)), and the emitter electrode (60), base electrode (67), and collector electrode made of At are formed in the first element region (41). (
68) and At in the second element region (42).
An emitter electrode (69), a base electrode (70) and a collector electrode (71) are formed. Thus, as shown in the second diagram, the first element region (41) has a low noise np
A target semiconductor device (74) is obtained in which an n-bipolar transistor (72) is formed and a high-speed npn bipolar transistor (73) is formed in the second element region (42).

According to the above configuration, the npn of the first element region (41)
As shown in the enlarged view of FIG. 3, the bipolar transistor (72) has a low concentration emitter region (46) and a base region (44) in contact with each other at the terminal end facing the interface with the insulating film (53) of the emitter junction. Therefore, both noise and emitter-base breakdown voltage (EIlo) are improved.

Further, the npn bipolar transistor (73) in the second element region (42) has a so-called polysilicon washed emitter structure, which allows miniaturization of the emitter region (51) and provides a high-speed transistor.

In this way, in this embodiment, a semiconductor device (74) is equipped with two types of transistors (72): a high-speed (high f1) transistor (73) and a low-noise, high-voltage V EBO transistor (72).
can be obtained, so it can be used selectively depending on the circuit application.

In addition, on the upper side, it was applied to an npn) transistor, but
The same applies to p n p l transistors. Furthermore, the base regions (43) and (49) in FIG. 2A can be of different types.

Next, we will discuss the MIS type capacitive element (87
), as shown in FIG. 6, a diffusion layer (82) of a second conductivity type, ie, n2 type, is formed in a semiconductor region (81) of a first conductivity type, for example, p-type, and an opening in an insulating film (86) is formed. One AI electrode (84) is placed on a predetermined region of the diffusion layer (82) through a dielectric film (83) made of, for example, 5iJa.
The other AI electrode (83) is formed in the other part of the diffusion layer (83).
5). This MIS type capacitive element (8
In 7), a highly accurate capacitive element is formed by sufficiently controlling the film thickness of the dielectric film (83). By the way, considering the combination with the bipolar transistor having the polysilicon washed emitter structure described above, the structure shown in FIG. 7 can be considered as the MIS type capacitor. That is, a dielectric film (83) made of, for example, Si+Ns is formed on the n-type diffusion layer (82).
, a polycrystalline silicon film (88) and an AI electrode (84) are stacked. In the case of a thin polycrystalline silicon film of 500 Å or less, A! The polycrystalline silicon reacts with the capacitance, resulting in MIS type capacitance characteristics. However, if the polycrystalline silicon film thickness exceeds 500 mm, the reaction is not sufficient and some polycrystalline silicon remains, and if this is pure polycrystalline silicon,
Fig. 8 shows an equivalent circuit in which polycrystalline silicon is connected in series with a capacitance C1 of 5iJn as a capacitance C1.Crystalline silicon has a large resistance R3 and a dielectric constant n=
The large value of 11.7 hinders the formation of a high-capacity, high-precision MIS type capacitor.

The embodiment shown in FIG. 5 improves this point and shows an MIS type capacitive element which can be mounted together with a transistor having a polysilicon washed emitter structure and which can be obtained with high precision.

First, as shown in FIG. 5A, for example, after forming an n-type epitaxial layer (92) on a p-type silicon substrate (91), a p-type element isolation layer (93) and an n-type diffusion layer (94) are formed. Formed by ion implantation method etc., then CVD on the substrate surface.
A SiO2 film (95) is formed by a method, and an opening (96) is formed in a portion corresponding to the MIS capacitance.

Next, as shown in FIG. 5B, a Si3N4 film (97) serving as a dielectric is formed by low pressure CVD and patterned to leave a 5iJ4 film (97) on the MIS capacitor pair.

Next, as shown in FIG. 5C, after forming an opening (98) in a portion of the SjO□ film (95) corresponding to the diffusion layer extraction portion, a polycrystalline silicon film (99) with a thickness of about 1000 is formed. form. This polycrystalline silicon film (99) is patterned as shown in the figure, leaving polycrystalline silicon films (99A) and (99B) only in the MlS capacitor part and the diffusion layer extraction part, respectively. Then, As'' (100) ions are implanted to remove the n゛ polycrystalline silicon film.

Then, annealing at approximately 1000°C in a N2 atmosphere was not performed for activation. In addition, instead of ion implantation, diffusion from AsF'-bu 5i02 was used to remove the polycrystalline silicon film 99A).
(99B) may be formed, or As-doped polycrystalline silicon may be formed by CVD.

Next, AZ is deposited using a conventional method, for example, by sputtering, and after buttering, sintering is performed in an atmosphere of 1 (2) to form polycrystalline silicon films (99A) and (99B), respectively.
Al electrodes (101) and (102) are formed on the fifth
A MIS type capacitive element (103) for the purpose shown in the figure is constructed.

Among the above steps, the polysilicon wash emitter of the npn bipolar transistor can be formed in the state shown in FIG. 5C.

According to the MIS type capacitive element (1,03) having the above configuration,
It is easy to mount the transistor together with an npn bipolar transistor having a polysilicon washed emitter structure.

Moreover, by adopting an n-type polycrystalline silicon film (99A) as the polycrystalline silicon film, the dielectric Si: +l
Even if the film thickness and area of the J+ film (97) are the same, the conventional MIS type capacitive element (n-type wave dispersion layer Si3N4) shown in FIG.
Higher capacity can be obtained compared to the membrane-AI tank structure, and there is less bias dependence. Regarding bias dependence, conventional M
While the IS type capacitive element has a voltage of 2000 ppm/V, this MIS type capacitive element (103) has a voltage of 1000 ppm/V.
/V or less.

Furthermore, this MIS type capacitive element (103) uses an n-type polycrystalline silicon film (99A), thereby obtaining good characteristics without capacitive hysteresis.

[Effects of the Invention] According to the present invention, in a semiconductor device having a pair of diffused resistors, a dummy pattern made of a polycrystalline semiconductor film is disposed on each diffused resistor with an insulating film interposed therebetween. It is possible to alleviate stress during assembly and improve variations in the resistance ratio of the pair of diffused resistors and variations in the absolute value of the resistance due to the presence or absence of At wiring on the diffused resistors.

Moreover, this increases the degree of freedom in designing the pattern of the Al wiring, making it easier to manufacture the semiconductor device.

[Brief explanation of drawings]

FIG. 1A is a manufacturing process diagram showing an example of a main part (a pair of diffused resistors) of a semiconductor device according to the present invention. B, ,C, are cross-sectional views, Fig. 1 A2. B2. C2 is a plan view, FIG. 2 is a sectional view showing the process order of an embodiment of a semiconductor device equipped with a high-speed bipolar transistor and a low-noise transistor at the same time, FIG. 3 is an enlarged sectional view of the main parts of the low-noise transistor, FIG. 4 is a cross-sectional view for explaining a conventional bipolar transistor, FIG. 5 is a cross-sectional view showing the process order of an embodiment of a MIS type capacitive element, FIG. 6 is a cross-sectional view of a conventional MIS type capacitive element, and FIG. is a 7C cross-sectional view of a MIS type capacitive element for comparison, Figure 8 is an equivalent circuit diagram of Figure 7, and Figures 9 to 11.
The figure is a plan view of a conventional pair of diffused resistors. (11) is the first conductivity type island region, (12) (13) is the diffused resistor, (14) is the insulating film, (15) (16) is the polycrystalline silicon dummy pattern, (188) (18B)
(198) (19B) is an Al electrode. Agent Hidemori Matsukuma 8 Ku9 Shiji Tokukai Hei 3 225950 (8) -Rikuzono

Claims (1)

[Claims] A semiconductor device having a pair of diffused resistors, wherein a dummy pattern made of a polycrystalline semiconductor film is disposed on each of the pair of diffused resistors with an insulating film interposed therebetween.