JPH03225963A - High-breakdown-strength mis transistor - Google Patents

Abstract

PURPOSE:To enhance a breakdown strength by a method wherein, in a high- breakdown-strength MIS transistor, a part around an interconnection contact part in a drain region is set to a low impurity concentration. CONSTITUTION:Since a part around an interconnection contact part in a drain region 6 is set to a low impurity concentration, a depletion region 10 of a large width is formed in a junction part of a part 6a around the interconnection contact part at the low impurity concentration to a semiconductor substrate 1. The region of the depletion layer formed in the junction part of the drain region 6 to the semiconductor substrate 1 is expanded, and a drain electric field is relaxed by this expanded portion. For example, the surface of a semiconductor substrate 1 is thermally oxidized selectively, a field insulating film 2 is formed, and an interelement isolation operation and an innerelement isolation are executed. Simultaneously with the operations, n-type impurities and p-type impurities which have been ion-implanted in advance into the semiconductor substrate 1 are diffused, and, e.g. an n<+> type channel stop region 3 and a p<-> type low-impurity concentration part 6a are formed at the lower side of the field insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage MIS transistor suitable for use in, for example, semiconductor integrated circuits.

[Summary of the invention]

According to the present invention, in a high voltage MIS transistor, a portion of a drain region surrounding a wiring contact portion has a low impurity concentration. Not only the portion around the wiring contact portion of the drain region but also the lower portion of the drain region may have a low impurity concentration. According to the present invention, high withstand voltage M
It is possible to improve the breakdown voltage of the IS transistor.

[Conventional technology]

Conventionally, a LOCOS offset drain type high voltage MOS transistor (hereinafter referred to as
The LOD type high voltage MO3I-transistor) is known. FIG. 7, FIG. 8, and FIG. 9 show conventional LOD type high voltage MO3 transistors. Here, FIG. 8 and FIG. 9 are cross-sectional views taken along the line ■-■ and the line IX-IX in FIG. 7, respectively. As shown in FIGS. 7, 8, and 9, in the conventional LOD type high voltage MO3 transistor, for example, an n-type silicon (Si) substrate 101
A field insulating film 102 is selectively formed on the surface of the
This performs inter-element isolation and intra-element isolation. Reference numeral 103 indicates, for example, an n'' type channel stop region. Further, a gate insulating film 104 is formed on the surface of the active region surrounded by the field insulating film 102.

The symbol G' indicates a gate electrode. In the n-type Si substrate 101, a p-type source region 105 is formed in self-alignment with this gate electrode G'. On the other hand, a p+ type drain region 106 is formed on the opposite side of the source N region 105 across the gate electrode G'.

In this case, in the lower part of the field insulating film 102 around this p+ type drain region 106, a p− type low impurity concentration portion 1 forming a part of this drain region 106 is formed.
06a is formed. and a gate electrode G',
A p-channel LOD type high breakdown voltage MO3 transistor is formed by the source region 105 and the drain region 106 having the low impurity concentration portion 106a.

In this case, the low impurity concentration portion 106 of the drain region 106
The drain electric field is relaxed by a.

Reference numeral 107 indicates an interlayer insulating film, and reference numerals 108 and 109 indicate aluminum (A1) wiring. Here, the A1 wiring 108 is connected to the source region 10 through the contact holes C1' to 05' formed in the interlayer insulating film 107 and the gate insulating film 104. Drain region 1.

5 and contacts 7 and gate insulating holes 06' to 06 [Problem to be solved by the invention] In the conventional LOD type high voltage MO3 transistor shown in FIGS. 7, 8, and 9 described above, Source area 105
is grounded and a negative drain voltage ■ is applied to the drain region 106.

When this is applied, a depletion layer 110 is formed as shown in FIGS. 8 and 9. In this case, the drain region 10
The junction between the low impurity concentration region 106a of No. 6 and the n-type St substrate 101 is a p--n- junction, but the junction between the p1-type drain region 106 and the n--type St substrate 101 is a p+n junction.
It is a joining. Therefore, the width of the depletion layer 110 at the junction between the low impurity concentration region 106a, which is a p--n-junction, and the n-type Si substrate 101 becomes large; drain region 106 n-type Si substrate 101
The width of the depletion layer 110 at the junction with the depletion layer 110 becomes smaller. Therefore, although the drain electric field is relaxed at the junction between the low impurity concentration region 106a and the n- type Si substrate 101,
It is not relaxed at the junction between the type drain region 106 and the n-type St substrate 101. This was the cause of deterioration in the breakdown voltage of the conventional LOD type high breakdown voltage MO3I-transistor.

Therefore, an object of the present invention is to provide a high voltage MIS transistor that can improve the voltage resistance.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a high breakdown voltage MIS transistor in which a portion of the drain region (6) surrounding the wiring contact portion has a low impurity concentration.

Preferably, not only the portion around the wiring contact portion of the drain region (6) but also the lower portion of the drain region (6) may have a low impurity concentration.

[Effect]

According to the high-voltage MIS transistor of the present invention configured as described above, since the portion around the wiring contact portion of the drain region (6) has a low impurity concentration, this wiring contact portion having a low impurity concentration The surrounding area (6a
) and the semiconductor substrate (1), a wide depletion layer (10) is formed at the junction. by this,
Compared to the case where only the portion around the drain region (6) has a low impurity concentration, the depletion layer region formed at the junction between the drain region (6) and the semiconductor substrate (1) is expanded, The drain electric field is relaxed by that amount. This makes the drain electric field more uniform.

As described above, it is possible to improve the breakdown voltage of the high breakdown voltage MIS transistor.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

FIG. 1 shows an LOD type high breakdown voltage MO3 according to an embodiment of the present invention.
The plan view of the transistor, FIGS. 2 and 3, are cross-sectional views taken along the lines 1--2 and 2--2 in FIG. 1, respectively.

As shown in FIGS. 1, 2, and 3, in the LOD type high voltage MO3 transistor according to this embodiment, for example, a SiO□ film is formed on the surface of a semiconductor substrate 1 such as an n-type Si substrate. A field insulating film 2 is selectively formed, thereby providing isolation between elements and isolation within elements. Reference numeral 3 indicates, for example, an n+ type channel stop region.

Here, this channel stop region 3 is formed so as to surround the entire transistor. Field insulation film 2
A gate insulating film 4 such as a 5i02 film, for example, is formed on the surface of the active region surrounded by. G indicates a gate electrode. This gate electrode G is made of a polycrystalline Si film doped with an impurity such as phosphorus (P), or a high melting point metal such as a tungsten silicide (WSiz) film on the polycrystalline Si film doped with this impurity. It can be formed using a polycide film or the like, which is a stack of silicide films. Further, this gate electrode G is formed to straddle both the gate insulating film 4 and the field insulating film 2 when viewed in the channel length direction of the transistor.

On the other hand, the reference numeral 5 indicates, for example, a p+ type source region. This source region 5 is formed in the semiconductor substrate 1 in a self-aligned manner with respect to the gate electrode G.

Reference numeral 6 indicates a drain region. Further, reference numeral 7 is an interlayer insulating film such as a phosphosilicate glass (PSC) film,
8 and 9 indicate wiring such as aluminum (AI) wiring, for example. Here, the wiring 8 contacts the source region 5 through the contact hole Cl"' C4 formed in the interlayer insulating film 7 and the gate insulating film 4, and the wiring 9 contacts the source region 5 through the contact hole Cl"' C4 formed in the interlayer insulating film 7 and the gate insulating film 4. Hall C
It is in contact with the drain region 6 through C8.

In this embodiment, contact holes C5 to C8 for bringing the wiring 9 into contact with the drain region 6 are formed on the active region surrounded by the field insulating film 2, respectively. The drain region 6 of the contact portion of this wiring 9 is, for example, p+ type. On the other hand, in this drain region 6, a portion around the contact portion of the wiring 9 and a portion below the field insulating film 2 are, for example, p-
This is a low impurity concentration portion 6a of the mold.

Next, the LOD according to this embodiment configured as described above
A method for manufacturing a high-type, high-voltage MOS transistor will be explained.

As shown in FIGS. 1, 2, and 3, first, for example, by selectively thermally oxidizing the surface of a semiconductor substrate 1, a field insulating film 2 is formed to perform inter-element isolation and intra-element isolation. At the same time, the n-type impurity and the n-type impurity that have been ion-implanted into the semiconductor substrate 1 are diffused, so that, for example, an n+ type channel stop region 3 and a p- type A low impurity concentration portion 6a is formed. Next, a gate insulating film 4 is formed on the surface of the active region surrounded by the field insulating film 2 by, for example, a thermal oxidation method. Next, a polycrystalline Si film, for example, is formed on the entire surface by the CVD method, and on this polycrystalline Si film, for example, P
After reducing the resistance by doping with impurities such as, the polycrystalline Si film is patterned into a predetermined shape by etching to form the gate electrode G. Note that when the gate electrode G is formed of a polycide film, after forming a high melting point metal silicide film on the polycrystalline St film doped with the impurity mentioned above, the high melting point metal silicide film and the polycrystalline Si film are removed. Perform patterning. Next, an n-type impurity such as boron (B) is ion-implanted into the entire surface at a high concentration. In this case, the gate electrode G and the field insulating film 2
serves as a mask during this ion implantation, and the source region 5 is formed in a self-aligned manner with respect to the gate electrode G, and p'' is formed on the opposite side of the source region 5 across the gate electrode G. '' type drain region 6 is formed.

Next, after a glabellar insulating film 7 is formed on the entire surface by CVD, predetermined portions of the glabellar insulating film 7 and gate insulating film 4 are etched away to form contact holes 0 CI to C1l. Next, a film is formed over the entire surface by, for example, sputtering, and then this AI film is patterned into a predetermined shape by etching to form interconnections 8.9. As a result, the desired LOD type high breakdown voltage MO3 transistor as shown in FIGS. 1, 2, and 3 is completed.

Note that in the case of a semiconductor integrated circuit in which an n-channel MO3 transistor and a p-channel MO3 transistor are formed on the semiconductor substrate 1, the ion implantation of p-type impurities for forming the low impurity concentration portion 6a of the drain region 6 described above is This can also be used for ion implantation of p-type impurities to form a channel stop region for a channel MO3 transistor.

In the LOD type high voltage MO3 transistor according to this embodiment, when the source region 5 is grounded and a negative drain voltage 2 is applied to the drain region 6, a depletion layer is formed as shown in FIGS. 2 and 3. 10 is formed. in this case,
The p+ type drain region 6n-type junction with the semiconductor substrate l is a p"-n1 junction, and the width of the depletion layer 10 formed at this p"-n-junction is small. On the other hand, the junction between the p-type low impurity concentration 6a of the drain region 6 and the n-type semiconductor substrate 1 is a p---n-junction, and the depletion formed in this p---junction is The width of 110 is large. In this embodiment, not only the surrounding area of the drain region 6 but also the surrounding area of the P'' type drain region 6 with which the wiring 9 contacts is a p-type low impurity concentration region 6a, so that the drain region The proportion of the portion of the junction between the semiconductor substrate 1 and the semiconductor substrate 1 that is a pn-junction increases. Therefore, the depletion layer region at the junction between the drain region 6 and the semiconductor substrate 1 is expanded compared to the conventional case. And drain region 6
When viewed as a whole, the drain electric field is more uniform than in the past. Thereby, the breakdown voltage of the LOD type high breakdown voltage MO3 transistor can be improved.

Further, the LOD type high breakdown voltage MOS transistor according to this embodiment can be easily realized by simply changing the pattern of the field insulating film of the conventional LOD type high breakdown voltage MOS transistor.

The structure of the LOD type high breakdown voltage MO3 transistor according to this embodiment has a large channel width and a wiring 9 in the drain region 6.
This is particularly effective when there are a large number of contact holes for making contact with each other.

Further, the LOD type high breakdown voltage MOS transistor according to this embodiment is suitable for application to, for example, a semiconductor memory.

Next, other embodiments of the present invention will be described.

4 and 5 are cross-sectional views showing LOD type high voltage MO3 transistors according to other embodiments of the present invention. This L
The plan view of the OD type high voltage MO3 transistor is the same as that in FIG. Here, FIGS. 4 and 5 correspond to cross-sectional views taken along the lines 1--2 and 1-2 in FIG. 1, respectively.

As shown in FIGS. 1, 4, and 5, in the LOD type high voltage MO3 transistor according to this embodiment, not only the portion around the p+ type drain region 6 of the contact portion of the wiring 9 but also the p+ type The lower part of the drain region 6 is also a p-type low impurity concentration portion 6a, for example. That is, in this embodiment, the p- type low impurity concentration portion 6a is also formed under the p+ type drain region 6.

In order to manufacture the LOD type high breakdown voltage MO3 transistor according to this embodiment, first, as shown in FIG. A resist pattern 11 having a predetermined shape with openings corresponding to the portions to be formed is formed by lithography. Thereafter, using this resist pattern 11 as a mask, a p-type impurity such as B is ion-implanted into the semiconductor substrate 1 at a low concentration (semiconductor substrate 1
(The dots represent the impurities ion-implanted into the dots.)

The dose of the p-type impurity ion implantation is such that, for example, the concentration of the low impurity concentration region 6a formed by the diffusion of the p-type impurity is the same as that of the low impurity concentration 6a formed under the field insulating film 2. The concentration is chosen so that it is almost the same as the concentration.

Next, after removing the resist pattern 11, as shown in FIG. Ion implantation at high concentration. After this, annealing is performed to electrically activate the implanted impurities. As a result, as shown in FIGS. 1, 4 and 5, a p' type source region 5 and a p' type drain region 6 having a p' type low impurity concentration region 6a are formed.

After this, the process is carried out in the same manner as described in the above example,
Complete the desired LOD type high voltage MO3 transistor.

As described above, according to this embodiment, not only the portion around the drain region 6 but also the portion around the contact portion of the wiring 9 and the lower part thereof are all p-type low impurity concentration portions 6a.
Therefore, a wide depletion layer 10 is formed throughout the junction between the drain region 6 and the semiconductor substrate 1. Then, the drain electric field becomes more uniform. Thereby, the breakdown voltage of the LOD type high breakdown voltage MO3 transistor can be further improved.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the two embodiments described above, four contact holes C8 to C4 are used to contact the wiring 9 with the drain N region 6, but it is also possible to use five or more contact holes, for example. It goes without saying that there is.

In addition, in the above two embodiments, the p-channel L
Although the case where the present invention is applied to an OD type high voltage MO3 transistor has been described, the present invention is applicable to an n-channel LOD
It is also possible to apply the present invention to a type high-voltage MO3 transistor. Furthermore, the present invention is not necessarily limited to LOD type high voltage MOI transistors, but can be applied to various high voltage MIS transistors other than LOD type high voltage MOI transistors.

〔Effect of the invention〕

As described above, according to the present invention, since the portion around the wiring contact portion of the drain region has a low impurity concentration, it is possible to improve the breakdown voltage.

Further, since the lower part of the drain region also has a low impurity concentration, the breakdown voltage can be further improved.

[Brief explanation of drawings]

FIG. 1 shows an LOD type high breakdown voltage MO3 according to an embodiment of the present invention.
A plan view showing the transistor, FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1, FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG. 1, and FIGS. The figure is a cross-sectional view of an LOD type high-withstand high-voltage MOS transistor according to another embodiment of the present invention, and FIGS. 6A and 6B are LOD-type high-withstand and high-voltage MOS transistors shown in FIGS. A sectional view for explaining the method, FIG. 7 is a plan view of a conventional LOD type high breakdown voltage MOS transistor, FIG. 8 is a sectional view taken along the line ■-■ in FIG. 7, and FIG. 8 is a sectional view taken along the line IX-IX in FIG. 7. FIG. 7. Explanation of the main symbols in the drawings: semiconductor substrate, 2: field insulating film, 5: source region, 6: drain region, 6a: low impurity concentration region, 8, 9: wiring, IO: depletion layer, G: gate electrode , CI”Ca: Contact hole.

Claims (2)

[Claims] (1) High breakdown voltage MI characterized by a low impurity concentration in the area around the wiring contact part of the drain region
S transistor. (2) The high breakdown voltage MIS transistor according to claim 1, wherein a lower part of the drain region also has a low impurity concentration.