JPH03226073A - Clamp circuit with switch - Google Patents

Abstract

PURPOSE:To prevent an output data at clamp from being deficient by incorporating a bipolar structure switch circuit and integrating a clamp circuit and the switch circuit into one chip and providing a control circuit outputting an optional data at clamping state. CONSTITUTION:When an optional voltage is desired to be clamped, a signal is inputted from a terminal 34 to turn on switches 4, 18 and an optional voltage desired to be clamped is inputted to noninverting inputs 1, 15 of amplifiers 5, 19. Thus, the output voltage from the amplifiers 5, 19 is fed back to one input of the amplifiers 5, 19 to clamp the same voltage as the level of the noninverting inputs 1, 15 to the emitter of transistors(TRs) 11, 25. In this case, emitters of TRs 14, 28 are used in common and the emitter follower constitution using a TR 30 as the constant current source. Thus, a signal outputted from the emitters of the TRs 14, 28 is a signal from any of the TRs 14, 28 having a base level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clamp circuit with a switch, and particularly to output data during clamping.

[Conventional technology]

Conventionally, when switching between two or more video signals, a method has been used in which a clamp circuit is installed in front of each video signal in order to equalize the levels of the synchronized portions, and then switching is performed using a switching element.

For example, as shown in FIG. 2, 0MO8 transmission gates 37, 38, and 39°40 were attached to a clamp circuit. That is, the switches 4 and 18 are turned on and the amplifiers 5 and 1 are turned on.
By inputting an arbitrary voltage to be clamped to the + side input l, 15 of the amplifier 5, 19, the output voltage of the amplifier 5, 19 is changed to the amplifier 5, which is connected to the collector of the transistor 7, 21 via the transistor 7, 21. Feedback is applied to one side of transistor 19, and 1, which is the + side input, is applied to the collector of transistor 7.21.
, 15 to clamp the same voltage. Next, switch 4,
18 is turned off and the input fi element 2.16 is connected to the capacitor 3,
By inputting an analog signal to the base of the transistor 7.21 through 17, the voltage from the collector of the transistor 7.21 is applied to any voltage input to 1 and 15, which are the positive inputs of the amplifiers 5 and 19. Can output analog signals. At this time, when it is desired to output the signal from the input terminal 2, the GND voltage is applied to the gate of the MO3h run transistor 40 that constitutes the transmission gate of the CMOS, and V is applied to the gate of 38.39. Apply a voltage of 0, turn on the transmission game) 37.38, and turn on the 39.4
By turning off 0, only the signal from input terminal 2 can be output. Similarly, when you want to transmit a signal from the input terminal 16, MO8) Apply pressure to the gate of the transistor 37.40 to Vcc', apply pressure to the gate of 38.39 to GNDl, turn on the transmission gate 39.40, and turn on the transmission gate 37. By turning off 38, the signal from the input terminal 16 can be output. In this manner, conventionally, when a plurality of clamp circuits were used by switching, the transmission gate of the CMO 8 was turned on and off to output data clamped to an arbitrary voltage to the next stage circuit. In other words, as shown in Figure 2, the next stage A/D
When a circuit is provided, the data after clamping is A/D converted by a transmission gate to generate digital data.

In Figure 2, 1, 2, 15.16 are input terminals, 5.1
9 is amplifier, 4, 18 is switch, 6゜8.20.22
is a resistor, 7 and 21 are transistors, 36 is an A/D converter, and 37 to 40 are MOS transistors.

Problems to be solved by the invention C] The conventional clamp circuit described above requires a transmission gate of MO8 when multiple circuits are switched and used, so the transmission gate and clamp circuit are built into an integrated circuit and integrated into one chip. In this case, since the transmission gate has an MO8 structure, it is difficult to integrate into one chip, and the cost is high.

Furthermore, since the select switch is off during clamping, the output is insufficient, so there is a drawback that the output data during clamping changes each time it is clamped, so the digital data after A/D conversion also changes.

Although the present invention will be described using an A/D converter as the next stage circuit, any other circuit may be used.

[Means to solve the problem]

The present invention provides a clamp circuit with a switch to improve the conventional problems.

In other words, the present invention has two stages of emitter followers in which the collector of a transistor to which an analog signal is input is connected to the base, and a switch for controlling the base potential of the emitter follower, as a means of integrating a switch circuit and a clamp circuit into one chip. It is characterized by having a transistor which is a circuit, and having a cheater control circuit for controlling the output cheater to an arbitrary cheater during clamping.

An embodiment of the present invention will be described with reference to FIG.

[Differences between the invention and the prior art]

In contrast to the conventional clamp circuit described above, the present invention has a built-in switch circuit with a bipolar structure, integrates the clamp circuit and the switch circuit into one chip, and also has a control circuit for outputting arbitrary data during clamping. It is said that

[Pretext] FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 2 are given the same numbers and the explanation will be omitted. 10~ in Figure 1
12,14.24-26,28°30 is a transistor,
9, 13, 23, 27, and 31 are resistors, 32 to 34 are terminals, 35 is a data control circuit, and 36 is an A/D converter.

The present invention integrates a switch circuit and a clamp circuit into one chip, and has two emitter followers whose bases are connected to the collectors of transistors into which analog signals are input as a means for outputting any desired output during clamping, and controls the base potential of the emitter followers. It is characterized in that it has a transistor which is a switch circuit for controlling the data, and a data control circuit for controlling output data to arbitrary data during clamping.

The operation according to an embodiment of the present invention will be described below.

In the clamp circuit with a switch of the present invention, when it is desired to clamp an arbitrary voltage, input a signal from the terminal 34, turn on the switches 4 and 18, and select the desired voltage to be clamped to the + side inputs 1 and 15 of the amplifier 5.19. By inputting the voltage, the output voltage of amplifier 5゜19 is changed to transistor 7.
．． 21 and the emitter of the transistor 11.25, whose collector is connected to the base of the amplifier 5,1.
Feedback is applied to one side input of 9, and the emitter of transistor 11.25 is clamped to the same voltage as 1 and 15, which are positive side inputs. The emitter of transistor 11.25 is connected to power supply 29
Transistor 12, which is given a higher base voltage.
It is connected to the collector of transistor 11.2.
5 has an emitter follower configuration with transistors 12 and 26 as constant current sources. Next, switch 4, 18
By turning off the input terminals 2 and 16 and inputting an analog signal to the base of the transistor 7.21 via the capacitors 3 and 17, the collector of the transistor 7.21 is connected to the base of another transistor 14.28. The emitter outputs an analog signal that amplitudes with respect to any voltage input to the amplifiers 5 and 19 and 15. At this time, the transistors 14 and 28 have a common emitter, and are connected to the collector of the transistor 30 to which the base voltage is applied from the power supply 29.
0 as a constant current source, the emitter of the transistor 14.28 outputs a signal from whichever of the transistors 14.28 has a higher base potential. Furthermore, when it is desired to output only the signal from the input terminal 2, the potential of the terminal 32 whose collector is connected to the base of the transistor 10 which is common to the transistor 7 is set to GND potential, and the terminal whose collector is connected to the base of the transistor 24 which is common to the transistor 21 is set to the GND potential. By setting the potential of the transistor 33 to V-0 potential, a combined current of the transistors 21 and 24 flows through the resistor 20 and the collector potential of the transistor 21 is forcibly lowered, so that the emitter follower 14
．． The base potential of transistor 28 becomes higher than that of transistor 14, and the signal from input terminal 2 is output. Similarly, when you want to output the signal from input terminal 16, use terminal 32.
The potential of V. By setting the potential of the terminal 33 to 0 (GND), the signal from the input terminal 16 can be output.

Also, when a signal is input from the terminal 34 and the switch 4.18 is turned on and clamped, the signal from the terminal 34 is taken into the data control circuit, and the output of the A/D converter is changed to A by the signal output from the data control circuit. It is possible to forcibly set certain data, for example, all "0", regardless of the input of /D.

At this time, the data control circuit may be, for example, a circuit as shown in FIG.
If the signal that turns on the transistor 8 is, for example, VCC potential, a current flows through the transistor 43 of the data control circuit in FIG. The potential becomes VCC potential, and this signal is received by the A/D converter to output arbitrary digital data, for example, all "0". In Figure 3, 41.45 is a resistor, 42 to 44 are transistors, and 4
6.47 is a power supply.

[Embodiment 2] FIG. 4 shows a second embodiment of the present invention. In FIG. 4, 48 to 50, 52 to 54 are transistors, 51.55 is a resistor, 56 is a switch, and 57.58 is a power supply. Since the other numbers are the same as those in FIG. 1, their explanation will be omitted.

In this embodiment, the switches 4, 18 and 56 are reverse operated by the clamp signal from the terminal 34, and the transistors 48, 52, which have a collector common to that of the transistors 7, 21, and the differential transistors 49 and 53 forming the differential, and resistors 51 and 55 forming constant current sources for the transistors forming the differential;
Clamped by providing transistors 49 and 53.

and the signals input from terminals 2 and 16 to the A/D
When sending the signal to the input of terminal 32, the operation is similar to that shown in Figure 1, but when clamping, the input from terminal 34 turns on switch 4.18 and turns off switch 56, so which signal is input to terminal 32.33? Even if such a signal is input, it will not affect the clamp. At this time, the data control circuit
3. If the signal of 34 is taken in and the data of terminal 32 is higher potential than the data of 33, send any signal in the clamp circuit connected to terminal 23 to A/D and the A/D will clamp connected to terminal 32 by that signal. Outputs any digital output of the circuit, for example all "0"s. Further, if the cheater at terminal 33 has a higher potential than the cheater at terminal 32, an arbitrary signal in the clamp circuit connected to terminal 33 is sent to the A/D, and the A/D is connected to terminal 33 by that signal.
It is possible to output any digital output of the clamp circuit connected to , for example, all "1"s. In this way, during clamping, data suitable for each selected clamp circuit can be output.

An example of such a cheater control circuit is shown in FIG.

As shown in Figure 5, 59, 60, 64, 65, 69°70
．． 74 is a resistor, 61-63, 66-68, 71-73 are transistors, 75-77 are power supplies, and 78 is a switch. In this data control circuit, when the input of terminal 34 is not clamped, switch 78 is turned off, so terminal 3
Regardless of the input signal of 2.33, the collectors of transistors 61 and 62 are at the same potential as V flow transistor 66
．． The collector potential of 72 becomes Low level, and its output sends a signal to the A/D, and the A/D outputs the deisotartator by inputting to the terminal 2.16. On the other hand, during clamping, the switch 78 is turned on, and the higher potential input of the terminals 32 and 33 sends a high level signal to the A/D, thereby digitally outputting arbitrary data to that signal.

〔Effect of the invention〕

As explained above, the present invention has two stages of emitter and vine followers in which the collector of the transistor to which an analog signal is input is connected to the base in a clamp circuit, and the transistor is a switch circuit for controlling the base potential of the emitter follower. By having a data control circuit to control the output data during clamping to arbitrary data, the switch circuit and clamp circuit are integrated into one chip, improving the lack of output data during clamping, and controlling the output data to arbitrary data during clamping. This has the effect of obtaining output data.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows a conventional example, and Fig. 4 shows an example of the present invention.
The figure shows an embodiment of the present invention, and FIGS. 3 and 5 show examples of data control circuits. Numbers 1, 2, 15, 16, 32 to 34 in the diagram are terminals,
4, 18, 58.78 are switches, 5゜19 is an amplifier,
3, 17 are capacitors, 6° 8.9, 13, 20,
22, 23, 26, 30° 41.45, 55, 59, 6
0,64,65°69.70.74 is resistance, 7.10~
12゜14.21.24~26.28, 30.42~4
4.48~50.52~54.61~63°66~68
．． 71-73 are transistors, 37-40 are MOS) transistors, 29, 46.47°57.58.75-77
36 is a power supply, 36 is an A/D, and 35 is a data control circuit.

Claims (2)

[Claims] (1) In a clamp circuit with a switch, which consists of multiple clamp circuits and switches that select their outputs,
Two emitter follower circuits are added to each of the outputs of the clamp circuits, and the output of one of the emitter follower circuits is used as a feedback signal for the clamp circuit, and the output of the other emitter follower circuit is commonly connected to the output terminal. 1. A clamp circuit with a switch, comprising means for selectively shifting the input bias voltage of each of the emitter follower circuits. (2) The clamp with a switch according to claim 1, which has a circuit that outputs preset data regardless of the output of the clamp circuit based on data of a switch that selects a plurality of clamp circuits during clamping. circuit.