JPH03226121A - Data conversion circuit - Google Patents

Abstract

PURPOSE:To make the increase in the circuit scale and wiring slight even when an expanded data length is large by giving a clock of a prescribed shift number of times to an N+l bit of register with a signal representing the shift so as to convert the data. CONSTITUTION:A shift means 83 is used to input 3 clocks to 6-bit shift registers FF6-1 and selectors 93-91 select signals A2-A0 of an effective n-bit at the initial clock, the selector 93 output a selection signal selecting an output of the high- order FF6 and the selectors 92, 91 output a selection signal selecting the output of the high-order FF at succeeding clocks. Then a signal A2 is outputted from outputs Y5-Y3 of FF6-FF4, a signal A1 is outputted from an output Y2 of the FF3, a signal A0 is outputted from an output Y1 of the FF2 and 0 is outputted from an output Y0 of the FF1 respectively and a data of a fixed decimal point representation in desired 6-bit is outputted. Thus, when the expand ed data length is increased by, e.g. 1 bit, a FF0 is to be provided newly and similar wiring to that for the FF1 is implemented.

Description

[Detailed Description of the Invention] [Overview] A data conversion circuit that converts floating point representation data consisting of an effective n-bit signal and a signal indicating a shift amount into fixed point representation data having a data length of (n+2) bits. With regard to Each input stage is provided with a selection circuit, and the output signal of the register at the top stage is inputted to one of the corresponding selection circuits, and the output signal from the registers below the top stage is sequentially input to the selection circuit at the input stage of the register at the bottom stage. Each of the 2-bit registers not provided with the selection circuit is configured to input an output signal from the register one level above, and the n-bit valid data is input to the 2-bit register. input to the n-bit register via the other input part of the selection circuit in the input stage of the n-bit register;
Next, the selection circuit is selectively driven to input the output signal of each of the registers, and data is converted by applying a clock for a predetermined number of shifts to the n+ff bit register using a signal indicating the shift amount. .

[Industrial application field]

The present invention is capable of converting floating-point representation data consisting of an effective n-bit signal and a shift amount signal to a data length of (n+l).
) This invention relates to an improvement in a data conversion circuit that converts bits into fixed-point representation data.

When calculating floating-point data, convert it to fixed-point data, and use data with high calculation precision (n-1
When inputting to a -j-bit arithmetic circuit, it is necessary to convert valid n-bit data into (n+f)-bit fixed-point representation data.

For example, the 5-bit valid data (M
(A4 of SB is a sine lift indicating positive or negative) and 3-bit shift data indicating a 4-bit shift amount. When floating-point display data is converted to 12-bit fixed-point display data, the result is shown in (B). As shown in FIG.
The bit is indicated by sign bit A4.

As described above, when converting data to a long data length, there is a demand for a data conversion circuit that does not increase the circuit scale and wiring even if the data length is increased.

Below, the conventional example and the embodiment of the present invention are shown in Fig. 4 (A
An example of converting the floating point data shown in FIG. 4(B) to the 12-bit fixed point data shown in FIG. 4(B) will be explained.

[Conventional technology]

FIG. 5 is a circuit diagram of a conventional data conversion circuit, which uses a barrel shifter.

In the figure, 1 to 12 are flip-flops (hereinafter referred to as FF) which are registers, 50 is a decoder, 51 to 68 are AND circuits, and 70 to 75 are OR circuits.

In this case, the decoder 50 outputs shift data B2°Bl,
If the value indicated by BO is O, the output 0 is a level and the others are O level, and if it is 4, the output 4 is a level and the others are 0 level.

Valid data is A4. A3. A2. If the 5 bits of Al and AO are shifted by 4 bits, output 4 of the decoder 50, Lebel, etc. are at O level, so AO is input to the AND circuit 61. Output via OR circuit 73°FF5, AI
, A2. A3. A4 is output via FF6, 7, 8.9.

Also, since the outputs of the AND circuits 60 to 51 are at 0 level,
O is output from FF4, 3, 2.1, A4 is input to FFl0 via the OR circuit 74, and A4 is output.
A4 is input to FFII via the OR circuit 75, and A4
is output, A4 is input to the FF 12, and A4 is output, and is converted into fixed-point display data using the clock.

In this circuit, 5101 AND circuits are subordinate to FFI, two AND circuits 52 and 53 are subordinate to FF2,
Three AND circuits 54 to 56 are subordinate to FF3, and FF3
Four AND circuits 57 to 60 are subordinate to FF4, and five AND circuits 61 to 65 are subordinate to FF5.Since the input data is valid 5 bits, the number of AND circuits increases to five, and FF5 is subordinated to five AND circuits 61 to 65.
F6-7 have 5 AND circuits, FF8 has 4 AND circuits, FF9 has 3 AND circuits, and FF10 has 2 AND circuits.
One AND circuit is subordinate to each FFII.

That is, as the data length to be expanded increases, in this case, the number of FFs that depend on five AND circuits increases, so the circuit scale becomes extremely large, and the number of wires connected to the output line of the decoder 50 also increases. .

[Problem to be solved by the invention]

As explained above, conventional data conversion circuits have the problem that when the data length to be extended becomes large, the circuit scale becomes very large and the number of wiring increases.

An object of the present invention is to provide a data conversion circuit in which the circuit scale and wiring are only slightly increased even when the data length to be extended becomes large.

[Means to solve the problem]

FIG. 1 is a bronch diagram of the principle of the present invention, in which an effective n-bit signal is A2. Expand with 3 bits, Al and AO, and shift amount by 2 bits! The case where the number of bits is 3 is shown.

Data conversion that converts floating point representation data consisting of an effective n bits (3 bits) signal and a signal indicating the shift amount (2 bits) to fixed point representation data with a data length of (n+f) bits (6 bits). As shown in FIG. 1, the circuit includes a selection circuit 93 at the input stage corresponding to the n+f bit registers 6 to 1 and the n+f bit registers 6 to 4 from the top stage, respectively. 91, inputs the output signal of the register 6 at the top stage to one of the corresponding selection circuits 93, and inputs the output signal of the register 6.5 below the top stage to the selection circuit in the input stage of the register at the bottom stage. Each of the r-bit registers 3 to 1 which is input to one of the circuits 92 and 91 and which is not provided with the selection circuit is configured to input an output signal from the register one level above. The n-bit valid data is input to the n-bit registers 6-4 through the other input section of the selection circuits 93-91 in the input stages of the n-bit registers 6-4, and then the selection circuit 93 ~
91 is selectively driven so as to input the output signal of each of the registers 6.5, and the clock for a predetermined number of shifts is applied to the n+l bit registers 6 to 1 by the signal indicating the shift amount.
The configuration is such that data is converted by giving it to .

[Operation] Converts the effective n-bit signal to A2. Referring to FIG. 1, in which 3 bits of AI and AO are used, the shift amount is 2 bits, and the 2 bits to be extended are 3 bits, each of the FFIs to 6 is cleared in advance by the clearing means 82.

Then, the shift means 83 inputs three clocks to the 6-bit shift registers 0FF6 to 0FF1, and the selector 9
3 to 91, at the time of the first clock, a valid n-bit signal A2. Al and AO are selected, and at the time of subsequent clocks, the selector 93 outputs the output of the highest-order FF6, and the selectors 92 and 91 output a selection signal for selecting the output of the higher-order FF.

Then, FF6. FF5. Output of FF4 Y5°Y4. Y
A2 is output from 3, AI is output from the output Y2 of FF3, AO is output from the output Y1 of FF2, and O is output from the output YO of FFI, thereby outputting desired 6-bit fixed-point representation data.

In this circuit, when the data length to be expanded increases by, for example, 1 bit, the FFO may be increased and wiring similar to FFI may be provided. That is, even if the expanded data length becomes longer, the increase in circuit scale and wiring is small.

〔Example〕

FIG. 2 is a circuit diagram of a data conversion circuit according to an embodiment of the present invention, and FIG. 3 is a time chart of each part of FIG.

In the figure, 1 to 12 are FF registers, 91 to 95 are selectors, 30 is a 4-bit counter, 31 to 37 are NOT circuits, 38.39 is an AND circuit, 40 is a NOR circuit, 81 is a 12-bit shift register, 82 83 shows a clear circuit, and 83 shows a shift circuit.

Since it is a 12-bit fixed decimal point display, 12 items are OFF.
Since the valid data is 5 bits, the 12-bit shift register 81 has five selectors 91 to 95, and the valid data A4 . A3. A2゜AI, AO selector 95-91
The selector 95 receives the output of the highest-order FF 12, and the selectors 94-91 receive the outputs of the higher-order FFs, so that they are selected by a select signal and input to the FFs 12-8.

The clear circuit 82 outputs a pulse, and the FF12
.about.l is cleared, and the set value of the 4-bit counter 30 of the shift circuit 83 is preset.

In the shift circuit 83, a signal BO indicating the shift amount.

Since Bl and B2 are 3 bits, 4 bit counter 3
0 is used, BO, Bl, and B2 are input to preset terminals A, B, and C via knot circuits 31 to 33, and "1" is input to the preset terminals (.

In this way, when the shift amount is 3, 11 is preset, and when the 4-bit counter 30 counts 4 clocks, it becomes a carrier load and outputs a carrier signal.

A clock as shown in Fig. 3 (CKO) is input to the 4-bit counter 30, and when a load pulse as shown in Fig. 3 (inverted LD) is input to the load terminal, the output of the 4-bit counter 30 is As shown in Figure 3 (Q), 11.
12, 13, 14.degree. 15, and from the carrier terminal, as shown in FIG.

Further, the AND circuit 38 is input with the clock shown in FIG. The inverted signal shown in FIG. 3 (inverted LD) is input, and the NOR circuit 40 outputs five clocks as shown in FIG. 3 (CK), and the FFI
~12 clocks.

In addition, the signal shown in FIG. 3 (inverted LD) is inverted by the NOT circuit 35, and the level signal shown in FIG. do.

Therefore, at the first clock shown in FIG. 3 (CK), selectors 95 to 91 use the Lebel selection signal to select effective 5 bits A4 to AO with the initial setting shown in FIG. 3 (REG).
When set to F12-8, and thereafter 4 bits, selectors 95-91 select the highest F by a 0-level selection signal.
F12 output.

The output of the upper OFF is selected and shifted by 4 pins.

Therefore, A
4 is output, A4 to AO is output from Y8 to Y4 of the output of FF9 to FF5, and Y3 to Y of the output of FF4 to l
O is output rather than YO.

Therefore, data in a floating point representation with 5 effective bits and a shift amount of 4 bits as shown in FIG. 4(A) is converted to data in a 12-bit fixed point representation as shown in FIG. 4(B). Ru.

In this circuit, even if the data length to be expanded becomes large, F
Since it is sufficient to simply increase F to a lower level, the increase in circuit scale and wiring is small.

〔Effect of the invention〕

As explained in detail above, according to the present invention, when data in floating point representation is converted to data in fixed point representation with a large data length, the increase in circuit size and wiring is small even if the data length becomes large. effective.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram of a data conversion circuit according to an embodiment of the present invention, Fig. 3 is a time chart of each part of Fig. 2, and Fig. 4 is an example of 8 bits. FIG. 5 is a circuit diagram of a conventional data conversion circuit. FIG. 5 is a circuit diagram of a conventional data conversion circuit. In the figure, 1-12 are flip-flops, 30 is a 4-bit counter, 31-37 are NOT circuits, 3B, 39.51-68 are AND circuits, 40 is a NOR circuit, 50 is a decoder, 70-75 are OR circuits, 81 is an (n+f) bit shift register, a 12-bit shift register; 82 is a clear means, a clear circuit; 83 is a shift means, a shift circuit; 91 to 95 are selectors.

Claims (1)

[Claims] In a data conversion circuit that converts floating-point representation data consisting of an effective n-bit signal and a signal indicating a shift amount into fixed-point representation data with a data length of n+l bits, an n+l-bit register ( 6 to 1), and input stages corresponding to the n bit registers (6 to 4) from the top stage among the n+l bit registers (6 to 1), respectively, are provided with selection circuits (93 to 91), respectively. The output signal of the upper register (6) is inputted to one of the corresponding selection circuits (93), and the output signals of the registers (6, 5) below the uppermost stage are sequentially input to the selection circuit at the input stage of the lower register. (92,91
), and each of the l-bit registers (3 to 1) not provided with the selection circuit is configured to receive an output signal from the register one level above, and The bit valid data is stored in the n-bit register (
input to the n-bit register (6-4) through the other input part of the selection circuit (93-91) in the input stage of 6-4), and then the selection circuit (93-91) Data conversion is performed by selectively driving the output signals of each register (6, 5) to be input, and applying a clock for a predetermined number of shifts to the n+l bit registers (6 to 1) using a signal indicating the shift amount. A data conversion circuit featuring: