JPH0322690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a method for planarizing the surface of a semiconductor fabricated into an integrated circuit element, and in particular to a method for planarizing the surface of a semiconductor using the characteristics of a photoresist.

<Prior Art> A semiconductor substrate on which an integrated circuit is built has irregularities on its surface due to an oxide film during circuit creation and conductors such as wiring and electrodes that electrically connect circuit elements. Such surface irregularities are not desirable when manufacturing semiconductor devices having a structure in which wiring is stacked in multiple layers, or laminated integrated circuit elements that are being developed to promote higher density and higher functionality. Flattening is usually performed to smooth out unevenness.

The steps shown in FIGS. 1a to 1d are conventional methods for planarizing the surface of a semiconductor substrate. That is, as shown in FIG. 1a, a semiconductor substrate 1 on which a circuit is built is electrically connected between circuit elements with a conductor 2 such as Al or polysilicon, and an insulating film is formed on the entire surface of the electrically connected semiconductor substrate. 3 for surface protection and electrical insulation. In the state shown in FIG. 1a, the surface of the insulating film 3 has irregularities that approximately correspond to the irregularities occurring on the surface of the semiconductor substrate 1 due to the conductor 2 and the like.

When manufacturing a laminated integrated circuit element, a polycrystalline silicon or amorphous silicon film for manufacturing an upper semiconductor is formed on the lower semiconductor substrate manufactured as described above, and the silicon film is subjected to energy beam annealing or the like. Therefore, it is made into a single crystal and used as a substrate for manufacturing circuit elements. However, the above figure 1a
As shown in Figure 2, depositing the upper semiconductor layer on the insulating film 3 which has irregularities corresponding to the irregularities on the surface of the semiconductor substrate will make the subsequent device manufacturing work extremely difficult and will also reduce the reliability of the device. There is a risk of damage.

As shown in FIG. 1b, the conventional planarization method is to apply a photoresist 4 on the insulating film 3 where the unevenness has appeared, and then to apply the photoresist 4 to the insulating film 3 and the photoresist 4. The entire surface of the resist 4 is etched as shown in FIG. 1c by setting conditions for etching both sides at a constant speed. During the process of coating the photoresist 4, the surface unevenness of the photoresist 4 has been smoothed out compared to the surface of the insulating film 3, and therefore the entire surface is then etched at a constant rate. Thus, the surface of the photoresist 4 is transferred to the insulating film 3 side, and a semiconductor having a relatively flat insulating film is obtained as shown in FIG. 1d.

In the case of the above-mentioned conventional planarization method, the photoresist coated on the insulating film is planarized with almost no minute recesses appearing when the fine pattern is distributed over the entire surface. However, in areas where the pattern is interrupted or where the pattern is coarse, the underlying shape appears on the photoresist surface and the photoresist cannot be flattened. Second
The figure shows the relaxation measurement results of surface irregularities that confirmed the above phenomenon. The measurement sample was prepared by forming conductors with a thickness a and a width w on a semiconductor substrate at intervals of w, as shown in Fig. 3, and coating the semiconductor substrate with a photoresist. . FIG. 2 shows the value of b/a for each value of w, where b is the difference in unevenness produced on the surface of the photoresist after drying treatment. As is clear from the figure, the degree of relaxation of resist unevenness depends on the pattern size, and as the pattern size increases, there is no relaxation of flatness at all.
Irregularities still remain on the surface of the insulating film 3 after the entire surface etching.

In addition, in the conventional method described above, it is necessary to use a sufficiently thick photoresist to flatten the uneven surface, which causes problems such as differences in the resist film thickness distribution and the film thickness on the convex parts after flattening. Ta.

<Objective of the Invention> The present invention has been made in view of the above-mentioned problems in the conventional method for flattening the surface of semiconductor devices, and it is possible to reduce the pattern size of unevenness on the semiconductor surface by effectively utilizing the characteristics of photoresist. It is an object of the present invention to provide a planarization method capable of manufacturing a semiconductor device covered with a planarized insulating film regardless of the structure.

<Example> FIGS. 4a to 4e are cross-sectional views for explaining the steps of an example according to the present invention. As shown in FIG. 1a, while building circuit elements on the semiconductor substrate 1,
Electrically connecting each circuit element with a conductor 2,
The surface is covered with an insulating film 3. In this state, the surface of the insulating film 3 has irregularities corresponding to the irregularities caused by the conductor 2 and the like on the underlying semiconductor substrate 1. Next, a positive resist 5 is applied to the surface of the semiconductor substrate on which the insulating film 3 has been deposited, as shown in FIG. 4a. The surface of the resist after coating also has unevenness corresponding to the above-mentioned unevenness occurring on the surface of the semiconductor substrate 1.

The photoresist film 5 is exposed to ultraviolet light to form a pattern 6 corresponding to the uneven pattern formed on the semiconductor surface as shown in FIG. 4b. The mask pattern 6 for exposure is designed such that the photoresist in areas corresponding to the convex portions on the semiconductor surface is exposed to ultraviolet light. A positive resist has quinonediazide in its molecular structure as shown on the left side of the following formula, and this quinodiazide decomposes when exposed to ultraviolet irradiation, releasing nitrogen gas (N ₂ ) and passing through an intermediate to form the following formula: Changes to indenecarboxylic acid on the right side.

That is, nitrogen gas is separated from the exposed portion of the photoresist. Next, the photoresist film 5 is softened by heating after exposure to ultraviolet rays. The nitrogen gas separated in this process is released from the photoresist, and the volume of the photoresist portion from which the nitrogen gas has escaped is reduced, canceling out the convex portions on the semiconductor surface, and the surface becomes as shown in Figure 4c.
As shown in the figure, the unevenness is evened out and a flat shape is created.
In addition, when the above heat treatment is performed, the surface layer of the unexposed area is hardened at an early stage of the treatment, and the nitrogen inside the resist generated by the heat treatment is not released to the outside but is confined inside. Therefore, there is almost no volume reduction in the unexposed area. The entire surface of the photoresist film whose surface has been flattened is etched as shown in FIG. 4d under conditions that the resist film and the insulating film 3 are etched at a constant rate. Since the surface of the photoresist film has already been almost flattened, as the etching progresses, the insulating film at the convex portions is also scraped off in the same way as the photoresist, and the etched surface after processing becomes a semiconductor layer as shown in Figure 4e. Regardless of surface irregularities, the surface of the photoresist film 6 is transferred and becomes flat.

In particular, the insulating film covering the conductor has the same thickness over almost the entire area on the conductor, preventing local changes in the thickness of the insulating film even when an upper conductor for multilayer wiring is deposited, for example. , to prevent leaks and dielectric breakdown.

A conductor pattern is formed on an insulating film with a flat surface to form a semiconductor device with a multilayer wiring structure, or an amorphous silicon or polycrystalline silicon film is deposited and simplified by laser annealing or the like to form a laminated structure. Used as a semiconductor substrate for circuit elements.

<Effects> According to the present invention, by utilizing the characteristics of the resist material, the entire surface of the semiconductor substrate can be highly planarized, and the thickness of the insulating film on the convex portions of the conductor etc. can be reduced. It becomes uniform regardless of the pattern size, and does not cause local dielectric breakdown when used as an interlayer insulating film of multilayer wiring. Furthermore, it is a practical planarization method that can use a commonly used positive type resist and does not pose the risk of complicating the process.

[Brief explanation of the drawing]

Figures 1 a to d are cross-sectional views for explaining the conventional planarization method, Figure 2 is a diagram showing the degree of relaxation of surface irregularities, and Figure 3 is a diagram showing dimensional relationships for explaining Figure 2. , and FIGS. 4a to 4e are cross-sectional views for explaining the steps of an embodiment of the present invention. 1: semiconductor substrate, 2: conductor, 3: insulating film,
5: Positive photoresist film, 6: Mask pattern.

Claims (1)

[Claims] 1. A step of forming an insulating film to be flattened on a semiconductor surface whose surface is uneven due to a conductor, etc., and a step of applying a positive resist on the insulating film. , selectively irradiating the resist above the protrusions on the semiconductor surface with light, and heat-treating after the irradiation to cause a volume change in the exposed portion above the protrusions and the unexposed portion above the concave portions, thereby reducing the protrusions. A step of substantially flattening the resist surface by reducing the upper resist volume, and a step of uniformly etching the resist from the surface to the insulating film, forming a substantially flat insulating film surface. A method for planarizing a semiconductor device, characterized in that: