JPH0323035B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to digital signal processing in video cameras.

Conventional Structure and Problems Conventionally, video camera signal processing has been analog signal processing, but advances in semiconductor technology have made it possible to perform digital signal processing.

A color video camera using a single-chip solid-state image sensor in which conventional analog signal processing is digitized will be described below.

FIG. 1 shows a mosaic filter placed on the light receiving elements of a solid-state image sensor, with a filter of one color placed on each light receiving element. The color arrangement of the filter shown in FIG. 1 will be explained. A transparent (W) and green (G) filter is arranged on the nth horizontal line of a certain field, and a cyan (C _Y ) and yellow (Ye) filter is arranged on the n+1th horizontal line.
Green (G) and transparent (W) filters are placed on the n'th horizontal line of the next field, and yellow (Ye) and cyan (C _Y ) filters are placed on the n'+1th horizontal line. Ru.

Figure 2 shows a specific example of a color video camera using a solid-state image sensor with the mosaic filter shown in Figure 1. 1 is a solid-state image sensor that converts the photoelectrically converted electric signal for each pixel into a driving pulse. Read out sequentially. 2 is an A/D converter that converts the output signal of the solid-state image sensor 1 into a digital signal. 3 causes a delay of 1 horizontal scanning period and 1 HDL, and 4
A signal obtained by delaying the original signal by one horizontal scanning period and the original signal are input to the synchronization circuit. It is separated into four color components W, G, Ye, and _CY by the four simultaneous circuits. 5 is a matrix and gain adjustment circuit, W, G,
Red (R), green (G), and blue (B) are matrixed from _Ye and CY to obtain output signals R ₀ , G ₀ , and B ₀ whose gains are adjusted to obtain white balance.
The matrix formula is R=(W-C _Y )+(Ye-G)/2 B=(W-Ye)+(C _Y -G)/2 G=(W+G)+(Ye+C _Y )-2R-2B /4.

6 is a gamma correction circuit that receives input signals of three primary colors R ₀ ,
For G ₀ and B ₀ , outputs of R ₀ ^0.45 , G ₀ ^0.45 , and B ₀ ^0.45 are obtained.

7 is a matrix circuit, which receives the luminance signal Y ₀ (Y ₀ =
0.3R ₀ ^0.45 +0.6G ₀ ^0.45 +0.1B ^0.45 ) and color difference signal C ₁ (C ₁
= R ₀ ^0.45 − Y ₀ ), C ₂ (C ₂ = B ^0.45 − Y ₀ ), obtain the encoded signal with encoder 8, and convert the digital signal to an analog signal with D/A 9. to make it a standard television signal. Generally, when a signal having the frequency band of a video signal is digitized and processed, parallel processing is performed. Further, a fully parallel type A/D converter is used. Therefore, with an 8-bit A/D, the comparator is 256
If you make this into 9 bits, it becomes 512 pieces, and
It becomes 1024 pieces to make it 10 bits. If the number of bits per bit is increased, twice as many comparators are required, so it is necessary to use an A/D with as few bits as possible. For example, if a 9-bit A/D converter is used and the highest value of the signal in the transparent W section is 9 bits, then red (R) is approximately 3/7 of the width of W, and blue (B) is approximately 3/7 of the amplitude of W.
The width is about 1/7. Therefore, the number of red bits is
7.7 bits, and the number of blue bits is 6.2 bits. If this is corrected by γ, it will decrease by at least 1.5 bits. In addition, the number of red bits is 6.2 bits, and the number of blue bits is 4.7 bits. The number of color bits is required to be 6 or more.

For this purpose, a 10-bit A/D converter is required. This required 1024 comparators, which resulted in very high cost and high power consumption.

Purpose of the Invention The present invention solves the above-mentioned conventional problems.
The purpose of this invention is to substantially improve the A/D converter by one bit without increasing the number of bits.

Structure of the Invention The present invention obtains an electric signal photoelectrically converted by a solid-state image sensor, and connects the solid-state image sensor between the reference voltage of an A/D converter and the electric signal by fc/2n (n: an integer of 1 or more, fc: the solid-state image sensor). An offset signal having an amplitude change equivalent to 1/2 LSB of the A/D converter at a frequency (horizontal readout frequency of pixels of the image sensor) is added to the reference voltage of the A/D converter, or an offset signal is added to the reference voltage of the A/D converter, or The A/D converter converts the sum into a digital signal, and inputs the digital signal to a digital circuit that removes the frequency of fc/2n and a digital circuit with opposite characteristics to the digital circuit with opposite characteristics. By inputting the low level output signal of the digital circuit to the clip circuit, removing the added offset signal, and adding the output signal of the digital circuit that removes the frequency of fc/2n and the output signal of the clip circuit, 1 bit can be obtained. By increasing the bit accuracy by a considerable amount, the number of bits in the A/D converter can be reduced, resulting in lower cost and lower power consumption.

DESCRIPTION OF THE EMBODIMENTS The improvement in bit accuracy when a 1/2 LSB offset signal is added to the comparator voltage of the A/D converter will be explained using FIG.

Reference numeral 41 in FIG. 9 is an output signal from the image sensor, which is A/D converted using a comparator voltage 43, and becomes a signal 42 when D/A converted. Next, when an offset voltage of 1/2LSB is applied to the comparator voltage of 43, the comparator voltage of 45 becomes. Now 41
When the signal is A/D converted and D/A converted, 4
It becomes a signal of 4. When the signals 42 and 44 are added as digital signals and subjected to D/A conversion, a signal 45 is obtained. In this way, the bit accuracy is improved by the equivalent of one bit.

However, since the offset signal is added to the uniform signal, the offset signal becomes an interfering signal. Therefore, the A/D converted electric signal is input to a digital circuit that removes the repetition frequency of the offset signal and a digital circuit with the opposite characteristics of the digital circuit, and the low level output signal of the digital circuit with the opposite characteristics is input to the clip circuit. By removing the input and added offset signal and adding the output signal of the digital circuit that removes the repetition frequency of the offset signal and the output signal of the clip circuit, the offset signal is removed and a signal with improved bit accuracy is obtained. .

FIG. 3 is a block diagram of signal processing of a solid-state imaging color video camera using the block filter of FIG. 1, which is a first embodiment of the present invention. In FIG. 3, 1 solid-state image sensor, 2 A/D converters,
3 1HDL, 4 simultaneous circuit, 5 matrix, 6 gamma correction circuit, 8 encoder, 9 D/
The A converter is identical to that of FIG. 1 and operates in the same manner. An offset is applied to the signal obtained from the solid-state image sensor 1 using 10 adders. An offset of 1/2LSB is given for each signal corresponding to two pixels, for example, W and G signals. Then, the phase is inverted for each horizontal scanning line. In other words, if the readout clock frequency of the solid-state image sensor is fc, the repetition frequency of each color, for example, W, is
Take fc/2. To avoid adversely affecting the color, use fc/
Add an offset signal with a frequency of 4 and an amplitude of 1/2 LSB. This signal is converted into a digital signal by A/D converter 2, and a signal obtained by delaying the original signal by one horizontal period is obtained by HDL 3. 11 and 12 are low-pass filters LPF, which remove the frequency of fc/4 and obtain the original signal with improved bit precision by 1 bit and a signal delayed by 1 horizontal period from the original signal.
Separate into G, Ye, C _Y colors. Matrix 5 and γ correction circuit 6 calculate R ₀ ^0.45 , G ₀ ^0.45 ,
We get a signal of B ₀ ^0.45 .

Since these signals are band-limited by the LPFs 11 and 12, the color difference signals C ₁ and
_C2 is obtained, and the adder 17 adds the high-passed high-frequency signal of the luminance signal and the three primary color signals to obtain a luminance signal. 13 is a circuit that adds the original signal and the signal delayed by one horizontal period; when there is a vertical correlation between the signals for each horizontal line, the c/4 offset signal is removed and the precision is improved by one bit. If the signals for each horizontal line have no vertical correlation, the c/4 offset signal is not removed. The high-pass filter 14 is a filter that passes the offset signal, and the low-pass filter 21 is a filter that removes the offset signal. The frequency characteristics of the original signal are restored using the 22 adders. 19 is
A difference signal between the outputs of the LPFs 11 and 12 is obtained, and the vertical correlation of the signals is detected. When there is vertical correlation, the difference output of 19 becomes zero. When there is a difference output of 19
1LSB of A/D converter of output signal of HPF14
15 clip circuits clip only the change in the signal, and remove the c/4 offset signal. 20 is an adder for obtaining a luminance signal, 0.6G ₀ ^0.45 +
Get 0.3R ₀ ^0.45 +0.1B ^0.45 . This signal is added to adder 2
A γ circuit that controls the gain at the level of the output signal of 0 performs γ correction, and an adder 17 adds it to the output signal of the adder 20 to obtain a luminance signal Y whose high frequency components have been corrected. Using this luminance signal Y and color difference signals C ₁ and C ₂ , 8
The signal is encoded by an encoder, and converted into an analog signal by a D/A converter 9 to obtain a standard television signal.

FIG. 5 is a block diagram of a second embodiment of the present invention, which is a color video camera using a solid-state image pickup device in which a mosaic filter as shown in FIG. 4 is arranged. The mosaic filter shown in FIG. 4 repeats red (R), green (G), and blue (B), and assuming that the readout clock frequency of the solid-state image sensor is c, the repetition frequency of each color is c/3. 10 is an adder for adding offset signals, which adds offset signals having a frequency of c/2 or c/6 and an amplitude of 1/2 LSB.

When an offset signal with a frequency of c/2 is added to the R, G, B, R, G, B... signals read from the solid-state image sensor, GRB... (,, is the signal to which the offset signal has been added) is obtained. . That is, for each color signal, it is equivalent to adding an offset signal of a frequency of c/6. Adding the c/6 offset signal gives RGBR,
C, B... The signal obtained by adding this offset signal is converted into a digital signal by A/D converter 2, and +R, G+, +
The B signal is obtained, the offset signal is removed, and the bit precision is improved. The HPF 14 and the clip circuit 15 obtain a high frequency signal from which the offset signal has been removed. This signal is added to the output signal of the LPF 11 by an adder 21. In the color separation circuit 22, R, G, B
The three primary color signals are separated into three primary color signals R ₀ , G ₀ , and B ₀ with white balance. γ correction circuit 6,
After passing through a matrix 7, an encoder 8, and a D/A converter 9, it becomes a standard television signal.

FIG. 6 is a third embodiment of the present invention, which is a block diagram of a process for improving the bit precision of a black and white video camera. 25 is a solid-state image pickup device that reads out electrical signals photoelectrically converted at clock frequency c. 26 is an adder that adds half the amplitude of the LSB of the A/D converter 27 at a frequency of c/2. Reference numeral 28 denotes a delay device (DL) that delays the period _Tc of one clock, and this delay device and the adder 29 are combined to form a low-pass filter.
Such an LPF, in combination with 28 delays and 30 subtractors, constitutes a high-pass filter,
The HPF has frequency characteristics such as 8-b and 8-b in FIG. 31 is a clip circuit that clips the error signal resulting from digitization, and ±
Set all 1LSB signals to 0. 32 is an adder which obtains a signal with improved bit precision of the low frequency signal.

Next, a case where an image of a subject whose light amount is changing with a gentle slope will be described using FIG. 7. In FIG. 7, 41 is an output signal of the image pickup device, and 42 is a signal obtained by reproducing a signal digitized by an A/D converter and also by a D/A converter. The broken line 43 indicates the digitized signal.
This is a signal that has been smoothed with an LPF and then reproduced with a D/A converter. When capturing an image of a subject that changes slowly like this, the LPF cannot improve the bit accuracy. The signal 44 is reproduced by applying a 1/2LSB offset at the timing indicated by the arrow 48. A signal obtained by delaying that signal is shown at 45. Adding these two signals results in 46 signals, which shows that the bit precision has improved by 1 bit. 47 is a differential signal between signals 44 and 45, and an error of 1LSB occurs, but since this is reduced to 0 by a clip circuit, no error occurs. In this way, the bit precision of the low frequency signal increases, while the precision of the high frequency signal decreases. However, the accuracy of high-frequency signals can be improved by passing them through the LPF, so there is no problem.

Note that in the first embodiment, the offset frequency is set to c/4. However, c/4n (n: an integer of 1 or more) may be used.

Further, in the second embodiment, the offset frequencies were set to c/2 and c/6, but they may also be set to c/2 and c/6n (n: an integer of 1 or more).

Further, although the offset frequency was set to c/2 in the third embodiment, it may be set to c/2n (n: an integer of 1 or more). Furthermore, although a signal from a solid-state image pickup device is used, the same method can be applied to a signal obtained by sampling an electrical signal obtained from an image pickup tube using clock c.

Effects of the Invention As described above, according to the present invention, without increasing the number of bits of the A/D converter, with a simple configuration,
Bit precision can be improved, and cost and power consumption can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a mosaic filter for a solid-state image sensor, Fig. 2 is a block diagram of a conventional signal processing device using a solid-state image sensor equipped with the mosaic filter shown in Fig. 1, and Fig. 3 is a diagram similar to that shown in Fig. 1. FIG. 4 is a block diagram of a signal processing section of a digital camera according to the first embodiment of the present invention using a solid-state image sensor with a mosaic filter arranged therein. Fig. 5 is a block diagram of the signal processing section of a digital camera according to the second embodiment of the present invention, which uses a solid-state image sensor equipped with the mosaic filter shown in Fig. 4, and Fig. 6 shows a block diagram of a signal processing section of a digital camera using a solid-state image sensor equipped with the mosaic filter shown in Fig. 4. A block diagram of the signal processing section of a digital camera according to the third embodiment of the present invention, FIG. 7 is a diagram for explaining the process of improving the bit accuracy of the digital camera, and FIG. 8 is a diagram for explaining the camera. The frequency characteristic diagram, FIG. 9, is an explanatory diagram of the improvement in bit accuracy when an offset voltage is added to the comparator voltage of the A/D converter. 1...Solid-state image sensor, 2...A/D converter, 3...1
1HDL to delay the horizontal period, 4...synchronization circuit for color separation, 10...to improve bit accuracy
Adders for adding OFFSET signals, 11, 12...
LPF (low pass filter), 14... HPF (high pass filter), 15... clip circuit for removing error signals generated in the LSB of the A/D converter.

Claims (1)

[Claims] 1. Obtain an electrical signal photoelectrically converted by a solid-state image sensor, and connect fc/2n (n: an integer of 1 or more, fc: the above-mentioned providing an offset signal having an amplitude change smaller than the amplitude of the lowest bit of the A/D converter at a frequency (horizontal readout frequency of pixels of a solid-state image sensor);
A digital circuit that converts a signal equivalently added to the offset signal and the electrical signal into a digital signal by the A/D converter, and removes a frequency of fc/2n from the digital signal, and a circuit that passes the offset signal. , the output signal of the pass circuit is input to a low-level clip circuit, and the output signal of the digital circuit for removing the fc/2n frequency is added to the output signal of the clip circuit. camera. 2. The digital camera according to claim 1, wherein the offset signal phase is changed for each horizontal scanning line. 3. The digital camera according to claim 1, wherein the digital circuit for removing the frequency of fc/2n is composed of a low-pass filter, and the circuit for passing the offset signal is composed of a band-pass filter. 4 Obtain an electric signal photoelectrically converted by a solid-state image sensor in which two different color filters are arranged horizontally alternately for each pixel, and apply fc/ 2n (n: an integer of 1 or more,
fc: horizontal readout frequency of pixels of the solid-state image sensor)
An offset signal having an amplitude change smaller than the amplitude of the lowest bit of the A/D converter is applied at a frequency of The digital signal is input to a digital circuit that removes the frequency of fc/2n and a digital circuit with the opposite characteristic of the digital circuit, the output signal of the digital circuit with the opposite characteristic is input to a low-level clip circuit, and the A digital camera characterized in that an output signal of a digital circuit that removes a frequency of fc/2n and an output signal of the clip circuit are added.