JPH03230610A - comparator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a comparator constructed of a semiconductor integrated circuit and capable of high-speed operation.

[Conventional technology]

FIG. 3 is a circuit diagram of a comparator using well-known bipolar transistors. In FIG. 3, bipolar transistor T1. T2 has its emitter in common and is connected to the collector of bipolar transistor T5. The load resistance R1°R2 is connected to the power supply 10 and the bipolar transistor T1. It is connected between T2. The differential input terminals 11, 12 are each bipolar transistor TI
, connected to the base of T2. Bipolar transistor T3. The bases of T4 are connected to the collectors of other bipolar transistors T4゜T3,
It is further connected to a load resistor RIR2, and its emitters are commonly connected to the collector of a bipolar transistor T6.

Bipolar transistor T5. The emitters of T6 are commonly connected to current source ■1, and the base of each is connected to a complementary US
A signal is given! 1III terminals 15°16 are connected.

In the conventional comparator configured as described above, the human input signal is transmitted through a pair of bipolar transistors T1. It is amplified by T2 and the output voltage appears at load resistor RIR2. Since the bipolar transistors T3 and T4 are connected to each other so as to provide positive feedback, they amplify and maintain the magnitude relationship between the voltages applied to the load resistors R1 and R2. Furthermore, bipolar transistor T5. T6 is a bipolar transistor T1. Amplification operation by T2 and bipolar transistor T3. The operation is selected between the holding operation by T4 and the holding operation by the respective bipolar transistors T5. It is controlled by which of T6 it is sent to.

[Problem to be solved by the invention]

However, in the above configuration, the number of transistors to configure the comparator is large, and the paths of the bipolar transistors TI and T2 and the bipolar transistors T3 . Since the current is switched to the path of T4, the switching signal is connected to the differential input terminals 11 and 12.
Noise was added, making it difficult to make highly accurate comparisons.

An object of the present invention is to provide a comparator with high accuracy, high speed, and simple construction.

[Means to solve the problem]

The comparator of the present invention connects the emitters of the first and second bipolar transistors in common, connects the differential input terminal to the bases of the first and second bipolar transistors, and connects the emitters of the first and second bipolar transistors in common. The collectors of the two bipolar transistors are connected to the IT source through the sources and drains of the first and second MOS transistors, respectively, and the gates of the first and second MOS transistors are connected to the drains of the other MOS transistors. A third MOS transistor is connected between the drains of the first and second MOS transistors.
It is connected with a MOS transistor.

[For production]

In the comparator configured as described above, the input voltage is amplified by the first and second bipolar transistors, and the input voltage is further amplified and held by the first and second MOS transistors which apply positive feedback. In addition, the first and second MOS
The held state is released by a third MOS transistor that connects the drains of the transistors, and the input voltages are newly compared.

〔Example〕

FIG. 1 shows the structure of a comparator according to a first embodiment of the present invention. In FIG. 1, T1 and T2 are bipolar transistors (first and second bipolar transistors) forming a differential pair, and are connected to a current source 1 with their emitters in common. 11 and 12 are differential input terminals, each of which is a bipolar transistor T.
1. Connected to the base of T2. Pl and R2 are P
Channel MO3 transistor (first and second MOS
The gates of each MOS transistor are connected to the drains of the other MOS transistor, and the sources and drains of each are connected to the power supply 10 and the collectors of the bipolar transistors TI and T2, respectively. An N-channel MOS transistor Nl (third MO
The source and drain of the S transistor) are connected. 1
3 is a control terminal, which is an N-channel MOS transistor N
Connected to gate 1.

Regarding the comparator of this embodiment configured as above,
The operation will be explained below.

When the potential of the differential input terminal 11 is higher than the potential of the differential input terminal 12, the bipolar transistor T1 conducts and lowers the potential of the collector. As a result, the gate potential of the P-channel MO3 transistor P2 decreases, so the resistance between the source and drain decreases, and the gate potential of the P-channel MO3I-transistor P1 increases. Therefore, the resistance between the source and drain of P-channel MOS transistor P1 increases, and P-channel MOS transistor P2
further lower the gate potential.

In this way, two P-channel MO3 transistors Pl
, P2, so that the magnitude relationship at a certain point in time can be maintained. Furthermore, high-speed comparison can be performed even when the difference in input voltage is small.

On the other hand, by making the N-channel MOS transistor N1 conductive, the magnitude relationship held by the P-channel MO3 transistors PI and P2 can be released, and a new comparison of 1! Get ready.

At this time, the voltage between the gate and source/drain of the N-channel MOS transistor Nl does not greatly exceed the threshold voltage VT of the N-channel MOS transistor Nl;
The potential of the source and drain of the channel MOS transistor Nl, that is, the bipolar transistor T1. Since the collector potential of T2 is held at a voltage that is lower than the gate potential of N-channel MOS transistor N1 by the threshold voltage VT, by appropriately applying the gate potential of N-channel MOS transistor N1, bipolar transistors T1. It is possible to prevent the collector potential of T2 from dropping too much unnecessarily, and the output amplitude can be controlled.

Furthermore, bipolar transistor T1. Since the emitter current of T2 is not interrupted, the differential input terminal 11.
No switching noise is added to 12, making it possible to perform highly accurate comparisons.

FIG. 2 shows the structure of a comparator according to a second embodiment of the invention. In this embodiment, P channel MOS transistors Pi, P2 are connected in parallel with other P channel MO3 transistors P3. Connect P4 and control those gates.
By assigning the first place, the comparison and retention operations are controlled in the same way as in the embodiment described above. Also, as shown in FIG. 2, bipolar transistor T1. T2 are connected to P-channel MOS transistors P1.T2 through the sources and drains of other N-channel MOS transistors N2. By connecting it to the drain of P2, the collector potential is prevented from dropping too much.

P-channel MO3 transistor P3. connected in parallel with the above-mentioned P-channel MO3 transistor PIP2. P4 is 1iai from a circuit perspective.

are connected in series through the input terminals of the P channel M
The structure is such that the drains of the oS transistors Pl and P2 are connected, and like the N-channel MOS transistor N1 in the embodiment of FIG. 1, it corresponds to the third MOS transistor in the claims.

Other functions and effects are the same as those of the embodiment shown in FIG.

Note that the same operation can be obtained by making the P-type and N-type all complementary.

[Effects of the Invention] According to the comparator of the present invention, the first and second MOS transistors are connected to the first and second bipolar transistors forming a pair, respectively.
The transistors are connected in series, the third MOS transistor is connected between the drains of the first and second MOS transistors, and the first and second MO3I-transistors are connected so that positive feedback is applied, so the number of transistors can be reduced. There is no switching of the current path between the comparison operation and the protection operation, so there is no switching noise, and high-accuracy and high-speed comparison can be performed with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a comparator according to the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the comparator according to the second embodiment of the present invention, and FIG. FIG. 3 is a circuit diagram of a comparator. 11.12...Input terminal, 13...Control terminal, Tl
. T2...Bipolar transistor, PL, P2P3
．． P4...P channel MoS transistor, Nl, N
2. N3...N channel MOS transistor, +1.
...Current source diagram! '=1 Figure

Claims (1)

[Claims] emitters of first and second bipolar transistors are connected in common, differential input terminals are connected to bases of the first and second bipolar transistors, respectively;
The collectors of the first and second bipolar transistors are connected to the sources of the first and second MOS transistors.
The gates of the first and second MOS transistors are connected to the power supply through the drains thereof, and the gates of the first and second MOS transistors are connected to the other MOS transistors.
connected to the drain of the transistor, and the first and second
A comparator characterized in that the drains of the MOS transistors are connected by a third MOS transistor.