JPH0323743A - Signal system detector - Google Patents

Abstract

PURPOSE:To detect a specific signal system even in fast digital transmission by performing the sampling of the output of a synchronization detector, expressing a sample value as a phase value, and detecting the fact that the change of the phase value is always kept constant at every symbol. CONSTITUTION:The device is equipped with a sample/phase converter 4 which generates a clock having a frequency equivalent to a symbol rate and performs the A/D conversion of the I-channel signal and the Q-channel signal of a demodulated signal and expresses the sample output of those signals as the phase values. And also, it is equipped with a comparator 7 which subtracts the output in which the sample output is delayed by one symbol from the output from the sample/phase converter 4, and compares the output with a reference value. The input of the specific signal system can be detected by setting the reference value at an appropriate value and detecting the coincidence of the output of a subtractor 6 with the reference value extending over continuous symbols. In such a manner, it is possible to demodulate transmission information and to detect the specific signal system even in fast digital communication.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal sequence detection device. especially. The present invention relates to a device for detecting a specific signal sequence such as a preamble from a digital angle modulated wave capable of synchronous detection such as an MSK method in a time division multiple access (TDMA) communication method under a multiple propagation path environment.

As is well known, in the TDMA communication system, transmitted and received waves are burst-shaped. In order to receive such a burst-like received wave, a preamble is provided in the received wave before the transmission information containing the data to be actually transmitted. That is, by detecting this preamble, the receiving section of each station recognizes the arrival of the received wave and demodulates the data contained in the received wave. or. Generally, the demodulated signal obtained by synchronously detecting (demodulating) this received wave is. It includes an in-phase component (■ channel signal) and a quadrature component (Q channel signal). Therefore, this demodulated signal is called a signal vector.

[Conventional technology] Conventional. This type of signal sequence detection device is shown in Figure 3. Clock regeneration circuit 101 and . It consists of a signal reproducing circuit 102 and a comparison circuit 103.

The clock recovery circuit 101 performs clock recovery from the 1-channel signal and the Q-channel signal of the demodulated signal. The signal regeneration circuit 102 is . I-channel signal of the signal demodulated at the optimal decision point using the recovered clock. Judgment is made for each Q channel signal. Play data.

The comparison circuit 103 is . The sequence reproduced by the signal reproducing circuit 102 and the specific signal sequence to be detected are compared. When the comparison circuit 103 detects that the signal sequences match, a specific signal sequence is detected.

[Problems to be Solved by the Invention] The conventional signal sequence detection device described above is not suitable for high-speed digital communication. Due to the influence of propagation delay, not only the preamble but also the transmitted information may not be correctly demodulated.

The following will explain the MSK method as an example of the modulation method. The MSK wave is. As is well known, cosφ(t)eosω
It is expressed as ct+s1nφ(t)slnωat. Here, ωC is the angular frequency of the carrier wave, and cosφ(t
)． sinφ(1) is the in-phase component and quadrature component of the input signal, respectively, and φ(1) is the phase of the signal vector.

For the direct wave of the MSK wave, time t. The delayed wave with amplitude ratio a delayed by . a eOsφ(t-to)cosωc
(t-to) +a sinφ(t-to)si
It is expressed as nωc (t-to). Therefore, the wave (superimposed wave) in which the direct wave and delayed wave are superimposed is [cosφ(L) + a cos(φ(t-to
) - ωeta)] cos ωct+ [sinφ(t)
+ a s1n(φ(t-to)-ωe to)
] s1n ωet.

This will be explained below using drawings. FIG. 4 shows an example in which a signal obtained by synchronously detecting an MSK wave is sampled using a clock synchronized with a symbol. In the figure, the ■ axis indicates the in-phase component, and the Q axis indicates the orthogonal component. The signal locus of the MSK wave changes on the circumference, and naturally the sample values also lie on this circumference. The phase of the signal vector of the MSK wave is expressed as the symbol ′
When ``1'' is entered manually, it changes by (π/2), and when ``0'' is input, it changes by (1 π/2). Therefore, if we sample with a clock synchronized with the symbol, the result shown in Figure 3(a) will change. The sampled signal must be fixed at a fixed position, as shown by the circle.However, it is affected by the propagation delay of multiple propagation paths, and when a wave in which the direct wave and delayed wave are superimposed is sampled. .The sample value no longer exists at a fixed position on the circumference.

Figure 4(b) shows "1101" based on the position of point 21.
This is an example in which the signal sequence "000" is sampled by a superimposed MSK wave direct wave and delayed wave with a clock synchronized with the symbol.The white circle is an example of only the direct wave.21→22
The vector transitions in the order of →23-422 →23 →22 →21 →24. The black circle mark is (cos ωc to,
sin ωc to )− (J] “/ 2.−J
- “/ 2), a-J] “/ 2, to = T (1/
T is an example of a wave superimposed with a delayed wave where T is the symbol rate). For example, when the direct wave transitions from 21 to 22,
At the timing of point 22. Point 2 on the direct wave vector
The direct wave vector at timing 1 is ωe 't
The vector 25 of the superimposed wave is obtained by rotating it by O and adding the result multiplied by a. Similarly, the vector changes in the order of 25→27→26→27→26→29→28. As in this example, when the delay is longer than the sampling interval and the amplitude of the delayed wave is large,
It is difficult to reproduce data correctly.

If the data cannot be reproduced correctly in this way, there is a drawback that the preamble cannot be detected.

Furthermore, in order to compensate for this drawback caused by intersymbol interference in multiple propagation paths, a device called a transmission path equalizer has been conventionally employed. However, even if data can be reproduced correctly using this device, there is a problem in that it takes time to detect a specific signal sequence.

Furthermore, even when there is no effect of propagation delay, conventional devices perform clock recovery, which has the disadvantage that data cannot be correctly recovered unless a stable clock is obtained.

[Means for Solving the Problems] A signal sequence detection device according to the present invention samples the phase of a signal vector at a sampling rate equal to the symbol rate over a finite number of consecutive symbols. By detecting that the phase difference between a certain phase value and the phase value one symbol before becomes a predetermined phase difference,
This is a device that detects a specific signal sequence.

In order to detect this specific signal sequence, the signal sequence detection device according to the present invention includes a clock generator that generates a clock having a frequency equal to the symbol rate, and a clock generator that generates a clock having a frequency equal to the symbol rate. Channel signal and Q
An A/D converter for A/D converting each channel signal, a sample/phase converter for representing the sample output from the A/D converter as a phase value, and a sample/phase converter for expressing the sample output from the A/D converter as a phase value. A delay device that delays the output by one symbol. It consists of a subtracter that subtracts the output of the delay device from the output from the sample/phase converter, and a comparator that compares the output of the subtracter with a reference value, and sets the reference value to an appropriate value. , by detecting that the output of the subtracter and the reference value match over consecutive symbols, it is detected that a specific signal sequence has been input. The signal sequence to be detected is not an arbitrary signal sequence. Select a signal sequence that is not affected by propagation delay.

By having the above-mentioned means, the problem of the conventional method is solved, and the present invention is characterized in that it does not require clock recovery or transmission line equalization. here. A signal sequence that is not affected by propagation delay refers to a signal sequence in which changes in the phase of a signal vector obtained by synchronously detecting a modulated wave at each sampling time interval T are always equal.

The principle of the present invention will be explained below with reference to FIGS. 5 and 6.

First, referring to Figure 5, similar to Figure 4, it is a sequence in which the signal vector obtained by synchronously detecting the MSK wave is sampled with a clock synchronized with the symbol, and the white circles are examples of only direct waves. There is a black circle mark. (eosωCto, sinω
eto) - (J7/2, -J″T/2
). This is an example of a wave in which delayed waves such as a-IT/2, t6-T are superimposed, and (a) is the case where the signal sequence is all symbols “1”, and (b) is the case where all the symbols are “0”. .

In Figure 5(a), the signal vector of the direct wave is 31→
When transitioning counterclockwise in the order of 32 → 33 → 34 → 31, the signal vector of the superimposed wave is 35 → 36 → 37 → 3
Transitions counterclockwise in the order of 8 → 35. In this way, if the change in phase of the direct wave signal vector and the change in phase of the delayed wave signal vector are always equal. The change in phase of the signal vector of the superimposed wave is also always the same.

Similarly, regarding FIG. 5(b), for the clockwise transition of the signal vector of the direct wave from 41 → 44 → 43 → 42 → 4], the signal vector of the superimposed wave changes from 45 → 48 → 47 →
It exhibits a clockwise transition of 46→45.

Figure 6 is similar to Figure 4. Unlike the case in Figure 5, the signal vector obtained by synchronously detecting the MSK wave is sampled using a clock whose frequency is slightly different from the clock synchronized with the symbol, and is displayed over a short period of time. , the signal sequence is all symbol "1°".The signal vector of the direct wave transitions counterclockwise in the order of 51 → 52 → 53 → 54 → 51, but since the sampling clock is not synchronized with the symbol. , the sample value is I
, does not exist on the Q axis. Also. As time passes, the sample values slowly move around the circumference. However, the change in the phase of the signal vector for each sample time interval T is always (
π/2). It appears to be fixed at four points on the I-Q plane.

Therefore, the signal vector of the superimposed wave is also 55→56−h5
7-58→55 in a counterclockwise direction, and the rate of change in the phase of the signal vector for each sampling time interval T is always (π/2). The same is true when the signal sequence is all symbols '0'', and the phase change of the signal vector at each sampling time interval T is always (1π/2).

As explained above, if the changes in the phase of the direct wave signal vector obtained by periodic detection of the modulated wave are always the same for each sampling time interval T, then the changes in the phase of the superimposed wave signal vector are also always the same. Furthermore, since only the phase change is focused, even if the sampling clock is not completely synchronized with the symbol, it is sufficient that the frequency can be synchronized within a certain accuracy.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a signal sequence detection device according to an embodiment of the present invention.

The outputs of the synchronous detector (not shown), that is, the 1-channel signal and the Q-channel signal, are sent to the A/D converter 1 and A/D converter 1, respectively.
It is input to converter 2. The output terminals of A/D converter 1 and A/D converter 2 are . It is connected to two input terminals of the sample/phase converter 4.

The output terminal of the sample/phase converter 4 is connected to one input terminal of a delay device 5 and a subtractor 6. The output terminal of delay device 5 is connected to the other input terminal of subtractor 6. The output terminal of the subtracter 6 is connected to a comparator 7. Clock generator 3 is connected to clock input terminals of A/D converter 1 , A/D converter 2 , and delay device 6 .

In the above configuration, the clock generator 3
A clock with a frequency equal to the rate is generated, and using this clock as a sampling clock, the 1-channel signal and Q-channel signal, which are the analog outputs of the synchronous detector, are sent to A/D converter 1 and A/D converter 2, respectively. It is converted into a digital signal at The sample/phase converter 4 converts the amplitude information of this digital signal into phase information,
Get the phase value.

The subtracter 6 calculates, from a certain phase value obtained by the sample/phase converter 4, by the clock from the clock generator 3.
The phase value delayed through the delay device 5 that causes a delay of one symbol is subtracted, and the subtraction result is compared with a reference value in the comparator 7. The comparator 7 outputs a detection signal indicating that the specific signal sequence has been received when the number of consecutive matches exceeds the length of the specific signal sequence to be detected.

In the above description, the sample/phase converter 4 that converts amplitude information into phase information can be implemented using a ROM.

The value that the reference value compared by the comparator 7 should take is (π/2) when detecting a signal sequence in which all symbols are "1" when the modulation method is the MSK method.
, when detecting a signal sequence in which all symbols are "0°", it is (1π/2).Also, when the modulation method is a GMSK method using a Gaussian filter as a baseband filter.The above MSK method It is similar to that of .On the other hand,
In the modulation method, if three symbols "1m" are input in a row, the phase of the signal vector increases by (π/2) per symbol, and if three symbols "0" are input in a row, the phase of the signal vector increases by one symbol. In the case of the Tamed PH method, where the phase of the signal vector does not change if symbols "0" and "1" are input alternately, the value that the reference value should take is When detecting a signal sequence in which is “1”, (π/2
), to detect a signal sequence in which all symbols are “0” (1π/2), the symbol “0°” and the symbol “1”
It is 0 when detecting a signal sequence in which .

In the comparator 7, in order to detect that the number of times the output of the subtracter 6 and the reference value match has become equal to or greater than the length of a specific signal sequence to be detected, specifically, the comparator 7 is As shown in Figure 2, the output of the subtracter 6 is input and compared with the reference value. For example, if they match, "0" is output, and if they do not match, "1" is output. 11, a shift register 12 having the same number of stages as the length of the specific signal series to be detected whose output from the comparator 11 is input to the serial input terminal, and the parallel output of the shift register 12 being all "0". If this is detected, the comparator 13 may be configured to output a signal indicating that a specific signal sequence has been input.

By the way, the number of times the output of the subtracter 6 and the reference value match may be smaller than the length of a specific signal sequence to be detected due to code interference if there is a delayed wave. In such cases, countermeasures can be taken, such as making the length of the specific signal sequence to be detected as long as possible, and deeming that the specific signal sequence has been detected even if the number of matches is several times less than the length of the specific signal sequence. All you have to do is apply.

In the above embodiment, the configuration of the device is shown as hardware, but the outputs of the A/D converters 1 and 2 or the output of the sample/phase converter 4 are input to the digital signal processor. The subsequent processing may be performed by software.

[Effects of the Invention] As explained above, the present invention samples the output of a synchronous detector at a sampling rate equal to the symbol rate, represents the sample value as a phase value, and calculates the change in this phase value for each symbol. By detecting that the signal is always constant, even in high-speed digital transmission, it is possible to detect a specific signal sequence with a simple demodulator that does not require transmission line equalization or clock recovery.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a signal detection device according to an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the comparator shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional signal detection device. Fig. 4 is a block diagram showing the configuration of the device. Fig. 4 shows an example in which the signal vector obtained by synchronously detecting the MSK wave is sampled with a clock synchronized with the symbol. (a) is an example of only direct waves; b) shows an example of a direct wave and a superimposed wave, and Fig. 5 shows an example in which the signal vector obtained by synchronously detecting the MSK wave to be detected is sampled with a clock synchronized with the symbol. is (b
) shows an example where all the signals are symbols “0”, and the 6th
The figure shows a signal vector obtained by synchronously detecting an MSK wave to be detected, which is sampled using a clock whose frequency is slightly shifted from a clock synchronized with a symbol, and is displayed over a short period of time. 1, 2... A/D converter, 3... Clock generator,
4... Sample/phase converter, 5... Delay device, 6...
...Subtractor, 7...Comparator, 11.13...Comparator, 12...Shift register, 101...Clock regeneration circuit, 102...Signal regeneration circuit, 10B...Comparison circuit . Figure 4 Figure 5

Claims (1)

[Claims] 1. Corresponding to symbols "1" and "0" to be transmitted, the phase of the carrier wave is in a first direction and in a second direction opposite to the first direction, respectively. The I-channel signal and In an apparatus for detecting, from the Q channel signal, a specific signal sequence corresponding to a specific symbol pattern in which the phase change of the received wave is equal to the symbol rate of the received wave at each sampling time interval, a first analog/digital conversion means for converting an I channel signal into a first digital signal in synchronization with the clock signal; and a first analog/digital conversion means for converting the I channel signal into a first digital signal in synchronization with the clock signal; second analog/digital conversion means for converting a signal into a second digital signal; and amplitude/phase conversion for determining the current phase value of the received wave from the amplitude values of each of the first and second digital signals. means for delaying the current phase value by the sampling time interval and outputting a delayed phase value; subtracting the delayed phase value from the current phase value and outputting the subtracted value. a subtraction means for determining whether the subtracted value and a predetermined value match consecutively a predetermined number of times, and if the determination result is affirmative, the specific signal sequence is detected. A signal sequence detection device comprising: a coincidence determination means for outputting a coincidence signal indicating that the signal sequence detects the coincidence.