JPH0323898U - - Google Patents
Info
- Publication number
- JPH0323898U JPH0323898U JP8376989U JP8376989U JPH0323898U JP H0323898 U JPH0323898 U JP H0323898U JP 8376989 U JP8376989 U JP 8376989U JP 8376989 U JP8376989 U JP 8376989U JP H0323898 U JPH0323898 U JP H0323898U
- Authority
- JP
- Japan
- Prior art keywords
- word line
- memory cell
- limiter circuit
- booster circuit
- junction diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Dram (AREA)
Description
第１図および第２図は本考案によるワード線リ
ミツタ回路を説明する回路図、第３図および第４
図は本考案に用いる接合ダイオードおよびツエナ
ーダイオードの構造を説明する断面図、第５図は
従来のワード線リミツタ回路を説明する回路図で
ある。
１……ワード線昇圧回路、２……メモリセル、
３……ワード線リミツタ回路、４……接合ダイオ
ード、５……ツエナーダイオード、６……Ｐ型シ
リコン基板、７……Ｎ型ウエル領域、８……Ｐ＋
型アノード領域、９……Ｎ＋型カソード領域であ
る。
1 and 2 are circuit diagrams illustrating a word line limiter circuit according to the present invention, and FIGS.
The figure is a sectional view illustrating the structure of a junction diode and a Zener diode used in the present invention, and FIG. 5 is a circuit diagram illustrating a conventional word line limiter circuit. 1...Word line booster circuit, 2...Memory cell,
3... Word line limiter circuit, 4... Junction diode, 5... Zener diode, 6... P type silicon substrate, 7... N type well region, 8... P +
9 is an N + type cathode region.
Claims (1)
ルと前記メモリセルに接続されたワード線と前記
ワード線の電位を書き込み時に昇圧するワード線
昇圧回路とを具備し、前記ワード線昇圧回路と前
記メモリセル間に接合ダイオードを複数個接続し
たことを特徴とするワード線リミツタ回路。 (2) 前記接合ダイオードの個数を電源Ｖｃｃ＋
２Ｖｔｎ（スレツシヨルド電位）になる様に設定
したことを特徴とする請求項１記載のワード線リ
ミツタ回路。 (3) １トランジスタ、１キヤパシタのメモリセ
ルと前記メモリセルに接続されたワード線と前記
ワード線の電位を書き込み時に昇圧するワード線
昇圧回路とを具備し、前記ワード線昇圧回路と前
記メモリセル間に接合ダイオードおよびツエナー
ダイオードを複数個接続したことを特徴とするワ
ード線リミツタ回路。 (4) 前記接合ダイオードおよびツエナーダイオ
ードの個数を電源Ｖｃｃ＋２Ｖｔｎになる様に設
定したことを特徴とする請求項３記載のワード線
リミツタ回路。[Claims for Utility Model Registration] (1) A memory cell having one transistor and one capacitor, a word line connected to the memory cell, and a word line booster circuit for boosting the potential of the word line during writing, A word line limiter circuit characterized in that a plurality of junction diodes are connected between a word line booster circuit and the memory cell. (2) The number of junction diodes is determined by the power supply Vcc+
2. The word line limiter circuit according to claim 1, wherein the word line limiter circuit is set to 2Vtn (threshold potential). (3) A memory cell having one transistor and one capacitor, a word line connected to the memory cell, and a word line booster circuit that boosts the potential of the word line during writing, the word line booster circuit and the memory cell. A word line limiter circuit characterized in that a plurality of junction diodes and Zener diodes are connected between them. (4) The word line limiter circuit according to claim 3, wherein the number of the junction diodes and Zener diodes is set so that the power supply Vcc+2Vtn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8376989U JPH0323898U (en) | 1989-07-17 | 1989-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8376989U JPH0323898U (en) | 1989-07-17 | 1989-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0323898U true JPH0323898U (en) | 1991-03-12 |
Family
ID=31631713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8376989U Pending JPH0323898U (en) | 1989-07-17 | 1989-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323898U (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6124094A (en) * | 1984-07-11 | 1986-02-01 | Hitachi Micro Comput Eng Ltd | Memory device for semiconductor |
| JPS61113195A (en) * | 1984-11-07 | 1986-05-31 | Hitachi Ltd | Semiconductor storage device |
| JPS63144555A (en) * | 1986-12-09 | 1988-06-16 | Toshiba Corp | Semiconductor integrated circuit |
| JPS63239673A (en) * | 1987-03-27 | 1988-10-05 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6489100A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Non-volatile semiconductor memory device |
| JPH01173500A (en) * | 1987-12-28 | 1989-07-10 | Toshiba Corp | Nonvolatile semiconductor memory device |
-
1989
- 1989-07-17 JP JP8376989U patent/JPH0323898U/ja active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6124094A (en) * | 1984-07-11 | 1986-02-01 | Hitachi Micro Comput Eng Ltd | Memory device for semiconductor |
| JPS61113195A (en) * | 1984-11-07 | 1986-05-31 | Hitachi Ltd | Semiconductor storage device |
| JPS63144555A (en) * | 1986-12-09 | 1988-06-16 | Toshiba Corp | Semiconductor integrated circuit |
| JPS63239673A (en) * | 1987-03-27 | 1988-10-05 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6489100A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Non-volatile semiconductor memory device |
| JPH01173500A (en) * | 1987-12-28 | 1989-07-10 | Toshiba Corp | Nonvolatile semiconductor memory device |
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