JPH03247013A - Output circuit for integrated circuit - Google Patents

Abstract

PURPOSE:To extract a large current to an external circuit by providing a field- effect transistor(TR) capable of switching in response to the output of a level conversion means largely increasing its voltage in response to an input signal. CONSTITUTION:N-channel metal oxide semiconductor field effect transistors(TRs) (N-channel MOS FETs) 3a, 3b are switching-controlled by the input signal from lines 4a, 4b. The input signal is generated by an arithmetic processing circuit or the like included in a large scale integrated circuit and given to the lines 4a, 4b. The absolute value of the input signal from the lines 4a, 4b is increased by level conversion circuits 1a, 1b provided to each of N-channel MOS FETs 3a, 3b and a boosting circuit 2 provided in common to plural N- channel MOS FETs 3a, 3b and given to gates of the N-channel MOSFETs 3a, 3b. Then the absolute value of the voltage given to the gates of the N- channel MOS FETs 3a, 3b is increased more than the absolute value of the input signal. Thus, a large current is extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an output circuit for extracting signals processed within an integrated circuit to the outside of the integrated circuit using a large current.

2. Description of the Related Art In conventional integrated circuits, a P-channel metal oxide semiconductor field effect transistor (
A switching circuit using a PchMOS type FET (abbreviated as PchMOS type FET) 31 has been used as an output circuit. In Figure 6,
The input signal is applied to the gate of a P-channel metal oxide semiconductor field effect transistor 31. The source of the P-channel metal oxide semiconductor field effect transistor 31 is connected to the power supply voltage VDD, and the drain is connected to the output terminal P30. The P-channel metal oxide semiconductor field effect transistor 31 increases the resistance value between the drain and the source according to the input signal when the input voltage is close to the power supply voltage VDD and the potential difference between the gate and the source is small, and the input signal is grounded. When the potential difference between the gate and source is close to the voltage and the potential difference between the gate and source is large, a switching operation is performed to reduce the resistance value between the drain and source. In response to this switching operation, the drain current of P-channel metal oxide semiconductor field effect transistor 31 is taken out to an external circuit from output terminal P30.

Problems to be Solved by the Invention In order to be able to draw a large current to an external circuit, it is necessary to increase the width of the gate electrode of a field effect transistor to reduce the conduction resistance between the drain and source. For this purpose, it is necessary to increase the area of the field effect transistor, and therefore the proportion of the area occupied by the field effect transistor in the integrated circuit increases.
It has been difficult to increase the density of integrated circuits. Particularly in large-scale integrated circuits (LSIs), the number of output circuits increases, so there is a greater need to reduce their area.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit in an integrated circuit that has a small area and is capable of drawing a large current to an external circuit.

Means for Solving the Problems The present invention includes: level converting means that responds to an input signal and greatly increases its voltage value; and a field effect transistor that performs a switching operation in response to the output of the level converting means. This is an output circuit for an integrated circuit characterized by:

Operation According to the present invention, the voltage value of the input signal is greatly increased by the level conversion means and applied to the field effect transistor that performs the switching operation.

Since the driving voltage of the field effect transistor becomes larger, a larger current can be taken out to the external circuit of the integrated circuit.

Embodiment FIG. 1 is a block diagram showing an embodiment of an output circuit for an integrated circuit according to the present invention. Large scale integrated circuit (LSI)
The present invention is implemented in order to take out a large current from the output field effect transistors 3a, 3b to an external circuit via the output terminal PlaPlb of an integrated circuit such as an integrated circuit. In the following description, the subscripts a and b will be omitted and a general description will be provided.

N-channel gold R oxide semiconductor field effect transistor (
The switching of the NchMO3 type FET (abbreviated as NchMO3 type FET) 3 is controlled by an input signal from a line 4. The input signal is generated by an arithmetic processing circuit included in a large-scale integrated circuit and applied to line 4. The input signal from the line 4 is transmitted to the level conversion circuit 1 provided for each N-channel metal oxide semiconductor field effect transistor 3 and to the level conversion circuit 1 provided for each N-channel metal oxide semiconductor field effect transistor 3
Level conversion means 1 including a booster circuit 2 provided in common to channel metal oxide semiconductor field effect transistors 3
．． 2 increases the absolute value of the voltage of the input signal to N
In the six-level conversion means 1 and 2 applied to the gate of the channel metal oxide semiconductor field effect transistor 3,
A specific configuration of the booster circuit 2 is shown in FIG. This circuit is a voltage doubler circuit also called a charge pump.

In FIG. 2, capacitors CI and C2 and associated switching elements 81 to S are used to perform voltage doubler operation.
4 is provided and connected to the DC power supply ■. The switching elements 81 to S4 are turned ON by the control circuit C8.
The switching behavior of 10 F F is controlled. The control circuit C8 receives a signal from a clock oscillation circuit CK for synchronous operation of the arithmetic processing circuit, etc. included in the large-scale integrated circuit, and operates the switching elements 81 to S4 in synchronization with this clock signal. It will be done. The switching elements 81 to S4 are realized, for example, by field effect transistors or bipolar transistors in a large-scale integrated circuit.

The voltage doubler circuit operates by alternately repeating the states shown in FIG. 2(1) and FIG. 2(2). In FIG. 2(1), the first and third switching elements S1 and S3 are turned on, and the second and fourth switching elements S2. S4 is OFF. therefore,
A DC voltage (■) is applied across the first capacitor C1, and the first capacitor C1 is charged with the DC voltage (■). The control circuit C8 controls the first and third switching elements S1,
S3 is turned off, and the second and fourth switching elements S2. A state in which S4 is turned on is shown in FIG. 2 (2). In FIG. 2(2), a voltage is applied to both ends of the second capacitor C2 from a circuit in which the first capacitor C1 and a DC voltage (2) are connected in series. First capacitor C1
is charged with the DC voltage V, so the voltage across the second capacitor C2 is twice the DC voltage V. . will be charged.

In the embodiment of FIG. 1, the DC voltage V is the power supply voltage v9. Use.

The booster circuit 2 repeatedly performs the operations described above in synchronization with the signal from the clock oscillation circuit CK. When the integrated circuit is composed of field effect transistors, the current consumption is extremely small, so the capacitance of the capacitors C1 and C2 can be reduced, and the area of the booster circuit 2 in the integrated circuit can be reduced. Furthermore, a single booster circuit 2 may be provided in common for a plurality of output field effect transistors.

A concrete circuit of the level conversion circuit 1 is shown in FIG. 3.The level conversion circuit 1 is supplied with a boosted voltage (2) by the boost supply line 6 shown in FIG. . is supplied.

The input signal is applied to the gate of the first N-channel metal oxide semiconductor field effect transistor 21, and is also applied to the gate of the second N-channel metal oxide semiconductor field effect transistor 21 via a first inverting circuit 25 made of a complementary metal oxide semiconductor (abbreviated as CMO3). It is applied to the gate of the channel metal oxide semiconductor field effect transistor 23. 1st
N-channel metal oxide semiconductor field effect transistor 2
The drain of 1 is connected to the power supply voltage V via the first P-channel metal oxide semiconductor field effect transistor 22 .

connected to. The first inverting circuit 25 also has a power supply voltage VDD.
is supplied. The drain of the second N-channel metal oxide semiconductor field effect transistor 23 is connected via the second P-channel metal oxide semiconductor field effect transistor 24 to
Connected to boosted voltage VCc. The gate of the first P-channel metal oxide semiconductor field effect transistor 22 is connected to the second P-channel metal oxide semiconductor field effect transistor 22.
N-channel metal oxide semiconductor field effect transistor 2
Connected to the drain of 3. The gate of the second P-channel metal oxide semiconductor field effect transistor 24 is connected to the first N
Channel metal oxide semiconductor field effect transistor 21
connected to the train. The drain voltage of the second N-channel metal oxide semiconductor field effect transistor 23 is applied to second and third inverting circuits 26 and 27 formed of cascade-connected complementary metal oxide semiconductors. The second and third inversion circuits 26 and 27 are supplied with the boosted voltage Vcc, similarly to the second P-channel metal oxide semiconductor field effect transistor 24.

As shown in FIG. 4 (1), when an input voltage varying in the range between the power supply voltage DD and the ground potential is applied, level conversion occurs at the drain of the second N-channel metal oxide semiconductor field effect transistor 23. , through the second and third inverting circuits 26 and 27 which operate as buffers, and are derived as the output voltage shown in FIG. 4(2).

The level conversion circuit 1 generates a boosted voltage (2) higher than the power supply voltage VpD. The input signal increased to C is applied to the gate of the output N-channel metal oxide semiconductor field effect transistor 3 via line 5 in FIG. The drain of the N-channel metal oxide semiconductor field effect transistor 3 is connected to the power supply voltage VDD, and the source is connected to the line 7.
is connected to the external output terminal P1 of the large-scale integrated circuit.

A metal oxide semiconductor field effect transistor has characteristics as shown in FIG. FIG. 5 is a graph showing the relationship between drain current and train-source voltage using the gate-source voltage as a parameter. In Figure 5,
Line 11. N2゜13 is the gate-source voltage Vos
1, Voa2, and Vara3, respectively, and the relationship of the following first equation exists.

Vasl > Vos2 > Vas3
-(1) Therefore, if the absolute value of the potential difference between the gate and the source becomes large, a large drain current can flow, and a large current can be taken out from the output terminal P1 to an external circuit.

In this way, by making the absolute value of the voltage applied to the gate of the N-channel metal oxide semiconductor field effect transistor 3 larger than the absolute value of the voltage of the input signal, the N-channel The current flowing between the drain and source of the metal oxide semiconductor field effect transistor 3 can be increased, and therefore the area required for forming the N-channel metal oxide semiconductor field effect transistor 3 can be reduced. The proportion of the area occupied in a large-scale integrated circuit can be reduced.

The level converting means 1.2 can be formed in a relatively small size and does not occupy an unnecessarily large area in the large-scale integrated circuit. It can be driven by a large current.

For example, in order to drive an external circuit with a current of 20 to 30 mA, it was conventionally necessary to use a field effect transistor with an area of about 0.5 mm square, but according to the configuration of the output circuit in this case, the field effect transistor has an area of about half that. It can be made smaller in area.

In the above description, an N-channel element is described as an output field effect transistor, but when a negative voltage is generated in the booster circuit 2, the level converter circuit 1
By converting the input signal to a negative voltage level, a P-channel metal oxide semiconductor field effect transistor 31 as shown in FIG. 6 is used for output, and a large current is passed from the external terminal P30 to the external circuit. It can also be supplied to

Also, for output circuit configurations in which current flows from an external circuit to an output field effect transistor, large current can be absorbed.

Effects of the Invention As described above, according to the present invention, the voltage value of the input signal is greatly increased and applied to the field effect transistor by the level converting means. In a field effect transistor, the larger the absolute value of the voltage between the gate and the source, the larger the current can flow through the train, so even if the gate area is small, a large current can be extracted to the external circuit. In this way, by using the output circuit for integrated circuits according to the present invention,
Integrated circuits that can draw large currents can be densified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the booster circuit 2, FIG. 3 is a circuit diagram of the level conversion circuit 1, and FIG. 4 is the input/output waveform of the level conversion circuit 1. 5 is a characteristic diagram of a metal oxide semiconductor field effect transistor, and FIG. 6 is a circuit diagram showing a conventional technique.

Claims (1)

[Claims] An integrated circuit comprising: level conversion means that responds to an input signal and greatly increases its voltage value; and a field effect transistor that performs a switching operation in response to the output of the level conversion means. Output circuit for circuit.