JPH0324721U - - Google Patents
Info
- Publication number
- JPH0324721U JPH0324721U JP8594589U JP8594589U JPH0324721U JP H0324721 U JPH0324721 U JP H0324721U JP 8594589 U JP8594589 U JP 8594589U JP 8594589 U JP8594589 U JP 8594589U JP H0324721 U JPH0324721 U JP H0324721U
- Authority
- JP
- Japan
- Prior art keywords
- trap
- vibrating electrodes
- different
- pairs
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
第１図は本考案にかかるトラツプ回路の一例の
回路図、第２図はトラツプ単体の斜視図、第３図
は一方のトラツプの特性図、第４図は他方のトラ
ツプの特性図、第５図は両方のトラツプを並列接
続したときの特性図、第６図は従来のトラツプの
特性図、第７図は従来のトラツプ回路の回路図で
ある。
５，６……トラツプ、１０……圧電セラミツク
基板、１１，１２……入出力電極、１３……共通
電極、１１ａ，１２ａ，１３ａ，１３ｂ……振動
電極。
FIG. 1 is a circuit diagram of an example of a trap circuit according to the present invention, FIG. 2 is a perspective view of a single trap, FIG. 3 is a characteristic diagram of one trap, FIG. 4 is a characteristic diagram of the other trap, and FIG. The figure is a characteristic diagram when both traps are connected in parallel, FIG. 6 is a characteristic diagram of a conventional trap, and FIG. 7 is a circuit diagram of a conventional trap circuit. 5, 6... Trap, 10... Piezoelectric ceramic substrate, 11, 12... Input/output electrode, 13... Common electrode, 11a, 12a, 13a, 13b... Vibration electrode.
Claims (1)
するためのトラツプ回路であつて、 周波数の異なる２個のセラミツク共振子からな
る３端子型トラツプを並列接続してなり、一方の
トラツプは電極面積が同一の２対の振動電極を有
し、他方のトラツプは電極面積が異なる２対の振
動電極を有することを特徴とするトラツプ回路。 (2) 請求項(1)に記載のトラツプ回路において、 同じ面積の振動電極を有するトラツプの圧電セ
ラミツク基板の厚みと、異なる面積の振動電極を
有するトラツプの圧電セラミツク基板の厚みとが
異なることを特徴とするトラツプ回路。[Claims for Utility Model Registration] (1) A trap circuit for removing a specific frequency signal contained in a signal, in which a three-terminal trap consisting of two ceramic resonators with different frequencies is connected in parallel. A trap circuit characterized in that one trap has two pairs of vibrating electrodes with the same electrode area, and the other trap has two pairs of vibrating electrodes with different electrode areas. (2) In the trap circuit according to claim (1), the thickness of the piezoelectric ceramic substrate of the trap having vibrating electrodes with the same area is different from the thickness of the piezoelectric ceramic substrate of the trap having vibrating electrodes with different areas. Features a trap circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8594589U JPH0324721U (en) | 1989-07-20 | 1989-07-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8594589U JPH0324721U (en) | 1989-07-20 | 1989-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0324721U true JPH0324721U (en) | 1991-03-14 |
Family
ID=31635327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8594589U Pending JPH0324721U (en) | 1989-07-20 | 1989-07-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0324721U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0654888U (en) * | 1992-12-26 | 1994-07-26 | 積水ハウス株式会社 | Building window device |
| JP2005293060A (en) * | 2004-03-31 | 2005-10-20 | Taisei Plas Co Ltd | Memory card housing and manufacturing method thereof |
| JP2012142740A (en) * | 2010-12-28 | 2012-07-26 | Daishinku Corp | Band rejection filter |
-
1989
- 1989-07-20 JP JP8594589U patent/JPH0324721U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0654888U (en) * | 1992-12-26 | 1994-07-26 | 積水ハウス株式会社 | Building window device |
| JP2005293060A (en) * | 2004-03-31 | 2005-10-20 | Taisei Plas Co Ltd | Memory card housing and manufacturing method thereof |
| JP2012142740A (en) * | 2010-12-28 | 2012-07-26 | Daishinku Corp | Band rejection filter |
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