JPH0324724U - - Google Patents
Info
- Publication number
- JPH0324724U JPH0324724U JP8407689U JP8407689U JPH0324724U JP H0324724 U JPH0324724 U JP H0324724U JP 8407689 U JP8407689 U JP 8407689U JP 8407689 U JP8407689 U JP 8407689U JP H0324724 U JPH0324724 U JP H0324724U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- short
- signal
- output control
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
Description
第１図はこの考案にかかる過電流保護回路図、
第２図はそのフロー図、第３図は端子Ｎ点での動
作波形図、第４図〜第７図は従来技術における同
様の回路図およびその各動作波形図を示すもので
ある。
ＶＡ……基準電源、ＲＡ……負荷抵抗、Ｔｒ１
……開閉スイツチング用のトランジスタ、Ｔｒ２
……短絡検出用のトランジスタ、Ｒ１……過電流
検出抵抗、Ｄ……ダイオード、Ｃ．Ｐ．Ｕ……制
御手段。
Figure 1 is an overcurrent protection circuit diagram according to this invention.
FIG. 2 is a flow diagram thereof, FIG. 3 is an operation waveform diagram at terminal N point, and FIGS. 4 to 7 are similar circuit diagrams in the prior art and their respective operation waveform diagrams. VA...Reference power supply, RA...Load resistance, Tr 1
...Transistor for opening/closing switching, Tr 2
...Transistor for short circuit detection, R1...Overcurrent detection resistor, D...Diode, C. P. U...control means.
Claims (1)
ール回路手段に開閉スイツチング用のトランジス
タを接続させると共に、当該トランジスタに供与
された過電流に応動する短絡検出用のトランジス
タを備えた過電流保護回路において、 (1) 短絡検出用のトランジスタからの信号に
よつて、時間設定回路手段により第１の動作時間
を設定すると共に、第１のタイマーにより所定時
間を設定して第１のゲートを開放させる手段、 (2) 短絡検出用のトランジスタからの信号と
、前記第１のゲートからの信号により、間歇的に
第２のゲートを開放させる手段、 (3) 前記第１および第２のゲートからの信号
をカウントする第１および第２のカウンタ手段、 (4) 前記第１および第２のカウンタ手段から
の信号を等しいか否かを比較する比較回路手段、 (5) 前記比較結果に基づき、等しければ短絡
信号と判断し、出力コントロール回路手段をＯＦ
Ｆさせ、等しくなければこれをノイズと判断し、
出力コントロール回路手段へは通信しないように
する判別回路手段、 からなることを特徴とする過電流保護回路装置
。 ２ 判別回路手段において、判断した短絡信号を
記憶手段に記憶させ、第２のタイマー手段により
第２の時間設定を行ない所定時間経過後に短絡状
態が継続しているか否かを判定する作業を実行し
、短絡状態が継続していると判断した際には、前
記時間設定回路手段および出力コントロール回路
手段のいずれもをＯＦＦのままとして、再度第２
のタイマー手段による時間設定を実施し、短絡状
態の検証を反覆し、また、短絡状態が解除された
と判断した際には、出力コントロール回路と検出
部との通信を有効にさせると共に、記憶回路手段
および第１、第２の各カウンタ手段のリセツトさ
せるようにした第２の判別回路手段を具備した請
求項１記載の過電流保護回路装置。[Claims for Utility Model Registration] 1. A transistor for opening/closing switching is connected to the output control circuit means connected to the detection signal generating means, and a transistor for short circuit detection is provided in response to an overcurrent applied to the transistor. In the overcurrent protection circuit, (1) the time setting circuit means sets the first operating time based on the signal from the short-circuit detection transistor, and the first timer sets a predetermined time and the first operating time is set. (2) means for intermittently opening a second gate in response to a signal from a short-circuit detection transistor and a signal from the first gate; (4) comparison circuit means for comparing the signals from the first and second counter means to see if they are equal; (5) the comparison Based on the results, if they are equal, it is determined that it is a short circuit signal, and the output control circuit means is turned off.
F, and if they are not equal, it is judged as noise,
An overcurrent protection circuit device comprising: discrimination circuit means for preventing communication to the output control circuit means. 2. In the determination circuit means, the determined short circuit signal is stored in the storage means, a second time is set by the second timer means, and after a predetermined time elapses, a task is performed to determine whether the short circuit state continues. When it is determined that the short-circuit condition continues, both the time setting circuit means and the output control circuit means remain OFF, and the second
The timer means is used to set the time, the short-circuit state is verified repeatedly, and when it is determined that the short-circuit state has been released, communication between the output control circuit and the detection section is enabled, and the memory circuit means is activated. 2. The overcurrent protection circuit device according to claim 1, further comprising second discrimination circuit means for resetting each of the first and second counter means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8407689U JPH0746981Y2 (en) | 1989-07-19 | 1989-07-19 | Overcurrent protection circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8407689U JPH0746981Y2 (en) | 1989-07-19 | 1989-07-19 | Overcurrent protection circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0324724U true JPH0324724U (en) | 1991-03-14 |
| JPH0746981Y2 JPH0746981Y2 (en) | 1995-10-25 |
Family
ID=31632265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8407689U Expired - Lifetime JPH0746981Y2 (en) | 1989-07-19 | 1989-07-19 | Overcurrent protection circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746981Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5307660B2 (en) * | 2009-07-30 | 2013-10-02 | 新日本無線株式会社 | Short circuit protection circuit for switching drive circuit |
| KR102623868B1 (en) * | 2021-12-27 | 2024-01-12 | 주식회사 현대케피코 | Solenoid power supply monitoring control method and system |
-
1989
- 1989-07-19 JP JP8407689U patent/JPH0746981Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746981Y2 (en) | 1995-10-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |