JPH0324813B2 - - Google Patents
Info
- Publication number
- JPH0324813B2 JPH0324813B2 JP58017090A JP1709083A JPH0324813B2 JP H0324813 B2 JPH0324813 B2 JP H0324813B2 JP 58017090 A JP58017090 A JP 58017090A JP 1709083 A JP1709083 A JP 1709083A JP H0324813 B2 JPH0324813 B2 JP H0324813B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- intermediate frequency
- frequency amplifier
- agc
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
- H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Circuits Of Receivers In General (AREA)
Description
【発明の詳細な説明】
本発明は、AM受信機に使用される多段構成の
AGC回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a multi-stage configuration used in an AM receiver.
Regarding AGC circuit.
第1図は主要部がIC化されたAM受信機の概略
ブロツク図で、1はアンテナ、2は初段の高周波
(RF)アンプ、3は次段のRFアンプ、4はミキ
サ、5は受信局発、6は初段の中間周波(IF)
アンプ、7は次段のIFアンプ、8は検波器、9
はAGC(自動利得制御)アンプである。RFアン
プ2,3の要部は電圧制御型の可変利得アンプ
VCA1,VCA2であり、またIFアンプ6の要部
も同様のアンプVCA3である。そしてこの受信
機のAGCは、AGCアンプ9のコントロール電圧
VcをアンプVCA1,VCA2およびアンプVCA
3に共通に帰還することにより行う。但し、各段
の減衰量ATTの変化には第2図実験のように差
をつけ、適当な利得配分がなされるように設定し
てある。即ち、コントロール電圧Vcの上昇に伴
ない最終段のVCA3が初めに減衰を開始し、次
にVCA2が、そして最後に初段のVCA1が減衰
を開始する。このようにしてS/Nの劣化や歪の
発生が生じないようにしている。 Figure 1 is a schematic block diagram of an AM receiver whose main parts are IC-based. 1 is an antenna, 2 is a first-stage radio frequency (RF) amplifier, 3 is a next-stage RF amplifier, 4 is a mixer, and 5 is a receiving station. 6 is the intermediate frequency (IF) of the first stage
Amplifier, 7 is the next stage IF amplifier, 8 is the detector, 9
is an AGC (automatic gain control) amplifier. The main parts of RF amplifiers 2 and 3 are voltage-controlled variable gain amplifiers.
These are VCA1 and VCA2, and the main part of the IF amplifier 6 is also a similar amplifier VCA3. The AGC of this receiver is the control voltage of AGC amplifier 9.
Vc to amplifier VCA1, VCA2 and amplifier VCA
This is done by making a common return to step 3. However, the changes in the attenuation amount ATT of each stage are differentiated as in the experiment shown in FIG. 2, and settings are made so that appropriate gain distribution can be achieved. That is, as the control voltage Vc increases, the final stage VCA3 starts to attenuate first, then the VCA2, and finally the first stage VCA1. In this way, deterioration of S/N and occurrence of distortion are prevented.
ところが、各VCAの特性が第2図のように減
衰量ATTに制限がない場合、VCA3で殆んど
AGCがかかつてしまい、大入力時でもVCA1に
AGCがかかわらず、VCA1のダイナミツクレジ
ンを越してしまい、歪んでしまう。 However, if the characteristics of each VCA are such that there is no limit to the attenuation amount ATT as shown in Figure 2, VCA3 has almost no limit.
AGC becomes stiff and VCA1 is used even during large input.
Regardless of AGC, it will exceed the dynamic resin of VCA1 and become distorted.
本発明は、回路的には抵抗を1素子追加するだ
けの変更で上記の欠点を解決しようとするもので
ある。 The present invention attempts to solve the above-mentioned drawbacks by simply adding one resistor to the circuit.
本発明は、アンテナ入力信号を増幅する第1の
高周波増幅器、該第1の高周波増幅器の出力信号
を増幅する第2の高周波増幅器、及び該第2の高
周波増幅器の出力信号をミキサにより中間周波信
号に変換した後該中間周波信号を増幅する中間周
波増幅器を夫々可変利得増幅器で構成し、後段の
増幅器から順に利得を低下させるAGC回路にお
いて、前記第1の高周波増幅器は前記アンテナ入
力信号を受けるトランジスタと、そのエミツタ側
に接続された抵抗と、該トランジスタのコレクタ
にエミツタが共通に接続されて一方のベースに基
準電圧をまた他方のベースにAGC用のコントロ
ール電圧を受ける一対のトランジスタとを備え、
利得の変化範囲が制限されることなく該一方のト
ランジスタのコレクタから出力を取り出すよう構
成され、前記第2の高周波増幅器及び中間周波増
幅器は入力信号を受けるトランジスタと、そのエ
ミツタ側に接続された抵抗と、該トランジスタの
コレクタにエミツタが共通に接続されて一方のベ
ースに基準電圧を、また他方のベースにAGC用
のコントロール電圧を受ける一対のトランジスタ
と、該一対のトランジスタの両コレクタ間に接続
された抵抗と、該コントロール電圧を受けるトラ
ンジスタのコレクタと電源との間に接続された抵
抗とを備え、該コレクタと電源との間に接続され
た抵抗により利得の変化範囲を制限して該基準電
圧を受けるトランジスタのコレクタから出力を取
り出すように構成してなることを特徴とするが、
以下図示の実施例を参照しながらこれを詳細に説
明する。 The present invention includes a first high-frequency amplifier that amplifies an antenna input signal, a second high-frequency amplifier that amplifies the output signal of the first high-frequency amplifier, and an intermediate frequency signal that converts the output signal of the second high-frequency amplifier into an intermediate frequency signal. In the AGC circuit, each of the intermediate frequency amplifiers that amplify the intermediate frequency signal after converting it into a variable gain amplifier is configured to reduce the gain sequentially from the downstream amplifier, and the first high frequency amplifier is a transistor that receives the antenna input signal. , a resistor connected to its emitter side, and a pair of transistors whose emitters are commonly connected to the collectors of the transistors and receive a reference voltage at one base and a control voltage for AGC at the other base,
The second high frequency amplifier and intermediate frequency amplifier are configured to take out the output from the collector of the one transistor without limiting the range of gain change, and the second high frequency amplifier and the intermediate frequency amplifier include a transistor receiving an input signal and a resistor connected to the emitter side of the transistor. and a pair of transistors whose emitters are commonly connected to the collectors of the transistors, and whose bases receive a reference voltage and whose other bases receive an AGC control voltage, and which are connected between both collectors of the pair of transistors. and a resistor connected between the collector of the transistor receiving the control voltage and a power supply, and the resistor connected between the collector and the power supply limits the range of gain change and controls the reference voltage. It is characterized by being configured so that the output is taken out from the collector of the transistor receiving the signal.
This will be explained in detail below with reference to the illustrated embodiments.
第3図は本発明に係る可変利得アンプVCAの
回路図で、R1が本発明により追加された抵抗で
ある。Viは交流入力電圧、V0はその増幅出力、
Vcは先の直流コントロール電圧、Vは基準電圧、
Tr1,Tr2は差動対を構成するトランジスタ、Tr3
は電圧Viを電流に変換するトランジスタ、R3は
そのエミツタ抵抗、R2はトランジスタTr2のコレ
クタ側に接続された抵抗である。基準電圧Vは
AGCをかけ始める点を規定する。従来のVCA
は、トランジスタTr1のコレクタと抵抗R2の接続
点を直接電源Vccに接続しているため、減衰量
ATTは無限大までの値をとり得る。しかし、一
般にATTは10〜20dB程度あれば十分なので、本
発明では抵抗R1を挿入してATTの変化範囲を制
限する。 FIG. 3 is a circuit diagram of a variable gain amplifier VCA according to the present invention, where R1 is a resistor added according to the present invention. Vi is the AC input voltage, V 0 is its amplified output,
Vc is the previous DC control voltage, V is the reference voltage,
Tr 1 and Tr 2 are transistors forming a differential pair, Tr 3
is a transistor that converts voltage Vi into current, R3 is its emitter resistance, and R2 is a resistance connected to the collector side of transistor Tr2 . The reference voltage V is
Specifies the point at which AGC starts. Traditional VCA
Since the connection point between the collector of transistor Tr 1 and resistor R 2 is directly connected to the power supply Vcc, the attenuation amount is
ATT can take values up to infinity. However, in general, ATT of about 10 to 20 dB is sufficient, so in the present invention, the resistance R1 is inserted to limit the range of change in ATT.
つまり、Vc<VであればトランジスタTr1がオ
フで全くAGCはかからない。このときの利得は
Vp/Vi=R1+R2/R3 …(1)
である。これに対し、Vc>VでトランジスタTr2
が完全にオフするとAGCが最高度にかかつた状
態になるが、このときの利得は
Vp/Vi=R1/R2 …(2)
である。通常動作時は(1),(2)式の間で利得が変化
する。 In other words, if Vc<V, the transistor Tr1 is off and no AGC is applied. The gain at this time is V p /V i =R 1 +R 2 /R 3 (1). On the other hand, when Vc>V, the transistor Tr 2
When is completely turned off, the AGC is applied to the highest level, and the gain at this time is V p /V i =R 1 /R 2 (2). During normal operation, the gain changes between equations (1) and (2).
従来の回路では(2)式でR1=0であるから利得
0、従つてATT=となるが、本発明ではR1の値
を設定することで、各VCAのATT限界を個々に
制限できる。第4図はVCA2とVCA3に第3図
の回路を適用した特性例である。 In the conventional circuit, since R 1 = 0 in equation (2), the gain is 0, and therefore ATT =, but in the present invention, by setting the value of R 1 , the ATT limit of each VCA can be individually limited. . FIG. 4 shows an example of characteristics when the circuit shown in FIG. 3 is applied to VCA2 and VCA3.
第5図はIC化された高周波段で、後段のアン
プVCA2に第3図と同様の構成が採用されてい
る。初段のアンプVCA1は利得の変化範囲を制
限しないので、その回路構成には手を加えない。
つまり差動対用のトランジスタTr4,Tr5と共通
エミツタ側のトランジスタTr6等でアンプVCA1
が構成される。Ist RF INはVCA1への交流入
力であり、その増幅出力はトランジスタTr4から
外付けのインダクタンスLを通して次段のアンプ
VCA2に供給される。2nd RF OUTがこのアン
プVCA2の増幅出力である。トランジスタTr1と
Tr5には共通にコントロール電圧Vcが供給され
る。これはOPアンプを用いたAGCアンプ9の出
力をダイオードD1で適当にシフトしたものであ
る。このアンプ9の入力は検波回路8の出力であ
り、また検波回路8の入力は中間周波トランス
IFTから得られる中間周波信号である。トランジ
スタTr4に印加される基準電圧V1とトランジスタ
Tr2に印加される基準電圧V2との間にはダイオー
ドD2の順方向電圧の差を持たせてある。このV1
>V2の関係から、後段のVCA2の方が先に減衰
を開始する。IF段のアンプVCA3についても
VCA2と同様の抵抗R1が追加されているが、こ
の部分の説明は省略する。 FIG. 5 shows a high-frequency stage implemented as an IC, and the configuration similar to that in FIG. 3 is adopted for the amplifier VCA2 in the subsequent stage. Since the first stage amplifier VCA1 does not limit the range of gain variation, its circuit configuration is not modified.
In other words, the amplifier VCA1 is made up of the differential pair transistors Tr 4 and Tr 5 and the transistor Tr 6 on the common emitter side.
is configured. Ist RF IN is the AC input to VCA1, and its amplified output is passed from transistor Tr 4 to external inductance L to the next stage amplifier.
Supplied to VCA2. 2nd RF OUT is the amplified output of this amplifier VCA2. Transistor Tr 1 and
Control voltage Vc is commonly supplied to Tr 5 . This is obtained by appropriately shifting the output of AGC amplifier 9 using an OP amplifier using diode D1 . The input of this amplifier 9 is the output of the detection circuit 8, and the input of the detection circuit 8 is an intermediate frequency transformer.
This is an intermediate frequency signal obtained from IFT. Reference voltage V 1 applied to transistor Tr 4 and transistor
A difference in the forward voltage of the diode D 2 is provided between the reference voltage V 2 applied to the Tr 2 and the reference voltage V 2 . This V 1
>V 2 , VCA2 in the latter stage starts attenuation first. Regarding the IF stage amplifier VCA3
A resistor R1 similar to VCA2 is added, but the explanation of this part will be omitted.
以上述べたように本発明によれば、多段構成の
可変利得アンプを用いるAGC回路で各段のAGC
に制限を加えたので、歪が生ぜず安定した動作が
期待できると共に、各増幅器のAGCがききはじ
める時点でその入力信号レベルを最大限に大きく
できるので、一層のS/Nの向上をはかることが
できる。 As described above, according to the present invention, each stage of the AGC circuit uses a multi-stage variable gain amplifier.
Since we have added a limit to the input signal, we can expect stable operation without distortion, and the input signal level can be maximized at the time when the AGC of each amplifier starts to be heard, further improving the S/N ratio. Can be done.
第1図はAM受信機のAGC回路を示すブロツ
ク図、第2図は従来のAGC特性の説明図、第3
図は本発明の要部回路図、第4図はそのAGC特
性図、第5図は本発明の一実施例を示す回路図で
ある。
図中、VCA1〜VCA3は可変利得アンプ、
Tr1〜Tr3はトランジスタ、R1〜R3は抵抗、Viは
入力、V0は出力、Vは基準電圧、Vcはコントロ
ール電圧、Vccは電源である。
Figure 1 is a block diagram showing the AGC circuit of an AM receiver, Figure 2 is an explanatory diagram of conventional AGC characteristics, and Figure 3 is a block diagram showing the AGC circuit of an AM receiver.
FIG. 4 is a circuit diagram of a main part of the present invention, FIG. 4 is an AGC characteristic diagram thereof, and FIG. 5 is a circuit diagram showing an embodiment of the present invention. In the figure, VCA1 to VCA3 are variable gain amplifiers,
Tr 1 to Tr 3 are transistors, R 1 to R 3 are resistors, Vi is an input, V 0 is an output, V is a reference voltage, Vc is a control voltage, and Vcc is a power supply.
Claims (1)
幅器、該第1の高周波増幅器の出力信号を増幅す
る第2の高周波増幅器、及び該第2の高周波増幅
器の出力信号をミキサにより中間周波信号に変換
した後該中間周波信号を増幅する中間周波増幅器
を夫々可変利得増幅器で構成し、後段の増幅器か
ら順に利得を低下させるAGC回路において、 前記第1の高周波増幅器は前記アンテナ入力信
号を受けるトランジスタと、そのエミツタ側に接
続された抵抗と、該トランジスタのコレクタにエ
ミツタが共通に接続されて一方のベースに基準電
圧をまた他方のベースにAGC用のコントロール
電圧を受ける一対のトランジスタとを備え、利得
の変化範囲が制限されることなく該一方のトラン
ジスタのコレクタから出力を取り出すよう構成さ
れ、 前記第2の高周波増幅器及び中間周波増幅器は
入力信号を受けるトランジスタと、そのエミツタ
側に接続された抵抗と、該トランジスタのコレク
タにエミツタが共通に接続されて一方のベースに
基準電圧を、また他方のベースにAGC用のコン
トロール電圧を受ける一対のトランジスタと、該
一対のトランジスタの両コレクタ間に接続された
抵抗と、該コントロール電圧を受けるトランジス
タのコレクタと電源との間に接続された抵抗とを
備え、該コレクタと電源との間に接続された抵抗
により利得の変化範囲を制限して該基準電圧を受
けるトランジスタのコレクタから出力を取り出す
ように構成してなることを特徴とするAGC回路。[Claims] 1. A first high-frequency amplifier that amplifies an antenna input signal, a second high-frequency amplifier that amplifies an output signal of the first high-frequency amplifier, and an output signal of the second high-frequency amplifier that is amplified by a mixer. In the AGC circuit, in which the intermediate frequency amplifiers that amplify the intermediate frequency signal after converting it into an intermediate frequency signal are each configured with a variable gain amplifier, and the gain is decreased in order from the downstream amplifier, the first high frequency amplifier is configured to convert the intermediate frequency signal into an intermediate frequency signal and then amplify the intermediate frequency signal. a resistor connected to its emitter side, and a pair of transistors whose emitters are commonly connected to the collectors of the transistors and receive a reference voltage to one base and a control voltage for AGC to the other base. The second high frequency amplifier and the intermediate frequency amplifier are connected to the transistor receiving the input signal and the emitter side thereof, and the second high frequency amplifier and the intermediate frequency amplifier are connected to the transistor receiving the input signal and to the emitter side thereof. a pair of transistors whose emitters are commonly connected to the collectors of the transistors and receive a reference voltage at one base and a control voltage for AGC at the other base; and a resistor connected between the collector of the transistor receiving the control voltage and the power supply, and the range of gain change is limited by the resistor connected between the collector and the power supply. An AGC circuit characterized in that the AGC circuit is configured to take out an output from the collector of a transistor that receives the reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1709083A JPS59143429A (en) | 1983-02-04 | 1983-02-04 | Agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1709083A JPS59143429A (en) | 1983-02-04 | 1983-02-04 | Agc circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59143429A JPS59143429A (en) | 1984-08-17 |
| JPH0324813B2 true JPH0324813B2 (en) | 1991-04-04 |
Family
ID=11934283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1709083A Granted JPS59143429A (en) | 1983-02-04 | 1983-02-04 | Agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59143429A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4850785B2 (en) * | 2007-06-11 | 2012-01-11 | 日本電信電話株式会社 | Variable gain circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5250644Y2 (en) * | 1971-11-17 | 1977-11-17 | ||
| JPS5013029A (en) * | 1973-04-11 | 1975-02-10 | ||
| JPS5242322A (en) * | 1975-09-30 | 1977-04-01 | Sanyo Electric Co Ltd | Agc circuit for tv receiver |
| JPS5722245A (en) * | 1980-07-15 | 1982-02-05 | Fuji Electric Co Ltd | Low fatigue electrophotographic receptor and its manufacture |
-
1983
- 1983-02-04 JP JP1709083A patent/JPS59143429A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59143429A (en) | 1984-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3479404B2 (en) | Multi-stage variable gain amplifier circuit | |
| US4742565A (en) | Radio receiver with field intensity detector | |
| US5256984A (en) | Amplifier for controlling linear gain of wide band using external bias | |
| EP0342671A2 (en) | AGC delay on an integrated circuit | |
| CA1183581A (en) | Variable load impedance gain-controlled amplifier | |
| US3731215A (en) | Amplifier of controllable gain | |
| JPH11150435A (en) | Gain control rf signal amplifier | |
| JPS5844803A (en) | 11/2 pole audio power amplifier | |
| EP1119100A2 (en) | Amplifiers | |
| HK92291A (en) | High-frequency differential amplifier stage and amplifier with such a differential amplifier stage | |
| JPH0324813B2 (en) | ||
| US6091275A (en) | Linear quad variable gain amplifier and method for implementing same | |
| JPH0314818Y2 (en) | ||
| US5838198A (en) | Gain control for parallel-arranged differential pairs | |
| JP3004138B2 (en) | Gain switching circuit | |
| JP3148540B2 (en) | AGC circuit of radio receiver | |
| CN212518924U (en) | Intermediate frequency gain control circuit for navigation receiver | |
| JPH0447485B2 (en) | ||
| JP2599884Y2 (en) | AGC circuit of high frequency amplifier | |
| JPS6334341Y2 (en) | ||
| EP0507311A2 (en) | High frequency amplifying apparatus | |
| JP2797865B2 (en) | Variable voltage attenuator | |
| JPH021945Y2 (en) | ||
| KR960005177Y1 (en) | Input Current Compensation Circuit of Amplifier | |
| Nauta et al. | A High-Performance Integrated if Amplifier and Detector for an AM Upconversion Receiver |