JPH03249624A - Manufacture of liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent electrostatic breakage in manufacturing process by removing a semiconductor layer in the same process with the selective removal of a protection film after the protection film is deposited on the surface of a transparent substrate, and disconnecting the short-circuited wiring. CONSTITUTION:Semiconductor layers AS and DO which connect the short- circuited wirings GSW and DSW decrease in resistance value through photoconducting operation when irradiated with light, thereby short-circuiting the short-circuited wirings mutually. Namely, the short-circuit wirings are short- circuited mutually by irradiating the semiconductor layers with the light throughout the process wherein a lower transparent glass substrate SUB1 is taken out of the jig of a CVD device after the protection film PSV1 is deposited by a plasma CVD method which easily generates static electricity in manufacturing the liquid crystal display device. Consequently, an electrostatic breakdown between a scanning signal line and a video signal line, a source electrode or drain electrode and a gate electrode, etc., is precluded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a liquid crystal display device, particularly an active matrix type liquid crystal display device using thin film transistors and the like.

[Prior Art] An active matrix type liquid crystal display device is one in which a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix.

Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so the active method has better contrast than the so-called simple matrix method, which uses a time-division drive method, especially in color. It is becoming an indispensable technology. A typical switching element is a thin film transistor (TPT).

Each pixel is arranged in an area surrounded by multiple horizontally extending scanning signal lines (gate signal lines) and vertically extending video signal lines (drain signal lines) that intersect with the horizontally extending scanning signal lines. has been done. An external terminal to which a scanning signal is applied is connected to one end of the scanning signal line, and an external terminal to which a video signal is applied is connected to one end of the video signal line. Each external terminal is arranged around the outer periphery of a liquid crystal display section (liquid crystal display panel). Each pixel is composed of a series circuit of a thin film transistor and a transparent pixel electrode.

For example, as described in Japanese Unexamined Patent Publication No. 61-59475, during the manufacturing process of a liquid crystal display device, the external terminal is configured integrally with other adjacent external terminals and short-circuited. Specifically, before cutting the transparent glass substrate, wires that commonly short-circuit the external terminals for scanning signals, external terminals for video signals, and external terminals for common signals are connected further outside of these external terminals. It is located around the area. A liquid crystal display device configured in this manner maintains the potential between each signal line (such as between a scanning signal line and a video signal line) even if static electricity induced during the manufacturing process is applied to these signal lines. Since they are equal, there is an advantage that electrostatic damage to the wiring (for example, short circuit between the scanning signal line and the video signal line due to damage to the gate insulating film) can be prevented. The processing steps in which static electricity is generated include a step of depositing an insulating film by plasma CVD, a step of removing a substrate from a jig after depositing a passivation film, a rubbing step of an alignment film, a transportation step, and the like.

After wiring formation is completed, the short circuit wiring is also cut at the same time as the transparent glass substrate is cut.

The active matrix liquid crystal display device using TPT is described in, for example, "12.5-inch active matrix color liquid crystal display with redundant configuration," Nikkei Electronics, pp. 193-210, 1986.
It is known for being published by Nikkei McGraw-Hill on February 15th.

[Problem to be solved by the invention]

However, during the manufacturing process of the above-mentioned liquid crystal display device,
Since each external terminal is short-circuited, it is not possible to test electrical characteristics such as short-circuit conditions between scanning signal lines, video signal lines, or between scanning signal lines and video signal lines, and the characteristics of thin film transistors. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can prevent electrostatic damage during the manufacturing process in a liquid crystal display device and also enable electrical characteristic testing during the manufacturing process.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing steps for achieving the above object in the liquid crystal display device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a liquid crystal display device of the present invention includes scanning signal lines and video signal lines arranged on the outer peripheral surface of a liquid crystal display portion of a transparent substrate. a plurality of external terminals of the line, a first short-circuit wiring that is provided on the surface of the outer periphery of the external terminal, and that short-circuits each of the scanning signal lines, and a second short-circuit wiring that short-circuits each of the video signal lines; a discharge portion in which the first and second short-circuit wirings are close to each other with a small gap therebetween;
In the method for manufacturing a liquid crystal display device, the liquid crystal display device has a semiconductor layer that connects a short-circuit wiring, and a protective film that covers the scanning signal line and the video signal line, after depositing the protective film on the surface of the transparent substrate. The method is characterized by comprising a step of removing the semiconductor layer and disconnecting the first and second short-circuit wirings in the same step as or after the step of selectively removing the semiconductor layer.

Further, the semiconductor layer is formed in the same process as a semiconductor layer used in a thin film transistor provided in the liquid crystal display section.

Further, the conductive film constituting the first and second short-circuit wirings that are close to each other with a small gap in the discharge portion is formed of a film that is difficult to be blown out.

[Function] When the semiconductor layer that connects the short-circuited wires is irradiated with light, the resistance value decreases due to the photoconductive (photoconductive) effect.
Shorting Wirings can be shorted together. That is, during the manufacturing process of a liquid crystal display device, especially in the process of removing the lower transparent glass substrate from the jig of the CVD equipment after depositing a protective film by plasma CVD, which tends to generate static electricity, the semiconductor layer is constantly exposed to light. By irradiating and short-circuiting the short-circuit wiring, it is possible to prevent electrostatic breakdown of the insulation between the scanning signal line and the video signal line, between the source electrode or the drain electrode, and the gate electrode, etc. In addition, after the semiconductor layer is removed, gaps are formed between the short-circuit wirings, so if static electricity is generated in a process where static electricity is likely to occur after the semiconductor layer is removed, discharge will occur in the gaps, resulting in static electricity damage. Since it is prevented, there is no need to irradiate the light.

Further, the short circuit wiring and the discharge portion according to the present invention can all be formed in the same manufacturing process as the scanning signal line, video signal line, and external terminal, so the number of manufacturing processes can be reduced.

Furthermore, since the conductive film constituting the short-circuit wiring that approaches each other across a small gap in the discharge portion is made of a film that is difficult to be blown out, it will not be blown out when a semiconductor layer or the like is etched.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to an active matrix color liquid crystal display device.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

Figures 1A (a) to (j) are process cross-sectional views showing the method for manufacturing a liquid crystal display device of the present invention, and Figure 1B is a plan view of the main parts of a liquid crystal display unit according to the present invention, including external terminals and static electricity. Figure 1C is a diagram showing the destruction prevention wiring (short-circuit wiring) and the discharge part.
The sectional view taken along the I-1 cutting line in Figure 1B and Figure 1D are as follows:
The sectional view taken along the section line ■-■ in Figure 1B and Figure 1E are as follows:
FIG. 2 is a schematic plan view of a transparent glass substrate showing the arrangement of short-circuit wiring.

FIG. 2A is a plan view showing one pixel and its surroundings of an active matrix color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section taken along the nB-IIB cutting line in FIG. 2A and the display panel. 2C is a cross-sectional view taken along the nc-nc line in FIG. 2A; FIG.

Moreover, FIG. 3 (main part plan view) shows a plan view when a plurality of pixels shown in FIG. 2A are arranged.

(Pixel arrangement) As shown in Figure 2A, each pixel is connected to two adjacent scanning signal lines (gate signal line or horizontal signal line) GL and two adjacent video signal lines (drain signal line or vertical signal line). Signal line)
Within the intersection area with DL (within the area surrounded by four signal lines)
It is located in Each pixel is a thin film transistor TPT,
It includes a pixel electrode ITOI and an additional capacitor Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction.

Overall cross-sectional structure of the panel> As shown in Figure 2B, a thin film transistor TPT and a transparent pixel electrode IT○1 are formed on the lower transparent glass substrate SOBl side with respect to the liquid crystal layer LC, and a transparent pixel electrode IT○1 is formed on the upper transparent glass substrate 5UB2 side. , a color filter FIL, and a light-shielding black matrix pattern BM are formed. The lower transparent glass substrate 5UBI side has a thickness of, for example, about 1.1 [mm].

The central part of Figure 2B shows a cross section of one pixel,
The left side shows a cross section of the left edge portion of the transparent glass substrates SUB1 and 5UB2 where external lead wiring is present. The right side shows a cross section of the right edge portion of the transparent glass substrates SUB1 and 5UB2 where no external lead wiring is present.

The sealing material SL shown on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the liquid crystal sealing opening (
It is formed along the entire edge periphery of the transparent glass substrates SUB1 and 5UB2 except for those (not shown). The sealing material SL is made of, for example, epoxy resin.

The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate 5UB2 is connected at least in one place to an external lead wiring formed on the side of the lower transparent glass substrate SUB1 with a silver paste material SIL. This external lead wiring includes the aforementioned gate electrode GT, source electrode SDI,
They are formed in the same manufacturing process as the drain electrode SD2.

Alignment films 0RII and 0RI2, transparent pixel electrode ITOI,
Common transparent pixel electrode IT○2, protective film PSVI and PSV
2. Each layer of the insulating film GI is formed inside the sealing material SL. The polarizing plate POL has a lower transparent glass substrate 5UB
I and the outer surface of the upper transparent glass substrate 5UB2.

The liquid crystal LC has a lower alignment film 0R that sets the direction of the liquid crystal molecules.
II and the upper alignment film 0RI2, and sealed by a sealing portion SL.

The lower alignment film 0RII is a lower transparent glass substrate SUB l
The protective film PSVI is formed on the side protective film PSVI.

On the inner surface (liquid crystal side) of the upper transparent glass substrate 5UB2, a light shielding film BM, a color filter FIL, and a protective film PSV are provided.
2. A common transparent pixel electrode (COM) ITO2 and an upper alignment film 0RI2 are sequentially laminated.

In this liquid crystal display device, the layers on the lower transparent glass substrate SUBl side and the upper transparent glass substrate 5UBZ side are formed separately, and then the upper and lower transparent glass substrates 5UBl and 5UBZ are formed separately.
2 are stacked on top of each other and a liquid crystal LC is sealed between the two.

(Thin Film Transistor TPT) The thin film transistor TPT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.

The thin film transistor TPT of each pixel has three
It is divided into two (plurality) of thin film transistors (divided thin film transistors) TFTI, TFT2, and TFT3. Each of the thin film transistors TPT1 to TFT3 has substantially the same size (channel length and width are the same).
It consists of

Each of the divided thin film transistors TPT1 to TFT3 mainly includes a gate electrode GT, a gate insulating film GI, i
It is composed of an amorphous Si semiconductor layer AS (intrinsic, not doped with conductivity type determining impurities), a pair of source electrode SDI and drain electrode SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following explanation as well, for convenience, one side is fixed as a source and the other side is fixed as a drain.

<Gate Electrode GT) As shown in detail in FIG. 4 (a plan view depicting only the layers gl, g2, and AS in FIG. 2A), the gate electrode GT extends from the scanning signal line GL in the vertical direction (FIGS. 2A and 2A). It is constructed in a shape that protrudes upward (in FIG. 4) (branched into a T-shape). The gate electrode GT is configured to protrude to the formation region of each of the thin film transistors TPT1 to TFT3. Thin film transistor TPT 1~
The gate electrodes GT of the TFTs 3 are integrally formed (as a common gate electrode) and are formed continuously to the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in the formation region of the thin film transistor TPT. first conductor 11
1g1 is, for example, chromium (Cr) formed by sputtering.
It is formed using a film with a film thickness of about 1000 [A].

As shown in FIGS. 2A, 2B, and 4, the gate electrode GT is formed to be thicker than the semiconductor layer AS (as viewed from below) so as to completely cover the semiconductor layer AS. Therefore, a backlight B such as a fluorescent lamp is placed below the board SUB 1.
When L is attached, the second opaque Cr gate electrode GT forms a shadow, and the semiconductor layer AS is not irradiated with backlight light, making it difficult for the conductive phenomenon caused by light irradiation, that is, deterioration of the off-characteristics of the TPT, to occur. The original size of the gate electrode GT is the minimum width required to span between the source/drain electrodes SDI and SD2 (including the alignment margin between the gate electrode and the source/drain electrodes), and the channel width. The depth length that determines W is determined by the ratio to the distance (channel length) L between the source and drain electrodes, that is, the factor W/L that determines the mutual conductance gm.

The size of the gate electrode in this embodiment is of course larger than the original size mentioned above.

Considering only the gate and light shielding functions of the gate electrode GT, the gate electrode and its wiring GL may be integrally formed in a single layer, and in this case, Sl is used as the opaque conductive material.
Al containing Al, pure Al.

Also, A1 containing Pd can be selected.

(Scanning Signal Line GL> The scanning signal line GL is composed of a composite film consisting of a first conductive film GL and a second conductive film g2 provided on top of the first conductive film GL. g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is configured integrally with the first conductive film g1.The second conductive film g2 is formed using, for example, an aluminum (AΩ) film formed by sputtering. The second conductive film g2 reduces the resistance value of the scanning signal line GL and increases the signal transmission speed (improves the writing characteristics of pixel information).
It is structured so that it can be achieved.

Further, in the scanning signal line GL, the width of the second conductive film g2 is smaller than the width of the first conductive film gl. That is, the side wall of the scanning signal line OL has a gradual step shape.

Gate insulating film GI) The insulating film GI is the thin film transistor TPT1 to TFT3.
It is used as a gate insulating film for each.

The insulating film CI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD, and has a film thickness of approximately 3000 mm.

(Semiconductor Layer AS) As shown in FIG. 4, the 1-type semiconductor layer AS is used as a channel formation region for each of the thin film transistors TPT1 to TFT3 divided into a plurality of parts.The 1-type semiconductor layer AS
is formed of an amorphous silicon film or a polycrystalline silicon film, and is formed with a film thickness of about 1,800 mm.

This l-type semiconductor layer AS is made of Si by changing the components of the supplied gas.
, N, are formed in the same plasma CVD apparatus following the formation of the gate insulating film CI, without being exposed to the outside from the apparatus. Also, P for ohmic contact
N4″ layer d doped with .

(FIG. 2B) is similarly formed continuously to a thickness of about 400 [Al]. After that, the lower substrate SUB 1 is taken out from the CVD equipment, and the N+ layer do
and one layer AS is patterned into independent islands as shown in FIGS. 2A, 2B, and 4.

As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS is located at the intersection of the scanning signal line GL and the video signal line DL (
The cross-over section) is also provided between the two. This intersection i-type semiconductor layer AS is connected to the scanning signal line G at the intersection.
It is configured to reduce short circuits between L and the video signal line DL.

2A, 2B, and 5 (layers d1 to d1 in FIG. 2A) As shown in detail in the plan view (plan view depicting only d3), they are provided separately on the semiconductor layer AS.

Each of the source electrode SDI and drain electrode SD2 is N+
From the lower layer side in contact with the type semiconductor layer do, the first conductive film d1
, a second conductive film d2, and a third conductive film d3 are sequentially stacked on top of each other. the first conductive film d1 of the source electrode SDI;
The second conductive film d2 and the third conductive film d3 are the drain electrode S
They are formed in the same manufacturing process as each of D2.

The first conductor@gdl uses a chromium film formed by sputtering and has a film thickness of 500 to 1000 [in this example, 60
The film thickness is approximately 0 [A]. When forming a chromium film thicker, the stress increases, so 2000
It is formed within a range that does not exceed the film thickness of [A].

The chromium film has good contact with the N+ type semiconductor layer do. The chromium film constitutes a so-called barrier layer that prevents aluminum of the second conductive film d2, which will be described later, from diffusing into the N" type semiconductor layer d○. In addition to the chromium film, the first conductive film d1 includes: High melting point metals (Mo, Ti, Ta,
W) film, high melting point metal silicide (MoSi, , TiSi
, TaSi, WSi, ) film.

After patterning the first conductive film d1 by photo processing, the N1 layer d○ is removed using the same photo processing mask or using the first conductive film J[idl as a mask. That is, the portions of the N'' layer do remaining on the i layer AS except for the first conductor tidl are removed by the self-line.

At this time, since the N4 layer do is etched so that its entire thickness is removed, the i layer AS is also slightly etched at its surface, but the extent can be controlled by the etching time.

Thereafter, the second conductive film d2 is formed by aluminum sputtering to a thickness of 3000 to 4000 [people] (in this embodiment, a film thickness of about 3000 [people]). The aluminum film has less stress than the chromium film, can be formed thicker, and is configured to reduce the resistance values of the source electrode SDI, drain electrode SD2, and video signal line DL.

The second conductive 1i film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive, in addition to an aluminum film.

After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Indium-T) formed by sputtering.
in-Oxide I T○: Consisting of 1
Film thickness of 000 to 2000 [A] (in this example, +20
0 [film thickness of about A]. This third conductive film d
3 constitutes the source electrode SDI, drain electrode SD2, and video signal line DL, and also constitutes the transparent pixel electrode IT○1.

First conductive film d1 of source electrode SDI, drain electrode SD
Each of the two first conductive films d1 extends further inward (into the channel region) than the upper second conductive film d2 and third conductive film d3.

In other words, the first conductive film d1 in these parts is the layer d
The structure is such that the gate length of the thin film transistor TPT can be defined independently of 2 and d3.

As described above, the source electrode SDI is connected to the transparent pixel electrode IT.
Connected to OI. The source electrode SDI has a step shape of the i-type semiconductor layer AS (the thickness of the first conductive film g1, the thickness of the N+ layer d
It is configured along a step corresponding to the sum of the film thickness of the i-type semiconductor layer AS and the film thickness of the i-type semiconductor layer AS. Specifically, the source electrode SDI includes a first conductive film dl formed along the step shape of the i-type semiconductor layer AS, and a first conductive film dl formed along the step shape of the i-type semiconductor layer AS.
A second conductive film d2 formed on the upper part of i with a smaller size on the side connected to the transparent pixel electrode ITOI, and a third conductive film connected to the first conductive film d1 exposed from this second conductive film. d3. Source electrode SDI
The second conductive film d2 cannot be formed thickly because the chromium film of the first conductive film dl increases stress and cannot overcome the step shape of the i-type semiconductor layer AS.
It is designed to overcome. In other words, the step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly,
This greatly contributes to reducing the resistance value of the source electrode SDI (the same applies to the drain@&SD2 and the video signal 11DL). Since the third conductive film d3 cannot overcome the step shape caused by the type 1 semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2, the exposed first conductive film dl configured to connect.

The first conductive film d1 and the third conductive film d3 not only have good adhesion but also have a small step shape at the connecting portion between them, so that they can be reliably connected.

(Pixel electrode IT○1) The transparent pixel electrode ITOI is provided for each pixel and constitutes one of the pixel electrodes of the liquid crystal display section.The transparent pixel electrode ITOI is a thin film transistor TPT divided into a plurality of pixels. The transparent pixel electrodes E1 to E3 are divided into three transparent pixel electrodes (divided transparent pixel electrodes) El, E2, and E3 corresponding to each of TPT1 to TPT3.The transparent pixel electrodes E1 to E3 are each connected to the source electrode SDI of the thin film transistor TPT. ing.

Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area.

In this way, the thin film transistor TPT of one pixel is divided into a plurality of thin film transistors TPT1 to TFT3, and the thin film transistors TPT1 to TFT3 divided into the plurality of thin film transistors TPT1 to TFT3.
By connecting each of the transparent pixel electrodes E1 to E3 divided into a plurality of parts to each of the divided parts (for example, T
Even if PTI) becomes a point defect, it is no longer a point defect when viewed from the perspective of the entire pixel (TPT2 and TPT3 are not defects), so the probability of a point defect can be reduced and the defect can be made difficult to see.

Furthermore, by configuring each of the divided transparent pixel electrodes E1 to E3 of the pixel to have substantially the same area, each of the transparent pixel electrodes El to E3 and the common transparent pixel electrode IT○2 can be configured to have substantially the same area. The liquid crystal capacitance (Cpix) can be made uniform.

Protective Film PSVI) A protective film PSVI is provided over the thin film transistor TPT and the transparent pixel electrode ITOI. Protective film P S
V1 is mainly formed to protect the thin film transistor TPT from moisture, etc., and a material with high transparency and good moisture resistance is used. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and is formed to have a thickness of about 8000 [layers].

<Light-shielding film BM> A shielding film BM is provided on the upper substrate 5UB2 side to prevent external light (light from above in FIG. 2B) from entering the l-type semiconductor layer AS used as a channel formation region, The pattern is as shown by the hatching in FIG. In addition, FIG. 6 shows the ITO film layer d3 in FIG. 2A,
FIG. 2 is a plan view depicting only a filter layer FIL and a light shielding film BM.

The light-shielding film BM is formed of, for example, an aluminum film or a chromium film that has a high light-shielding property, and in this embodiment, the chromium film is formed by sputtering to a thickness of about 1300 [layers].

Therefore, the common semiconductor layer AS of TPT1 to TPT3 is sandwiched between the upper and lower light shielding films BM and the thick gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG. There is. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the semiconductor layer AS from light and serving as a black matrix.

In addition, the backlight is attached to the 5UB2 side, and the 5UBI
can also be set as the observation side (external n8 side).

Common electrode ITO2> The common transparent pixel electrode IT○2 is connected to the lower transparent glass substrate SU.
Opposing the transparent pixel electrode ITOI provided for each pixel on the B1 side, the optical state of the liquid crystal changes in response to the potential difference (field) between each pixel electrode IT○1 and the common electrode IrO2. This common transparent pixel electrode IT02 has a common voltage V
com is applied. The common voltage V com is a low level drive voltage Vdm1n applied to the video signal line DL and a high level drive voltage Vdma.
It is an intermediate potential with x.

Color Filter FIL) The color filter FIL is constructed by coloring a dyed base material made of a resin material such as an acrylic resin with a dye.

The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (Fig. 7), and is colored differently (Fig. 7 shows the third conductive film layer d3 and the color filter layer FIL in Fig. 3). (The R, G, and B filters are each 45° 135' with a cross hatch). The color filter FIL is formed thick so as to cover all of the pixel electrodes ITOI (El to E3) as shown in FIG. It is formed inside the periphery of the electrode ITOI.

Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate 5UB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps.

The protective film PSV2 is provided to prevent the dyes used to dye the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is made of, for example, a transparent resin material such as acrylic resin or epoxy resin.

(Pixel Arrangement) As shown in FIGS. 3 and 7, a plurality of pixels of the liquid crystal display section are arranged in the same column direction as the direction in which the scanning signal MGL extends, and are arranged in pixel columns XI, X2°X3. Each pixel column X1.X2.X3.X constitutes each of X4.
4. Each pixel of... is a thin film transistor TFT1
~TFT3 and transparent pixel electrodes El~E3 are arranged in the same position. That is, odd pixel columns XI, X3 .・
Each pixel of... is a thin film transistor TPT1-T
The arrangement position of PT3 is on the right side, and the arrangement position of transparent pixel electrode El-E3 is on the left side. Odd pixel columns Xi, X3.
. . , adjacent even-numbered pixel columns in the row direction X2. X4.
. . are arranged in odd-numbered pixel columns XI, X3 . ...
Each pixel is made up of pixels that are symmetrically turned upside down with respect to the extending direction of the video signal line DL.

That is, pixel row X2. X4. Each pixel of...
The thin film transistors TFTI to TFT3 are arranged on the left side, and the transparent pixel electrodes E1 to E3 are arranged on the right side. Then, pixel row X2. X4. Each pixel in pixel columns XI, X3 . . . are moved (shifted) by half a pixel interval in the column direction. In other words, if each pixel interval of the pixel column X is 1.0 (1,0 pitch), then the next stage pixel column X has each pixel interval of 1.
0, and is shifted by 0.5 pixel interval (0.5 pitch) in the column direction with respect to the previous pixel column X. The video signal line DL extending in the row direction between each pixel is configured to extend in the column direction by a half pixel interval (0.5 pitch) between each pixel column X.

As a result, as shown in FIG. 7, the pixels on which the predetermined color filter of the previous pixel row The pixels on which color filters are formed (for example, the pixels on which red filter R is formed in pixel column x4) are separated by 1.5 pixel intervals (1.5 pitches), and the RGB color filters FIL are arranged in a triangular arrangement. Become. Color filter FIL
The triangular arrangement structure of RGB can improve the mixing of each color, thereby improving the resolution of a color image.

Moreover, since the video signal line DL extends in the column direction by only half a pixel interval between each pixel column X, it does not intersect with the adjacent video signal line DL. Therefore, video signal JJ
It is possible to eliminate the routing of the DL and reduce its occupied area, and it is also possible to eliminate the detour of the video signal line DL and eliminate the multilayer wiring structure.

Equivalent circuit of entire display panel FIG. 8 shows the circuitry of this liquid crystal display device.

X i G, X i + I G, ... are video signals #ID connected to the pixels where the green filter G is formed.
It is L.

Xi B, Xi+I B, . . . are video signal lines DL connected to pixels in which the blue filter B is formed.

Xi+IR, Xi+2R, =- are video signal lines DL connected to the pixels in which the red fill '2R is formed. These video signal lines DL are selected by a video signal drive circuit. Yi is a scanning signal line OL that selects the pixel column XI shown in FIGS. 3 and 7.

Similarly, Yi+1. Yi+2. Each of the pixel rows X2 . X3. . . . is a scanning signal line GL that selects each of the following. These scanning signal lines GL are connected to a vertical scanning circuit.

(Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 to E3 is connected to a thin film transistor T.
At the end opposite to the end connected to PT, it is bent into an L-shape so as to overlap with the adjacent scanning signal line OL. As is clear from FIG. 2C, this superposition allows each of the transparent pixel electrodes E1 to E3 to be connected to one t-pole PL.
2, and a storage capacitor element (electrostatic capacitor element) Cadd is configured in which the adjacent scanning signal line GL is the other electrode PLI. The dielectric film of this storage capacitor element Cadd is an insulating film C used as a gate insulating film of the thin film transistor TPT.
It is composed of the same layer as I.

As is clear from FIG. 4, the storage capacitor Cadd is formed in the widened portion of the first layer g1 of the gate line OL. Note that the portion of the layer g1 that intersects with the drain line DL is made thin in order to reduce the probability of short circuit with the drain line.

Similar to the source electrode SDI, a portion between each of the transparent pixel electrodes El-E3 that are overlapped to form the storage capacitor element Cadd and the capacitor electric tangent line (gl) is provided with In order to prevent the transparent pixel electrode ITOI from disconnecting, an island region made up of the first conductive film d1 and the second conductive film d2 is provided. This island region is configured to be as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel @HARUITOI.

Equivalent circuit of additional capacitance Cadd and its operation> FIG. 9 shows an equivalent circuit of the pixel shown in FIG. 2A. In FIG. 9, Cgs is the gate electrode GT of the thin film transistor TPT.
and a parasitic capacitance formed between the source electrode SD1.

The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cpi
x is a liquid crystal capacitance formed between the transparent pixel electrode ITOI (PIX) and the common transparent pixel electrode IT○2 (COM).

The dielectric film of the liquid crystal capacitor Cpix is the liquid crystal LC1 protective film PSv.
1 and alignment film ORI 1. It is ORI 2.

Vlc is a midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Via when the TFT switches. Expressing this situation using the formula, △V lc = ((Cgs/ (Cgs+Cadd+
Cpix) ) X△Vg. Here, ΔVlc is Δ
It represents the change in midpoint potential due to Vg. This change Δv
The IC causes a DC component applied to the liquid crystal, but the larger the holding capacitance Cadd is, the smaller the value can be reduced.

In addition, the holding capacitor Cadd also has the effect of lengthening the discharge time, so that video information is stored for a long time after the TPT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching liquid crystal display screens.

As mentioned above, since the gate electrode GT is made large enough to completely cover the semiconductor layer AS, the overlapping area with the source/drain electrodes SDI and SD2 increases, and therefore the parasitic capacitance Cgs increases, and the midpoint potential Vlc decreases. This has the opposite effect of becoming more susceptible to the influence of the gate (scanning) signal Vg. However, by providing the holding capacitor Cadd, this disadvantage can also be eliminated.

The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4・Cp
ix(Cadd(8・Cpjx), superposition capacitance Cgs
8 to 32 times <8・Cgs<, Cadd<32・
Cgs).

(Connection method of additional capacitance Cadd electrode line) As shown in FIG. )IrO2.As shown in FIG. 2B, the common transparent pixel electrode IT○2 is connected to the external lead wiring by a silver paste material SIL at the peripheral part of the liquid crystal display device.Moreover, this external lead wiring Some of the conductive layers (gl and g2) are formed in the same manufacturing process as the scanning signal line GL.As a result, the final stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode ITO2. can.

Alternatively, as shown by the dotted line in FIG. 8, the capacitor electrode line GL at the final stage (first stage) may be connected to the scanning signal line GL at the first stage (last stage). Note that this connection can be made by internal wiring within the liquid crystal display section or external wiring.

DC component cancellation by additional capacitance Cadd scanning signal> This liquid crystal display device is based on the DC cancellation method (DC cancellation method) described in Japanese Patent Application No. 62-95125 previously filed by the applicant of the present application. Diagram (time chart)
As shown in FIG. 3, by controlling the drive voltage of the scanning signal line DL, the DC component applied to the liquid crystal LC can be further reduced. In FIG. 1○, Vi is the drive voltage of an arbitrary scanning signal line GL, and Vi+1 is the drive voltage of the scanning signal line OL at the next stage. Vee is a low-level drive voltage Vdm1n% applied to the scanning signal line GL, and Vdd is a high-level drive voltage Vdma applied to the video signal line DL.
It is x. Midpoint potential Vl at each time L=t to 4
The voltage change ΔV, ˜Δv4 of c (see FIG. 9) is as follows.

1=1: △V, = -(Cgs/C)・V 2
t = t,: △V, = + (Cgs/C) (V 1
+V 2) - (Cadd/C) ・V 2 = 3: △V, = - (Cgs/C) ・V
1 + (Cadd/C)・(V1+V2) 1=1. : △V4=-(Cadd/C
) ・V Also, total capacitance of pixels: C=
Cgs + Cpix + Cadd Here, if the drive voltage applied to the scanning signal line GL is sufficient (see note below), the DC voltage applied to the liquid crystal LC is △v, +△V, = (Cadd - V 2 -Cgs-
V 1 )/C, so Cadd-V 2 =
When Cgs-V is 1, the DC voltage applied to the liquid crystal LC becomes 0.

[Note] At times t1 and t, the change in scanning line v1 affects the midpoint potential vlc, but during the period from t to 1c, the midpoint potential ■1c is the same as the video signal potential through the signal line Xi. potential (sufficient writing of video signal).

The potential applied to the liquid crystal is almost determined by the potential immediately after the TPT is turned off (the TPT off period is overwhelmingly longer than the on period). Therefore, the calculation of the DC component applied to the liquid crystal requires a period of 1
-3 can be almost ignored, and it is only necessary to consider the influence of the transient at the potential immediately after the TPT is turned off, that is, at time 3, and.

Note that the polarity of the video signal Vi is inverted for each frame or line, and the DC component due to the video signal itself is zero.

In other words, the DC cancellation method uses the drive voltage applied to the storage capacitance element Cadd and the next stage scanning signal line GL (capacitance electrode line) to push up the drop caused by the pull-in of the midpoint potential Vlc by the superimposed capacitance Cgs. The DC component applied to the LC can be made extremely small. As a result,
The liquid crystal display device can improve the lifespan of the liquid crystal LC. Of course, if the gate GT is increased in size to improve the light shielding effect, the value of the storage capacitor Cadd may be increased accordingly.

<Measures to prevent static electricity damage> Figure 1B (a plan view of the main parts of the liquid crystal display section) shows the following measures to prevent wiring damage caused by static electricity induced during the manufacturing process.
The wiring for preventing electrostatic damage (short-circuit wiring) and the discharge area are shown. Cross sections taken along the I-1 section line and the ■-■ section line in FIG. 1B are shown in FIGS. 1C and 1D, respectively. Note that the cross-sectional structure shown in FIG. 1C is slightly different from the cross-sectional structure shown in the embodiment of FIG. 2B.

In Figure 1B, GP is the lower transparent glass substrate SUB
external terminals of a plurality of scanning signal lines GL formed on the surface of l;
DP is an external terminal of the video signal line DL, GSW is a short-circuit wiring that shorts each scanning signal line GL (wire for preventing electrostatic damage),
DSW is a short-circuit wiring that short-circuits each video signal line DL, SP is a connection part that connects each external terminal GP%DP and short-circuit wiring GSW, DSW, and ED is a short-circuit wiring that connects short-circuit wiring GSW and DSW with a small gap between them. The discharge parts are arranged close to each other, PJ is the protrusion of the discharge part ED, GAP is the gap between the protrusions PJ, PS
VI is a protective film.

As shown in FIGS. 1B and 1C, the liquid crystal display device has a thin film transistor TPT on the inner surface (liquid crystal side) of a lower transparent glass substrate SUB 1 having a thickness of about 1.11TIIT1. Thin film transistor TPT
mainly consists of a gate electrode GT, an insulating film GI used as a gate insulating film, and a gate electrode 1 used as a channel forming region.
type semiconductor layer AS, source electrode (or drain electrode) S
It is composed of DI and a drain electrode (or source electrode) SD2.

The gate electrode GT is made of carbon deposited by sputtering, for example.
It is formed using the r film g1 with a film thickness of about 1100. The gate electrode GT is formed in the same manufacturing process (same conductive layer) as the scanning signal line GL, and is integrated with the scanning signal line GL. The scanning signal line GL is connected to the IT on the Cr film g.
It is formed of a composite film in which O films g2 are laminated. The IT◯ film g2 is deposited by sputtering and has a thickness of about 1,400 layers. This ITO film g2 mainly covers the scanning signal line GL.
It is configured to reduce the connection resistance value between and TAB (external signal input means) and increase the transmission speed of the scanning signal. The gate electrode GT is formed integrally with the lower Cr film g1 of the scanning signal line GL. As shown in FIG. 1B, the scanning signal lines GL extend horizontally, and a plurality of scanning signal lines GL are arranged vertically.

At least one end of the scanning signal line GL is connected to an external terminal CP at the outer periphery of the liquid crystal display section. A scanning signal is applied to this external terminal GP. A plurality of external terminals CP are arranged vertically on the surface of the lower transparent glass substrate SUB 1 in FIG. 1B. The external terminal GP is configured integrally with the scanning signal line GL.

That is, the external terminal CP is made of Cr as shown in FIG. 1D.
It is composed of a composite film in which an ITO film g2 is laminated on a film g2. The ITO film g2 is formed to have a larger size than the Cr film g1, and is configured to cover the Cr film g1.

The insulating film GI is formed above the gate electrode GT and the scanning signal line GL, except for the external terminal GP.

The insulating film GI is formed using, for example, a silicon nitride film deposited by a plasma CVD method, and has a thickness of about 3,700.

The i-type semiconductor layer AS is formed in an island shape above the gate insulating film GI. The l-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film deposited by the CVD method, and has a thickness of about 2
It is formed with a thickness of about 200 people. l-type semiconductor layer A
S is mainly used as a channel forming region of a thin film transistor TFT.

Each of the source electrode SDI and drain electrode SD2 is l
They are provided separately on the type semiconductor layer AS.

The source electrode SDI and the drain electrode SD2 are operationally switched between source and drain when the bias polarity of the circuit changes. In other words, the thin film transistor TPT has a bidirectional structure like the insulated gate transistor FET.

Each of the source electrode SDI and drain electrode SD2 is
For example, the l-type semiconductor layer A
From the lower layer side in contact with S, the n+ type semiconductor layer do, CrM
d1, All! It is composed of a composite film in which Id2 is sequentially laminated, and an ITO film d3 is connected to a Cr film cll.

The n+ type semiconductor layer do is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of approximately 400 nm. The n''' type semiconductor layer dO is composed of the l type semiconductor layer AS and CrP.
It is configured to reduce the contact resistance value with Adi. The Crgdl is deposited by sputtering, for example, and has a thickness of about 6
It is formed with a film thickness of about 0.00 people. The ITO film d3 is deposited by, for example, a sputtering method, and is formed to have a thickness of about 1,400 layers. This IT○ film d3 mainly consists of transparent pixel electrode IT○1.
It is designed to form a For example, the A1 film d2 is deposited continuously by sputtering in the same apparatus after sputtering the Cr film d1, and is formed to have a thickness of about 3,700.

The A1 film d2 mainly reduces the resistance value of the video signal line DL,
It is configured to increase the transmission speed of video signals.

The video signal line DL, like the source electrode SDI and drain electrode SD2, is formed of a composite film in which a Cr' film d1 and an Al film d2 are sequentially laminated. The video signal 19DL is connected to the scanning signal line G as shown in FIG. 1B.
It extends in the vertical direction intersecting L, and a plurality of them are arranged horizontally.

A transparent pixel electrode ITOI provided for each pixel is connected to the source electrode SDI. Transparent pixel electrode ITO
I constitutes one of the pixel electrodes of the liquid crystal display section. The transparent pixel electrode ITOI is provided on the insulating film GI, and is formed of the IT○ film d3. The drain electrode SD2 is configured integrally with the video signal line DL.

At least one end of the video signal line DL is connected to an external terminal DP at the outer periphery of the liquid crystal display section. A video signal is applied to this external terminal DP. A plurality of external terminals DP are arranged horizontally on the surface of the lower transparent glass substrate SUB 1 in FIG. 1B.

The external terminal DP is configured integrally with the video signal line DL. That is, the external terminal DP is connected to the IT○ film d on the Cr film gl.
It is composed of a composite membrane made by laminating three layers. ITO1jd3
is formed with larger dimensions than the Cr film g1, and the Cr film gl
It is configured to cover.

The thin film transistor TPT and the transparent pixel electrode ITO
A protective film PSVI is provided on I. protective film ps
vi is formed mainly to protect the thin film transistor TPT from moisture, etc., and a material having high transparency and good moisture resistance is used. The protective film PSVI is formed of, for example, a silicon oxide film or a silicon nitride film deposited by a plasma CVD method, and has a thickness of about 1 μm.

A light shielding film LS is provided above the protective film PSV1 on the thin film transistor TFT so that external light does not enter the l-type semiconductor layer AS used as a channel formation region. The light-shielding film LS is made of, for example, an A1 film (or an Al-3 film) so as to have high light-shielding properties and conductivity.
It is formed of materials such as Al-Cu), Cr, etc., and is deposited by sputtering to a thickness of about 1,000 to 4,000 layers.

During the manufacturing process (including assembly process) of the liquid crystal display device, the scanning signal line GL, video signal line DL, external terminal GP
, and the same process as forming the external terminal DP, a short-circuit wiring GSW that short-circuits each scanning signal line GL, and a short-circuit wiring DSW that short-circuits each image signal line are formed. FIG. 1E schematically shows the short-circuited state of the short-circuited wirings GSW and DSW. Two short-circuiting wirings GSW are provided, one on each side of the figure, to short-circuit each scanning signal line GL. Two short-circuiting wirings DSW are provided, one at the top and one at the top and bottom of the figure, to short-circuit each video signal line DL. The four short-circuit wirings GSW and DSW are close to each other with a small gap separated by discharge parts ED provided at the four corners of the transparent glass substrate. A detailed view of the discharge section ED is shown in FIG. 1B.

The manufacturing process of the short-circuit wiring and discharge portion for preventing electrostatic damage is shown in FIGS. 1A (a) to (j). Each figure in Figure 1A represents a part of the discharge section, for example ■-m in Figure 1B.
A cross section taken along the cutting line is shown.

First, at the same time as forming the gate electrode GT of the thin film transistor TPT and the chromium (Cr) film g1 and IT○ film g2 of the scanning signal line GL on the lower transparent glass substrate SOB l (see FIG. 1C showing a cross section of the thin film transistor section). reference)
As shown in FIG. 1A (a), a Cr film g1 and an ITO film g2 forming the short-circuit wiring GSW having a predetermined pattern, and a Cr film g1 forming the DSW are formed.

PJ is each protrusion of the short circuit wiring GSW and DSW, and GAP is a gap between the protrusions PJ.

Next, the gate insulating film GI,1 of the thin film transistor TPT is
At the same time as forming the type semiconductor layer AS and the n+ type semiconductor layer do, as shown in FIG. Form a layer do.

Next, at the same time as patterning the type 1 semiconductor layer AS and the n+ type semiconductor layer do of the thin film transistor TFT,
As shown in FIG. 1A (c), using the selectively formed resist film PRI as a mask, the l-type semiconductor layer AS and n
“Dry etching the type semiconductor layer do.

Next, as shown in FIG. 1A(d), the same resist film P
Using R as a mask, the insulating film GI is dry etched.

After etching, the insulating film Gl has a slope as shown in the figure.

Next, after removing the resist film PRI, the transparent pixel electrode I
At the same time as forming TO1 (ITOMd3), the first A
As shown in Figure (e), an ITO film d3 is formed.

Next, at the same time as patterning the transparent pixel electrode ITOI, a part of the ITO film d3 is removed using the selectively provided resist film PR2 again as a mask, as shown in FIG. 1A (f).

Next, after removing the resist film PR2, at the same time as the Cr film d1 and the A1 film (or Si-added Al film) d2 of the source/drain electrodes, a patterned Cr film is formed as shown in FIG. 1A (g). d1 and A1 film d2 are formed.

Next, as shown in FIG. 1A (h), a protective film PSVI made of SiN or the like is applied to the entire surface of the lower transparent glass substrate 5UBI.
is formed by plasma CVD method.

Next, at the same time as patterning the protective film PS1 covering the liquid crystal display section, that is, the scanning signal line GL and the video signal line DL, a resist film PR3 selectively provided as shown in FIG. 1A (i) is patterned. As a mask, the protective film PSVI, the n''' type semiconductor layer do, the 1 type semiconductor layer AS, and the insulating film Gl are dry etched at the same time.
Semiconductor layers AS and d connected SW and DSW.

is removed to disconnect the short-circuit wiring GSW and DSW.

Finally, as shown in FIG. 1A (j), the resist film PR
Remove 3.

The effects of this embodiment with the above configuration will be explained. Semiconductor layer A connecting short-circuit wiring GSW and DSW
When S and do are irradiated with light, the resistance value decreases due to photoconduction, and the short-circuit wiring GSW and D
It can be short-circuited with SW. In other words, during the manufacturing process of liquid crystal display devices, plasma C is particularly prone to generating static electricity.
Deposition process of protective film PSVI by VD method, protective film PSV
After depositing I (shown in FIG. 1A (h)), in the process of taking out the lower transparent glass substrate SUB I from the jig of the CVD device, the semiconductor layers AS and do are constantly irradiated with light, and the short-circuit wiring GSW , by shorting between the DSWs,
Between scanning signal line GL and video signal line DL, source electrode SDI
Alternatively, it is possible to prevent the insulation between the drain voltage %SD2 and the gate electrode GT from being damaged by static electricity. Also,
As shown in FIG. 1A (j), after the semiconductor layers AS and do are removed, a gap GAP is formed, so the semiconductor layer AS
If static electricity is generated during the alignment film rubbing process, transport process, etc. where static electricity is easily generated after %do removal, discharge will occur in the gap GAP, preventing electrostatic damage, so there is no need to irradiate it with light. good.

After patterning the protective film PSVI on the surface of the lower transparent glass substrate 5UBI, the lower transparent glass substrate SUBl on the outer periphery of each external terminal GP, DP having the short circuit wiring GSW, DSW and the discharge part ED is patterned on the plane of FIG. 1B. Cut along the cutting line CL shown in the figure. Thereby, it is possible to test electrical characteristics such as the short-circuit state between the scanning signal lines GL, between the video signal lines DL, or between the scanning signal line OL and the video signal line DL, and the characteristics of the thin film transistor TPT.

Further, the short-circuit wiring GSW, DS~' and the discharge portion ED according to the present invention all include the scanning signal line GL, the video signal line DL,
Since it is formed in the same manufacturing process as the external terminals GP and DP, the number of processes does not increase.

Furthermore, since the conductive films constituting the short-circuit wiring GSW and DSW that approach each other across a small gap in the discharge part ED are made of the IT○ film d3, which is difficult to melt, the semiconductor layers AS, d
o, it is not fused when etching the insulating film CI, etc.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in FIG. 1A, it is not necessary to form the insulating film CI in the discharge portion ED.

Furthermore, although this embodiment shows a reverse staggered structure in which gate electrode formation → gate insulating film formation → semiconductor layer formation → source/drain electrode formation, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. be.

[Effects of the Invention] As explained above, according to the present invention, it is possible to prevent electrostatic damage to wiring, etc. during the manufacturing process of a liquid crystal display device, and to perform electrical characteristic inspection for short circuits, etc. of wiring. I can do it.

[Brief explanation of drawings]

1A (a) to (j) are process cross-sectional views showing a method for manufacturing a liquid crystal display device according to the present invention, and FIG. 1B is a plan view of essential parts of a liquid crystal display unit according to the present invention.
Figure 1C is a sectional view taken along cutting line I-1 in Figure 1B. Figure 1D is a cross-sectional view taken along the ■-■ line in Figure 1B. 1E is a schematic plan view of a transparent glass substrate showing the arrangement of short-circuit wiring, and FIG. 2A is a liquid crystal display section of an active matrix color liquid crystal display device according to embodiment (2) of the present invention. FIG. 2B is a sectional view of the portion taken along the line IIB-DB in FIG. 2A and the vicinity of the seal portion. FIG.
FIG. 3 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2A are arranged; FIGS. 7 is a plan view depicting only a predetermined layer of the pixel shown in FIG. FIG. 9 is an equivalent circuit diagram showing the liquid crystal display section of a matrix type color liquid crystal display device.
FIG. 10 is an equivalent circuit diagram of the pixel shown in FIG. A. FIG. 10 is a time chart showing the drive voltage of the scanning signal line using the DC cancellation method. In the figure, SUB...Transparent glass substrate, GL...Scanning signal line, DL...Video signal line, GP, DP...External terminal, GSW, DSW...Short circuit wiring (electrostatic damage prevention wiring) , ED...discharge part, PJ...protrusion, GAP...
・Gap, PSVI...protective film, GI...insulating film,
GT...gate electrical contact, AS...i-type semiconductor layer, SD
...source electrode or drain electrode, LS...light shielding film,
LC...Liquid crystal, TPT...Thin film transistor, IT
O...Transparent electrode, g, d...Conductive film, Cadd...
・Holding capacitance element, Cgs...superposition capacitance, Cpix
...Liquid crystal capacity (numerical subscripts after letters are omitted).

Claims (1)

[Scope of Claims] 1. A plurality of external terminals of scanning signal lines and video signal lines arranged on the outer peripheral surface of the liquid crystal display section of the transparent substrate, and further provided on the outer peripheral surface of the external terminals, A first short-circuit wiring that short-circuits each of the scanning signal lines, a second short-circuit wiring that short-circuits each of the video signal lines, and the first and second short-circuit wiring are close to each other with a small gap in between. In a method for manufacturing a liquid crystal display device, the method includes: a discharge portion; a semiconductor layer provided in the gap portion and connecting the first and second short circuit wiring; and a protective film covering the scanning signal line and the video signal line. After the protective film is deposited on the surface of the transparent substrate, the semiconductor layer is removed in the same process as or after the process of selectively removing the protective film, and the first and second short-circuit wirings are removed. A method for manufacturing a liquid crystal display device, comprising the step of: disconnecting the . 2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the semiconductor layer is formed in the same process as a semiconductor layer used in a thin film transistor provided in the liquid crystal display section. 3. The liquid crystal display device according to claim 1, wherein the conductive films constituting the first and second short-circuit wirings that are close to each other with a small gap in the discharge section are formed of a film that is difficult to be fused. Production method.