JPH03250355A - Inter-processor communication method for multiprocessor system - Google Patents

Abstract

PURPOSE:To attain the inter-processor communication with use of the least hardware resources used for interruption processing by providing (n) pieces of message areas to a shared memory in response to (n) pieces of processors and then having an access to the common message area corresponding to a prescribed processor. CONSTITUTION:A shared memory 10 is provided with the common message areas 10-1 - 10-n which give the information to decide whether the accesses should be enabled or not to the interruption requests given from all processors except its own one in response to the processors P1 - Pn respectively. Each processor writes a prescribed message into a relevant area when the information enabling the accesses to the areas 10-1 - 10-n corresponding to the processors P1 - Pn is represented and then produces an interruption to a relevant processor. In such a constitution, it is just needed to provide the interruption processing hardware consisting of the prescribed component elements proportional to (n). Then the inter-processor communication is attained with use of the least hardware resources despite use of a large number of processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interprocessor communication method in a multiprocessor system for exchanging messages between a plurality of processors.

[Conventional technology]

FIG. 4 is a schematic configuration diagram showing the configuration of a general multiprocessor system. In the figure, processors (including local memory) PI to Pn and a shared memory 41 are
They are connected via a system bus 42, and each processor can perform inter-processor communication by accessing the shared memory 41 and generating an interrupt to any other processor.

As shown in FIG. 5, a conventional multiprocessor system includes processors P1, P2, .
・Fixed areas 41-1 to 41- corresponding to Pn, respectively
n is allocated, and furthermore, in these fixed areas, a fixed area for writing messages is provided corresponding to each processor other than the self (i.e., (n - 1,) processors), in which messages from each processor are written. There are things that are being done. In addition, in FIG. 5, r Inte
rrupt (symbol X-symbol Y) J indicates that an interrupt occurs from processor PX to processor PY.
t(?1)J indicates that an interrupt occurs from processor P2 to processor P1. In the figure, in each fixed area, squares other than the hatched squares, for example, the squares indicated by arrow B, indicate fixed areas for message writing.

In the multiprocessor system described above, when each processor performs inter-processor communication using the shared memory 41, for example, when processor P2 generates an interrupt for processor P1, in the fixed area 411 corresponding to processor P1, Writes a message to the fixed message writing area for own use and interrupts (I)
interrupt(2-'1.)). On the other hand, in the processor P1, an interrupt (Interrupt(
? 1. )), the message write fixed area corresponding to processor P2 is accessed and interrupt processing is executed.

In this case, the address of the shared memory area (fixed area for message writing) is known in advance by both parties communicating.

[Problem to be solved by the invention]

By the way, in the conventional multiprocessor system mentioned above, n
In order for these processors to operate equally, it is necessary to set both the fixed area for writing messages (in the shared memory) and the types of interrupts to (nX (n-1,)), and when n is large, , a large amount of interrupt processing hardware with a complex circuit configuration is required. Since more hardware is required, the number of constituent parts increases, resulting in an increase in cost.

The present invention solves the above-mentioned drawbacks and enables inter-processor communication in a multiprocessor system, which enables processor open communication with a simplified circuit configuration and minimal hardware resources even when there are many processors. The purpose is to provide a method.

[Means to solve the problem]

The present invention provides a multiprocessor system having a plurality of processors and a shared memory that can be commonly accessed by the processors, in which the shared memory is configured to respond to interrupt requests from all processors other than the processor itself. A common message area is provided that provides information on whether access is permitted or not, and each processor, if information indicating permission to access is shown in the message area corresponding to the processor of the communication partner, This is configured to write a message to generate an interrupt to the processor concerned.

[Effect]

According to the inter-processor communication method of the present invention, the shared memory is provided with n common message areas (areas for all other processors to generate interrupts) corresponding to n processors.

When receiving an interrupt request, each processor refers to the message area corresponding to the communication partner's processor, and if information permitting access is indicated, writes its own identification information and message to the area, and If an interrupt is generated by referring to its own message area, the corresponding interrupt processing is executed.

Therefore, if there are n processors, interrupt handling hardware consisting of predetermined components proportional to n will suffice, and even if there are many processors, the minimum hardware Communication between processors becomes possible using hardware resources.

〔Example〕

Embodiments of the inter-processor communication method according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which an inter-processor communication method according to the present invention is applied. In the figure, parts that perform the same functions as the constituent parts in the multiprocessor system shown in FIG. 4 are given the same reference numerals.

In FIG. 1, the shared memory 10 includes a processor P1.
, P2, ... 10 fixed areas for message writing (hereinafter referred to as fixed areas) corresponding to Pn, respectively.
10-2, . = 10-n are allocated. Each of these fixed areas functions as the message area described above, and interrupt information from all processors other than the corresponding self-processor is written therein. For example, [(2~I+)→
1)'' indicates that interrupt information from all processors P2 to Pn other than processor P1 is written. The same thing applies to other fixed areas 1o-2,
10-3,...]0-n. however,
In the fixed area 10-2 and 10-3 of the same figure, for simplicity of expression, I" (1, -n) → 2 J, r (1~n)
Although it is written as -3J, the exact numbers are "(1,3~n 2") and "(1,2,4~n)-3."

In other words, n fixed areas are allocated to the shared memory]0 corresponding to n processors, and the fixed area corresponding to the processor is used for communication to a given processor. Each fixed area (each entry in shared memory)
includes a flag (semaphore flag) indicating whether access to the corresponding processor is permitted, and identification information (ID) of the interrupt source.

On the other hand, interrupts also correspond to n processors (that is, correspond to the processor that receives the interrupt).
The same interrupts are used for all communications to the processor.

Therefore, fixed area and interrupt
) are also set to correspond to the n number of processors.

Note that "rInterrupt((2~n)→1)" in the part surrounded by the dotted line indicated by arrow A in FIG. It shows that. Similarly, r Interrupt((1~n)−2
) J , - r Interrupt for -Pn ((1
~n-1)=n) J also connects other processors (PI, P3 to Pn) to the corresponding processors P2,...Pn, respectively.
n),... Processor (PI~P(n-1,))
This indicates that an interrupt will be generated.

Next, the inter-processor communication processing operation of the multiprocessor system will be explained using FIGS. 2 and 3.

Here, the processor on the side that issues an interrupt is assumed to be processor P1, and the processor on the side that receives the interrupt is assumed to be processor P2.

First, the interrupt processing of the processor that issues the interrupt will be explained with reference to FIG.

Processor P1 accepts an interrupt processing request from a requestor for interprocessor communication (step 20), and stores a fixed area (this area) in shared memory 10 corresponding to the communication partner processor (processor P2 in this example) to which an interrupt is to be issued. In the example, the semaphore flag in the fixed area 1o-2 (see FIG. 1) is accessed by a test and set instruction to secure the right to interrupt the communication partner.

That is, the processor P1 determines whether the semaphore flag in the fixed area 1.0-2 is on or not (step 2).
), if it is off, it is recognized that interrupts are enabled (recognizes that the right to issue an interrupt has been secured), and the fixed area corresponding to the processor of the communication partner, that is, the fixed area 10-
2, writes its own processor identification information (ID) and a necessary message (step 22), generates an interrupt to the communication partner processor P2 (step 23), and then returns in preparation for the next interrupt processing request.

Note that in step 21 above, if the communication partner is busy (
Busy) (if the semaphore flag is on), sets an error code (Busy) (step 24), notifies the requestor of the inter-processor communication to that effect,
Encourage retry.

Next, the processing of the processor on the side where the interrupt is applied will be explained using FIG.

When an interrupt from another processor occurs (in this example, an interrupt from processor P1 occurs), processor P2, which is the processor receiving the interrupt, registers a register (not shown) in its own processor (step 30). Save the value (for example, the current state of the self) (
Step 31) After that, read the processor ID and message written in the fixed area 1.0-2 (see Figure 1) corresponding to the own processor, and based on that information, The content is identified and passed to the corresponding processing task (step 32).

Next, the processor P2 clears the semaphore flag in the fixed area 10-2 for its own processor (step 33), and restores the register value (step 34).
, further ends the interrupt processing (step 35), and returns in preparation for the next interrupt request.

As explained above, according to this embodiment, when the number of processors is n, the hardware components are incremented in proportion to n, whereas in the past, the increment was proportional to (nX(n-1)). Incremental test.

In other words, even in the case of a multiprocessor system in which n processors communicate with any other party on an equal footing, the fixed area for message writing and the type of interrupt are each (nX(n- 1)) There is no need to use n pieces for both the fixed area for message writing and the types of interrupts, so the circuit configuration of the hardware for interrupt processing can be simplified, and /%-
The number of components (components) of Fware can be minimized.

Therefore, it is possible to provide an inexpensive multiprocessor system and to perform inter-processor communication with a minimum of hardware resources.

〔Effect of the invention〕

As explained above, according to the present invention, the shared memory includes
n message areas corresponding to n processors are provided, and all other processors access a common message area corresponding to the predetermined processor for communication to a predetermined processor. It is only necessary to set hardware for interrupt processing consisting of proportional components, and inter-processor communication can be performed with a minimum of hardware resources.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system to which the interprocessor communication method according to the present invention is applied, FIGS. 2 and 3 are flowcharts showing interrupt processing operations, and FIG. 4 is a general multiprocessor system. FIG. 5 is a schematic block diagram showing the structure of a processor system. FIG. 5 is a block diagram showing the structure of a conventional multiprocessor system. P], P2, Pn... Processor, 10. Shared memory,
10-1.10-2.10-3.10-n... fixed area for writing messages, 42... system bus. Figure 4 339-

Claims (1)

[Scope of Claims] In a multiprocessor system having a plurality of processors and a shared memory that can be commonly accessed by those processors, the shared memory stores interrupt requests from all processors other than itself corresponding to each processor. A common message area is provided that provides information on whether or not to permit access to the processor, and if each processor has information indicating that access is permitted in the message area corresponding to the processor of the communication partner, then 1. A method for communicating between processors in a multiprocessor system, characterized in that a predetermined message is written to a processor to generate an interrupt in the processor.