JPH0325058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an additional device for limiting the usable period of a radio selective calling receiver with display.

[Description of prior art]

In recent years, wireless selective calling receivers have become more multi-functional.
In addition to the conventional alert tone service that notifies users of a call using a selective call signal, there is a transition to a service that adds message information. In this service, when a selective call signal and a message information signal are received, a notification sound notifying the reception is sent out, and at the same time, the display device is driven to display the contents of the message. Furthermore, as the content displayed by this call display service increases, the number of users is increasing significantly.

By the way, in conventional call-only services, the base station deletes the subscriber number from the subscriber registration for subscribers who do not pay the service fee. However, in the case of a call display service, there are multiple users of message information, so even if some of these users do not pay the service fee,
Since services for other paying subscribers must continue, message information cannot be stopped on the base side, which has the drawback of causing operational problems.

[Purpose of the invention]

The present invention is intended to eliminate the above-mentioned drawbacks, and is aimed at preventing certain subscribers who wish to receive illegal services from among subscribers who use radio selective calling receivers to which a service is provided in which message information is added to selective calling signals. To provide a radio selective calling receiver with a display that allows services of other subscribers to be normally performed even if the services of one subscriber are stopped.

[Key points of the invention]

According to the present invention, a timer is set in a wireless selective calling receiver with a display that prohibits the reading operation of the memory circuit when a predetermined time elapses, the reset circuit of this timer is sealed, and the reset circuit is operated. It is possible to charge the user of the receiver until the predetermined time has elapsed.
A radio section that receives a radio signal, a memory circuit that stores a selective call code, a coincidence detection circuit that matches an output signal of the radio section with a readout output of the memory circuit, and a coincidence detection circuit that outputs a coincidence output. A wireless selective calling receiver with a display, comprising means for generating a sound when a matching output is obtained, and a display circuit for displaying an output signal successively transmitted from the wireless section after the matching output is obtained, The present invention is characterized in that it includes a timer means for prohibiting reading of the memory circuit when a predetermined time has elapsed, and a reset circuit of the timer means is sealed so that it cannot be operated by a user.

[Explanation based on examples]

Hereinafter, an embodiment of the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing the overall configuration of an apparatus according to the present invention, and FIGS. 2, 3, and 4 are block diagrams showing the configuration of parts of the apparatus according to the present invention.

First, the configuration and connections of this embodiment device will be explained based on FIGS. 1 to 4. As shown in FIG. 1, this embodiment device includes an antenna 1, a radio section 2, a waveform shaping circuit 3, a decoder 4, and a
ROM 5, message processing section 6, and amplification section 7
, speaker 8, LCD 9, and crystal oscillator 10
The decoder 4 includes a signal detection circuit 21 and a switch 11, as shown in FIG.
, a matching circuit 22, a P-ROM reading/decoding circuit 23, and a sound generation circuit 24. The P-ROM 5 is an AND gate having a timer 30 and an AND gate 34, as shown in FIG. A count timer circuit 31 consisting of a gate circuit 32
The P-ROM 5 is composed of a count timer 31 composed of a timer 30 and an AND gate 32, and a memory 33 as shown in FIG. In addition, the timer 30 of the P-ROM 5 connects not gates 47 and 48 and a resistor 42, as shown in FIG.
and 43 and a capacitor 44, not gates 46 and 49, and a flip-flop circuit 45 ₁
~45 _° and a switching circuit 50.

As shown in FIG. 1, the output of the antenna 1 input from an external information source (not shown) is
The output of the wireless section 2 is connected to the input of the waveform shaping circuit 3, the output of the waveform shaping circuit 3 is connected to the first input of the decoder 4, and the first output of the decoder 4 is , the output of the amplifier 7 is connected to the input of the speaker 8, and the second output of the decoder 4 is connected to the input of the message processing unit 6, and the output of the amplifier 7 is connected to the input of the message processing unit 6. The output of the message processor 6 is connected to the input of the LCD 9, the second output of the message processing unit 6 is connected to the second input of the decoder 4, and the third input of the decoder 4 is connected to the output of the crystal oscillator 11. , the fourth output of decoder 4 is connected to the input of P-ROM5, the fourth input of decoder 4 is connected to the output of P-ROM5, and the fifth input of decoder 4 is connected to switch 1
0, and the other terminal of the switch 10 is connected to a non-conducting potential.

Here, in the decoder 4, as shown in FIG. 2, the first input of this circuit is the signal detection circuit 21.
and the first input of the matching circuit 22, and the output of the signal detection circuit 21 is connected to the first input of the P-ROM reading/decoding circuit 23;
- the first output of the ROM reading/decoding circuit 23 is the fourth output of the decoder 4;
The second input of the readout/decoding circuit 23 is the fourth input of the decoder 4 and is used for P-ROM readout/decoding.
The output of the decoding circuit 23 is connected to the second input of the matching circuit 22, the output of the matching circuit 22 is the second output of the decoder 4, and the second input of the decoder 4 is connected to the sound generating circuit 24. The output of the sound generating circuit 24 is the first output of the decoder 4.

Moreover, as shown in FIG. 3, the P-ROM5 is
The output of the P-ROM reading/decoding circuit 23 is connected to one input of an AND gate 34 constituting an AND gate circuit, the other input of this AND gate 34 is connected to the first output of a timer 30, The output of gate 34 is connected to the input of memory 33. The input of the timer 30 is connected to the terminal 35, and the output of the memory 33 is connected to the P-ROM.
It is connected to the input of the reading/decoding circuit 23.

Furthermore, the timer 30, as shown in FIG.
In the astable multivibrator circuit 40 of this timer 30, one end of the resistor 42 is connected to the not gate 4.
The output of not gate 47 and one end of resistor 43 are connected to the input of not gate 48, the output of not gate 48 is connected to one end of capacitor 44, and the output of not gate 47 is connected to one end of resistor 43.
The other end of the resistor 43 and the other end of the capacitor 44 are connected, and in the binary counter circuit 30 of the timer 30, the output of the not gate 48 of the astable multivibrator circuit 40 is connected. connected to the input of the not gate 49 and the input of the flip-flop 45 ₁ of this circuit;
The Q output of the flip-flop 45 ₁ is connected to the φ input of the flip-flop 45 ₂ in the next stage and the switched terminal Q ₁ of the switching circuit 50, and the output of the flip-flop 45 ₁ is connected to the φ input of the flip-flop 45 ₂ in the next stage. . Similar connections are made in sequence to complete the connections between flip-flop 45o _-1 , flip-flop 45n, and switching circuit 50. The R input of flip-flops 45 ₁ to 45 _o is connected to this P
- Connected to the terminal 35 of the ROM circuit 5.

Next, the operation of this embodiment device will be explained based on the drawings. In this explanation, the drawings of FIGS. 5 to 7 are used in addition to FIGS. 1 to 4.

Here, FIG. 5 is a time chart showing the operation of this embodiment device, and FIG. , symbol N indicates a selective call signal, and symbol I indicates a message signal. In addition, Figure A shows an enlarged view of this received signal, Figure b shows the power supply state of this embodiment device, and Figures c to K show each part of Figure 2. It shows the waveforms of signals c to K.

Moreover, FIG. 6 is a schematic diagram showing the memory contents stored in the memory element of the P-ROM 5, and FIG. The output state of the stored contents from is shown.

First, to explain the outline of the operation of this embodiment device based on FIG. 1, a radio signal as shown in FIG. It is converted into a digital signal and output to the decoder 4. In decoder 4,
P-ROM in which the frame synchronization signal F is detected and its own calling number is written in advance
The contents of the circuit 5 and the digital signal from the waveform shaping circuit 3 are compared, and when a match is confirmed, a detection signal is sent to the message processing section 6, and preparations are made for processing subsequent message data. Next, when the message processing section 6 detects the end of the message signal, this detection signal is output to the decoder 4, and the speaker 8 is driven via the amplification section 7. Furthermore, the message processing section 6
The LCD 9 is driven and message information is displayed on the LCD 9. Further, a clock signal for the decoder 4 is supplied from a crystal oscillator 10. Further, change information and status signals generated by the operation of the reset switch 11 are sent to the message processing unit 6 via the decoder 4, and the sound is stopped and the LCD display is stopped and activated.

Next, the operation of the P-ROM 5 according to the present invention will be explained in detail based on FIGS. 2 to 7.

When the frame synchronization signal F, which is the output signal from the waveform shaping 3, is supplied to the signal detection circuit 102 of the decoder 4, the pulse waveform shown in FIG.
It is output to the ROM reading/decoding circuit 23. Subsequently, the P-ROM read/decode circuit 23 sends read pulses shown in FIGS. 5D to 5K. Here, the read pulse D is P-ROM5
The read pulse E is sent to terminal #12 of P-ROM5.
The read pulse F is sent to terminal #13 of P-ROM5.
The read pulse G is sent to terminal #14 of P-ROM5.
The read pulse H is sent to terminal #15 of P-ROM5.
The read pulse I is sent to terminal #16 of P-ROM5.
The read pulse J is sent to terminal #17 of P-ROM5.
The read pulse K is sent to terminal #18 of P-ROM5.
is periodically sent to terminal #19. Here, P-
ROM reading/decoding circuit 23 to P-ROM5
When read pulse D is input to terminal #12 of
From the output terminals #3 to #6 of the P-ROM5, as shown in Fig. 7, "H" is output from all the output terminals.
A level signal is output. That is, data A1 stored in P-ROM5 is sent from output terminal #3, data _A9 stored in P-ROM5 is sent from output terminal #4, and data A1 stored in P-ROM5 is sent from output terminal #5. Data A17 stored in ROM5
However, data A25 stored in the P-ROM 5 is also output from the output terminal #6. Similarly, when read pulses E to K are input to input terminals #12 to #19 of the P-ROM 5, the to
A signal waveform with a level as shown in is output.
That is, data A ₁ to _{A 8} stored in the P-ROM 5 are sequentially output from the output terminal #3.

The data output from the output terminals #3 to #6 of the P-ROM 5 is transferred to the P-ROM as shown in FIG.
It is sent to the reading/decoding circuit 23. That is, the output data is read out bit by bit from the P-ROM 5 by this P-ROM reading/decoding circuit 23, and this output data is sent to the matching circuit 22.
Then, each bit is compared with the received information from the waveform shaping circuit 3, and the number corresponding to the number of erroneous bits is counted. The device of this embodiment allows up to 2 error bits, so if the count is less than 2, a detection signal is sent to the message processing unit 6, indicating that the device itself has been called.

Here, the operation of the timer 30 built in the P-ROM 5 according to the present invention will be explained based on FIG. 4. The timer 30 includes an unstable multivibrator circuit 40 and a counter circuit 41. In this unstable multivibrator circuit 40, there is a phase difference of 180 degrees between the input and output of the inverters 47 and 48 of this circuit, and the pulse period T related to the CR time constant is Assuming that the capacitance value of the capacitor 44 is C, and the resistance value Rs of the resistor 42 is Rs≧10R, there is a relationship of T=about 2.2RC.

Counter circuit 41 includes inverters 46 and 4
9 and flip-flops 45 ₁ to 45 _o , and the period until timer out is set by connecting the terminals Q ₁ to Q _o .

Therefore, the setting of the operation period of the timer 30 is as follows:
This is executed by setting the number of flip-flop stages and the period T of the unstable multivibrator.

Now, the timer 30 of the P-ROM 5 in FIG. 3 outputs a signal _C1 of logic "1" when the timer is operating, and logic "0" when the timer is out.
The read pulses A ₁ to _{A 8} from the ROM reading/decoding circuit 23 and the signal C ₁ from the timer 30 are operated on by the AND gate circuit 32 , and the output of the AND gate circuit 32 is sent to the memory 33 . here,
During timer operation, the signal _C1 from timer 30 is
Because of the logic “1” level, the signals A ₁ to _{A 8} are
The signals are the same as the signals X ₁ to X ₈ , but since the signal C ₁ is at the logic "0" level at the time of timeout, the signals X ₁ to X ₈ are at the 0 level, and the P-ROM
Even if a read pulse is sent from the read/decode circuit 23 to the P-ROM 5, the selective call number previously written in the memory 33 is not read out.
Therefore, when the timer 30 of the P-ROM 5 times out, as explained above, this embodiment becomes unable to receive data, and in order to restart, it is necessary to reset the timer 30.

The signal line of the timer 30 shown in FIG. 7 is this reset signal line, and its terminal is arranged on the surface of the P-ROM 5 package. This terminal is located in a location where it cannot be easily discovered by the general user, such as under a nameplate made of insulating material, and
When restarting or lending to a user, the timer 30 is initialized by the service provider.

〔Effect of the invention〕

As described above, the present invention enables charging to be updated each time the usage period is completed by setting the usage period of the wireless selective calling receiver with display with high precision, thereby preventing subscribers who are receiving services illegally. Since it is possible to selectively suspend the service and continue the service to other subscribers who are jointly receiving the service, this has the effect of streamlining the operation of the billing system.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment apparatus. FIG. 2 is a block diagram showing the structure of the decoder 4 shown in FIG. 1. Figure 3 shows P- shown in Figure 1.
FIG. 3 is a block configuration diagram showing the configuration of the ROM 5; FIG. 4 is a block diagram showing the configuration of timer 30 shown in FIG. 3. FIG. 5 is a time chart showing the operation of the embodiment device. FIG. 6 is a schematic diagram showing the storage contents of the P-ROM 5. FIG. 7 is a waveform diagram showing the output waveform of the P-ROM 5. DESCRIPTION OF SYMBOLS 1...Antenna, 2...Radio unit, 3...Waveform shaping circuit, 4...Decoder, 5...P-ROM, 6...Message processing unit, 7...Amplifier, 8...Speaker, 9...
LCD, 10...Crystal oscillator, 11...Switch, 2
1... Signal detection circuit, 22... Matching circuit, 23... P-
ROM reading/decoding circuit, 24...Sound generation circuit, 30...Timer, 31...Count timer circuit,
32...AND gate circuit, 33...memory, 34...
AND gate, 35...terminal, 40...unstable multivibrator circuit, 41...binary counter circuit, 4
2, 43...Resistor, 44...Capacitor, 45 ₁ to 4
5 _o ...Flip-flop, 46-49... Not gate, 5... Switching circuit.

Claims (1)

[Scope of Claims] 1. A radio unit that receives a radio signal; a memory circuit in which a selective call code is stored; a coincidence detection circuit that matches an output signal of the radio unit with a readout output of the memory circuit; A display device comprising means for generating a sound when a coincidence output is obtained in the coincidence detection circuit, and a display circuit that displays an output signal that is subsequently sent from the wireless section after the coincidence output is obtained. A display characterized in that a radio selective calling receiver is provided with a timer means for prohibiting reading of the memory circuit when a predetermined time has elapsed, and a reset circuit of the timer means is sealed so that it cannot be operated by a user. Wireless selective calling receiver.