JPH03250617A - Manufacture of bonded wafer - Google Patents
Manufacture of bonded waferInfo
- Publication number
- JPH03250617A JPH03250617A JP4577890A JP4577890A JPH03250617A JP H03250617 A JPH03250617 A JP H03250617A JP 4577890 A JP4577890 A JP 4577890A JP 4577890 A JP4577890 A JP 4577890A JP H03250617 A JPH03250617 A JP H03250617A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- wafers
- oxide film
- bonded
- bond
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 235000012431 wafers Nutrition 0.000 claims abstract description 136
- 239000010408 film Substances 0.000 claims abstract description 57
- 239000010409 thin film Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000009826 distribution Methods 0.000 abstract description 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000008188 pellet Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009864 tensile test Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、2枚のウェーハを接合一体止して成る接合ウ
ェーハの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a bonded wafer by bonding two wafers together.
(従来の技術)
従来、誘電体基板上に単結晶半導体薄膜を形成する方法
としては、単結晶サファイア基板上に単結晶シリコン(
Si)膜等をエピタキシャル成長させる技術か良く知ら
れているか、この技術においては、基板誘電体と気相成
長されるシリコン多結晶との間に格子定数の不一致かあ
るため、シリコン気相成長層に多数の結晶欠陥か発生し
、このために該技術は実用性に乏しい。(Prior Art) Conventionally, as a method for forming a single crystal semiconductor thin film on a dielectric substrate, single crystal silicon (
This is a well-known technique for epitaxially growing Si) films, etc., but in this technique, there is a mismatch in lattice constant between the substrate dielectric and the silicon polycrystalline grown in the vapor phase. A large number of crystal defects occur, which makes the technique impractical.
又、シリコン基板表面上に熱酸化膜を形成し、この熱酸
化膜上に多結晶状若しくはアモルファス状のシリコン膜
を被着し、これに電子線或いはレーザー光線等のエネル
ギービームを線状に、且つ一方向に照射して該シリコン
膜を線状に融解冷却及び側止することによって、全体を
単結晶の薄膜とする技術も良く知られている。Also, a thermal oxide film is formed on the surface of a silicon substrate, a polycrystalline or amorphous silicon film is deposited on the thermal oxide film, and an energy beam such as an electron beam or a laser beam is linearly applied to this film. It is also well known that the silicon film is irradiated in one direction to melt and cool the silicon film in a linear manner, and to form a single crystal thin film as a whole.
ところで、熱酸化膜上のシリコン多結晶膜をレーザー光
線等て多結晶膜化する技術は、例えば特公昭62−34
716号公報に開示されている。この技術においては、
単結晶シリコン基板の端部にこれと一体に連続する単結
晶突部を設け、これを核として多結晶膜の単結晶化を試
みているか、溶融シリコンの酸化膜との相互作用によっ
て部分的には単結晶化は可能であるか、実用に耐え得る
シリコン単結晶膜は得難いのが実情である。By the way, the technique of converting a silicon polycrystalline film on a thermal oxide film into a polycrystalline film using a laser beam, etc.
It is disclosed in Japanese Patent No. 716. In this technology,
A continuous single crystal protrusion is provided at the edge of the single crystal silicon substrate, and the polycrystalline film is attempted to be made into a single crystal by using this as a core, or the polycrystalline film is partially crystallized by interaction with the oxide film of molten silicon. However, the reality is that it is difficult to obtain a silicon single crystal film that can withstand practical use.
そこて、近年、SOI (Si on 1nsulat
ion)構造のウェーハか特に注目されるに至った。こ
の接合ウェーハは、2枚の半導体ウェーハの少なくとも
一方を酸化処理してそのウェーハの少なくとも一方の表
面に酸化膜を形成し、これら2枚の半導体ウェーハを前
記酸化膜か中間層になるようにして重ね合わせた後、所
定温度に加熱して両者を接着し、その上層のウェーハ(
以下、ボンドウェーハと称す)を研磨加工してこれを薄
膜化することによって得られる。Therefore, in recent years, SOI (Si on 1nsulat
ion) structure has attracted particular attention. This bonded wafer is produced by oxidizing at least one of two semiconductor wafers to form an oxide film on the surface of at least one of the wafers, and forming an intermediate layer between the two semiconductor wafers using the oxide film. After stacking them, they are heated to a predetermined temperature to bond them together, and the upper layer wafer (
It is obtained by polishing a bond wafer (hereinafter referred to as a bond wafer) to make it into a thin film.
(発明か解決しようとする課題)
ところて、接合ウェーハにおいては、両ウェーハの結合
強度が全接着面に亘って高いことか必要であり、結合強
度か不十分であると接合界面にボイドと称される未結合
領域か生じ、製品の歩留りか悪くなるという問題か生ず
る。尚、ボイドの検出方法としては、赤外線透過法、超
音波損傷法、X線ラング法等か知られている。(Problem to be solved by the invention) However, in bonded wafers, it is necessary that the bonding strength between both wafers be high over the entire bonding surface, and if the bonding strength is insufficient, voids will occur at the bonding interface. This results in unbonded areas, resulting in a problem of poor product yield. Incidentally, known methods for detecting voids include infrared transmission method, ultrasonic damage method, and X-ray Lang method.
又、接合ウェーハの製造工程においては、ウェーハ表面
に被着された酸化膜を除去するために例えばフッ化水素
液を用いたエツチングか実施されるか、接合界面のエツ
チング液(フッ化水素液)に対する耐浸食性か高くなけ
れば、デハイス工程においてボンドウェーハ上に形成さ
れるパターンに剥れか発生する等の不具合か生しる。In addition, in the manufacturing process of bonded wafers, etching is performed using, for example, a hydrogen fluoride solution to remove the oxide film deposited on the wafer surface, or etching is performed using an etching solution (hydrogen fluoride solution) at the bonding interface. If the corrosion resistance is not high, problems such as peeling or peeling may occur in the pattern formed on the bond wafer in the dehyzing process.
本発明は上記問題に鑑みてなされたもので、その目的と
する処は、結合強度及び接合界面のエツチング液に対す
る耐浸食性か高い接合ウェーハを得ることかてきる接合
ウェーハの製造方法を提供することにある。The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a bonded wafer that can obtain a bonded wafer with high bonding strength and corrosion resistance against etching liquid at the bonded interface. There is a particular thing.
帽1を解決するための手段)
上記目的を達成すべく本発明は、2枚の第1第2鏡面ウ
ェーハのうちの第2鏡面ウェーハの少なくとも片面鏡面
側に酸化膜を形成し、該酸化膜が中間層になるようにし
て第2鏡面ウェーハの該酸化膜を形成した鏡面を第1ウ
ェーハの少なくとも一方の鏡面に重ね合わせた後、これ
ら第1、第2ウェーハを所定温度に加熱して両者を接着
した後、第2鏡面ウェーハの非接合表面を研磨してこれ
を薄膜化することによって接合ウェーハを得ることを特
徴とする。Means for Solving Problem 1) In order to achieve the above object, the present invention forms an oxide film on at least one mirror surface side of a second mirror surface wafer of two first and second mirror surface wafers, and The mirror surface of the second mirror wafer on which the oxide film is formed is superimposed on at least one mirror surface of the first wafer so that the oxide film forms an intermediate layer, and then the first and second wafers are heated to a predetermined temperature to separate them. After bonding, a bonded wafer is obtained by polishing the non-bonded surface of the second mirror-finished wafer to make it a thin film.
(作用)
第1.第2鏡面ウェーハ(以下、単にウェーハと称す)
をこれらの間に酸化膜を介して接着するパターンとして
は、第1ウェーハ(接合ウェーハにおいて、主としてそ
の機械的強度を与える保護用ウェーハてあって、以下、
ベースウェーハと称す)のみに酸化膜を形成し、この酸
化膜を介してベースウェーハに第2ウェーハ(薄層化さ
れ、接合ウェーハにおいて、デバイスか形成されるウェ
ーハてあって、以下、ボンドウェーハと称す)を#着す
るパターン、逆にボンドウェーハのみに酸化膜を形成し
、この酸化膜を介して両ウェーハを接着するパターン、
両ウェーハに各々酸化膜を形成し1、これらの酸化膜を
介して両ウェーハを接着するパターンか考えられる。(Effect) 1st. Second mirror wafer (hereinafter simply referred to as wafer)
The pattern for bonding these through an oxide film is the first wafer (in the bonded wafer, a protective wafer that mainly provides mechanical strength;
An oxide film is formed only on the base wafer (referred to as the base wafer), and the second wafer (the wafer that is thinned and on which devices are formed in the bonded wafer) is connected to the base wafer via this oxide film. A pattern in which an oxide film is formed only on the bond wafer, and a pattern in which both wafers are bonded via this oxide film,
A conceivable pattern is to form oxide films on both wafers, respectively, and then bond both wafers together via these oxide films.
本発明者等は、上記パターンの違いか接合ウェーハに8
ける丙ウェーハの結合機構、延いては両ウェーハの結合
強度及び接合界面のエツチング液に対する耐浸食性に影
響を及ぼすものとの見地に立って種々実験した結果、本
発明方法のようにボンドウェーハのみに酸化膜を形成す
れば、薄層化されたボンドウェーハにおいて高い結合強
度及び耐浸食性か得られることを見い出した。The present inventors discovered that the difference in the pattern described above was due to the difference in the pattern.
As a result of various experiments from the viewpoint of the bonding mechanism of the second wafer, which affects the bonding strength of both wafers and the erosion resistance against etching liquid at the bonding interface, we have found that the method of the present invention is effective only for bonded wafers. It has been found that high bond strength and corrosion resistance can be obtained in thinned bond wafers by forming an oxide film on the bond wafer.
(実施例)
以下に本発明の一実施例を添付図面に基づいて説明する
。(Example) An example of the present invention will be described below based on the accompanying drawings.
第1図(a)〜(e)は本発明に係る製造方法をその工
程順に示す説明図であり、本発明方法に3いては、第1
図(a)に示すように素子形成面となるべき単結晶のS
iボンドウェーハlを酸化処理してその片面(下面)に
厚さ約500n+*のSin、酸化膜3を形成し、この
ボンドウェーハlの他に、ベース材となるべき同じく単
結晶のSiベースウェーハを用意する。FIGS. 1(a) to 1(e) are explanatory diagrams showing the manufacturing method according to the present invention in the order of the steps, and in the method of the present invention, the first
As shown in Figure (a), the S of the single crystal that should become the element formation surface
An i-bond wafer l is oxidized to form a Si oxide film 3 with a thickness of about 500n+* on one side (lower side), and in addition to this bond wafer l, a single-crystal Si-based wafer is also used as a base material. Prepare.
次に、第1図(b)に示すように、ベースウェーハ2の
上にボンドウェーハlを重ね合わせて一体化し、これら
一体止されたウェーハ1,2をN2雰囲気中又は酸化性
雰囲気中て約1100°Cの温度て約120分間たけ熱
酸化処理することによって、第1図(c)に示すように
両ウェーハ1,2の全表面に厚さ約500nmの5if
t酸化膜4を形成する。Next, as shown in FIG. 1(b), the bond wafer 1 is superimposed on the base wafer 2 to integrate them, and the bonded wafers 1 and 2 are placed in an N2 atmosphere or an oxidizing atmosphere. By thermal oxidation treatment at a temperature of 1100°C for about 120 minutes, a 5if film with a thickness of about 500 nm is formed on the entire surface of both wafers 1 and 2, as shown in FIG. 1(c).
A t-oxide film 4 is formed.
次に、上記接合一体止されたウェーハ1,2は冷却され
て第1図(d)に示すようにその上層のボンドウェーハ
lの表面か所定の研磨代(例えば、3gm)を残して所
定の厚さt□ (例えば、6μm)になるまてプレ研磨
(1次研磨)されるか、前述のようにSi単結晶から成
るウェーハ1.2の熱収縮率(熱膨張率)の方かSiO
□酸化M3,4のそれよりも大きいため、ウェーハ1.
2を冷却した時点てこれらウェーハ1,2内には残留応
力か蓄積される。Next, the bonded wafers 1 and 2 are cooled, and as shown in FIG. Either pre-polishing (primary polishing) is performed until the thickness t□ (for example, 6 μm), or as mentioned above, the thermal contraction coefficient (thermal expansion coefficient) of the wafer 1.2 made of Si single crystal or SiO
□Because it is larger than that of oxidized M3,4, wafer 1.
After the wafers 2 are cooled, residual stress is accumulated within the wafers 1 and 2.
然るに、本実施例ては、上記プレ研磨か終了した時点で
ベースウェーハ2の上下面は略凹−厚さ(約500n■
)の酸化1i13,4によって被われるため、該ベース
ウェーハ2の上下面における残留応力分布か略等しくな
り、上下面の熱収縮量か路間−となって邑該ヘースウェ
ーハ2の撓み変形か防かれる。However, in this embodiment, the upper and lower surfaces of the base wafer 2 have a substantially concave thickness (approximately 500 nm
), the residual stress distributions on the upper and lower surfaces of the base wafer 2 are approximately equal, and the amount of thermal contraction on the upper and lower surfaces becomes a gap, thereby preventing bending deformation of the base wafer 2. .
ところて、前述のようにプレ研磨された厚さtlのボン
ドウェーハl(第1図(d)参照)は、2次研磨によっ
て厚さt2 (例えば、3uLm)まて研磨されて薄膜
化され、これによって第1図(e)に示すような接合ウ
ェーハ5か得られる。By the way, the bond wafer l (see FIG. 1(d)), which has been pre-polished as described above and has a thickness tl, is polished to a thickness t2 (for example, 3uLm) by secondary polishing to become a thin film. As a result, a bonded wafer 5 as shown in FIG. 1(e) is obtained.
而して1以上のようにして得られる接合ウェーハ5の結
合強度を調べるために、接着時の温度900℃、 1.
000℃、1100℃、1200℃て各2時間加熱して
得られる接合ウェーハを複数用意し、各接合ウェーハの
引っ張り強度を引っ張り試験機で測定した結果を第2図
(c)に示す。又、同し加熱条件下て、ウェーハ間に酸
化膜を介在させないで直接接合して得られる接合ウェー
ハ、両ウェーハに共に厚さ5001■の酸化膜を形成し
、この酸化膜を介して両ウェーハを接合して得られる接
合ウェーハに対して行なわれた引っ張り試験によって得
られた引っ張り強度の測定結果を第2図(a)、(b)
にそれぞれ示す。尚、第2図中、・印は両ウェーハの接
合界面か剥離したときの値を示し、Oはウェーハを引っ
張り試験機に接合した接着剤が剥離したときの値を示す
。又、同図中、酸化膜010nm 、 5001500
nm 、 50010n■とは、両ウェーハ間に酸化膜
か存在しない場合1両ウェーハに共に厚さ5000■の
酸化膜を形成している場合、ボンドウェーハのみに厚さ
500n+sの酸化膜を形成している場合(本発明の場
合)をそれぞれ示す。In order to examine the bonding strength of the bonded wafer 5 obtained as described above, the bonding temperature was 900° C.; 1.
A plurality of bonded wafers obtained by heating at 000° C., 1100° C., and 1200° C. for 2 hours each were prepared, and the tensile strength of each bonded wafer was measured using a tensile tester. The results are shown in FIG. 2(c). In addition, under the same heating conditions, a bonded wafer obtained by directly bonding the wafers without intervening an oxide film, and an oxide film with a thickness of 5001 mm formed on both wafers, and bonding between both wafers through this oxide film. Figures 2 (a) and (b) show the results of measuring the tensile strength obtained by a tensile test conducted on the bonded wafers obtained by bonding the wafers.
are shown respectively. In FIG. 2, the symbol * indicates the value when the bonding interface between both wafers has peeled off, and O indicates the value when the adhesive bonded to the wafer on the tensile testing machine has peeled off. Also, in the same figure, the oxide film is 010 nm, 5001500
nm, 50010n■ means that when there is no oxide film between both wafers, when an oxide film with a thickness of 5000mm is formed on both wafers, and when an oxide film with a thickness of 500n+s is formed only on the bond wafer. (In the case of the present invention)
第2図(c)に示す結果より明らかなように、本発明方
法のようにボンドウェーハのみに酸化膜を形成すれば、
温度1100°C以上に加熱した場合には、800Kg
/cm2以上の高い結合強度か得られる。As is clear from the results shown in FIG. 2(c), if an oxide film is formed only on the bond wafer as in the method of the present invention,
When heated to a temperature of 1100°C or higher, 800kg
A high bonding strength of /cm2 or more can be obtained.
そして、第2図に示される結果から、各品種のウェーハ
の結合強度に対する判定を各加熱温度毎下すと、第3図
に示すような結果となる。尚、第3図中、○印は良、Δ
印は可、x印は不可を示す。From the results shown in FIG. 2, when the bonding strength of each type of wafer is judged for each heating temperature, the results shown in FIG. 3 are obtained. In addition, in Figure 3, ○ marks are good and Δ
The mark indicates acceptable, and the x mark indicates disapproval.
而して、以上の結果を総合すると、本発明方法のように
ボンドウェーハのみに酸化膜を形成し、接着時に110
0℃以上の温度て加熱すれば、高い結合強度(800K
g/c■2以上)か得られることか判る。Taking all the above results together, it can be concluded that when an oxide film is formed only on the bond wafer as in the method of the present invention, the oxide film is
High bonding strength (800K
g/c■2 or more).
一方、上記各品種のウェーハに対して接合界面のエツチ
ング液(フッ化水素液)に対する耐浸食性試験を実施し
た結果、本発明方法によって得られた接合ウェーハには
高い耐浸食性か確保されることか判った。尚、他の接合
ウェーハ(両ウェーハ間に酸化膜か存在しないもの及び
両ウェーハに共に酸化膜を形成したもの)においては、
満足すべき耐浸食性か得られなかった。On the other hand, as a result of conducting erosion resistance tests against etching liquid (hydrogen fluoride solution) at the bonding interface on each of the above types of wafers, it was found that the bonded wafers obtained by the method of the present invention have high corrosion resistance. I realized that. In addition, for other bonded wafers (those with no oxide film between both wafers and those with oxide films formed on both wafers),
Satisfactory erosion resistance could not be obtained.
ところで、本発明方法によって得られる接合ウェーハ5
にあっては、その厚さの大部分を占めるベースウェーハ
2の撓み変形か前述のように防かれるため、該接合ウェ
ーハ5は反りの無い平坦度の高いものとなり、次工程以
降における当該接合ウェーハ5の真空吸着か確実に行な
われる等の効果か得られる。By the way, the bonded wafer 5 obtained by the method of the present invention
In this case, since the bending deformation of the base wafer 2, which accounts for most of the thickness, is prevented as described above, the bonded wafer 5 is free from warp and has a high degree of flatness, and the bonded wafer 5 is Effects such as vacuum suction in step 5 can be achieved reliably.
接合界面のエツチングに対する耐久性を調べるために、
前述の接合ウェーハ(第2図(b)及び(c)に示すも
の)を薄刃、例えば80gmの外周式ダイヤモンドスラ
イサーで切断し、それぞれの接合ウェーハから約2mm
角のベレットを20個ずつ切断分離し、これらを弗化水
素#25%水濃液中て25℃において20分間放置し、
水洗、乾燥後、その接合状況を調べた。即ち、ビンセッ
トて軽くボンドウェーハ及びベースウェーハ側を反対方
向に引張ったところ、第2図(b)に示す接合ウェーハ
から得られたベレットはその約半数かその接合部て互い
に分離したのに対し、本願発明に係る第2図(c)に示
す接合ウェーハから得られたベレットは、全くそのよう
な破壊か行なわれなかった。更に、顕微鏡でその境界面
したところ1本願発明に係る第2図(c)に示す接合ウ
ェーハ八から得られたベレットでは、特にベースウェー
ハと酸化膜の接合面ても、その中央部ではエツチング液
による腐食か進んていなかった。In order to investigate the durability against etching of the bonding interface,
The aforementioned bonded wafers (shown in FIGS. 2(b) and (c)) are cut with a thin blade, e.g., an 80 gm peripheral diamond slicer, approximately 2 mm from each bonded wafer.
Cut and separate the corner pellets into 20 pieces, and leave them in a concentrated solution of hydrogen fluoride #25% water for 20 minutes at 25°C.
After washing and drying, the bonding condition was examined. That is, when the bond wafer and base wafer sides were pulled in opposite directions using a bin set, about half of the pellets obtained from the bonded wafer shown in Figure 2(b) separated from each other at the bonded portion. The pellet obtained from the bonded wafer shown in FIG. 2(c) according to the present invention was not subjected to such destruction at all. Furthermore, when the interface was examined under a microscope, it was found that the pellet obtained from the bonded wafer 8 according to the present invention shown in FIG. The corrosion had not progressed.
本願発明の構造を有する接合ウェーハは、ボンドウェー
ハに例えば集積回路素子か公知の方法て形成される場合
、山間の酸化膜を熱酸化形成するならば、ベースウェー
ハに当該酸化膜か形成されるのと比較してボンドウェー
ハか誘電体である酸化膜によって、集積回路素子の形成
される領域の片面か完全に被覆されていることにょワて
、当該集積回路素子の耐絶縁特性、その他の電気特性か
良好に実現される。In the bonded wafer having the structure of the present invention, when an integrated circuit element is formed on the bond wafer by a known method, if an oxide film between the peaks is formed by thermal oxidation, the oxide film is formed on the base wafer. Compared to the bond wafer or the dielectric oxide film, the area where the integrated circuit element is formed is completely covered on one side or the other, and the insulation resistance and other electrical properties of the integrated circuit element are lower. or well realized.
(発明の効果)
以上の説明て明らかな如く本発明によれば、2枚の#!
1、第2ウェーハのうちの第2ウェーハの少なくとも片
面に酸化膜を形成し、該酸化膜が中間層になるようにし
て第2ウェーハを第1ウェーハに重ね合わせた後、これ
ら第1.第2ウェーハを所定温度に加熱して両者を接着
した後、第2ウェーハの表面を研磨してこれを薄膜化す
ることによって接合ウェーハを得るようにし、又、前記
第1、第2ウェーハを接着した後、これら第1第2ウェ
ーハを熱酸化処理してその全表面に酸化膜を形成するよ
うにしたため、結合強度及び接合界面のエツチング液に
対する耐浸食性か高く、集積回路素子用の基板として優
れた接合ウェーハを得ることかできるという効果か得ら
れる。(Effects of the Invention) As is clear from the above explanation, according to the present invention, two #!
1. After forming an oxide film on at least one side of the second wafer of the second wafers and stacking the second wafer on the first wafer so that the oxide film becomes an intermediate layer, After heating the second wafer to a predetermined temperature and bonding them together, the surface of the second wafer is polished and made into a thin film to obtain a bonded wafer, and the first and second wafers are bonded together. After that, these first and second wafers were subjected to thermal oxidation treatment to form an oxide film on their entire surface, so the bonding strength and the erosion resistance against etching liquid at the bonding interface were high, making it suitable as a substrate for integrated circuit devices. It is possible to obtain an excellent bonded wafer.
4゜121面の簾中な説明
第1区(a)〜(e)は本発明に係る製造方法をその工
程順に示す説明図、第2図及び第3図は各種の接合ウェ
ーハに対して実施された引っ張り試験結果を示す図であ
る。4゜121-sided blind explanation Section 1 (a) to (e) are explanatory diagrams showing the manufacturing method according to the present invention in the order of the steps, and Figures 2 and 3 are diagrams showing the process carried out on various bonded wafers. It is a figure which shows the result of the tensile test carried out.
1・・・ボンドウェーハ(第2ウェーハ)、2・・・ベ
ースウェーハ(第1ウェーハ)、3.4・−・酸化膜、
5・・・接合ウェーハ。1... Bond wafer (second wafer), 2... Base wafer (first wafer), 3.4... Oxide film,
5... Bonded wafer.
Claims (1)
なくとも片面に酸化膜を形成し、該酸化膜か中間層にな
るようにして第2ウェーハを第1ウェーハに重ね合わせ
た後、これら第1、第2ウェーハを所定温度に加熱して
両者を接着した後、第2ウェーハの表面を研磨してこれ
を薄膜化することによって接合ウェーハを得ることを特
徴とする接合ウェーハの製造方法。An oxide film is formed on at least one side of the second wafer of the two first and second wafers, and the second wafer is stacked on the first wafer so that the oxide film becomes an intermediate layer. A method for manufacturing a bonded wafer, which comprises heating the first and second wafers to a predetermined temperature to bond them together, and then polishing the surface of the second wafer to make it a thin film to obtain a bonded wafer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2045778A JPH0795505B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing bonded wafer |
| DE69126153T DE69126153T2 (en) | 1990-02-28 | 1991-02-28 | Process for the production of bonded semiconductor wafers |
| EP91301680A EP0444943B1 (en) | 1990-02-28 | 1991-02-28 | A method of manufacturing a bonded wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2045778A JPH0795505B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing bonded wafer |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9209954A Division JP3030545B2 (en) | 1997-07-19 | 1997-07-19 | Manufacturing method of bonded wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03250617A true JPH03250617A (en) | 1991-11-08 |
| JPH0795505B2 JPH0795505B2 (en) | 1995-10-11 |
Family
ID=12728752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2045778A Expired - Lifetime JPH0795505B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing bonded wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795505B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183477A (en) * | 1993-12-22 | 1995-07-21 | Nec Corp | Manufacture of semiconductor substrate |
| JPH1126336A (en) * | 1997-07-08 | 1999-01-29 | Sumitomo Metal Ind Ltd | Laminated semiconductor substrate and method of manufacturing the same |
| JP2006156770A (en) * | 2004-11-30 | 2006-06-15 | Shin Etsu Handotai Co Ltd | Direct bonding wafer manufacturing method and direct bonding wafer |
| CN110024080A (en) * | 2016-12-19 | 2019-07-16 | 信越半导体株式会社 | The manufacturing method of SOI wafer |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5013155A (en) * | 1973-06-06 | 1975-02-12 | ||
| JPS6050970A (en) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | Semiconductor pressure converter |
| JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
| JPH01232244A (en) * | 1988-03-12 | 1989-09-18 | Fujitsu Ltd | Inspecting method for stuck soi substrate |
| JPH01302740A (en) * | 1988-05-30 | 1989-12-06 | Toshiba Corp | Dielectric isolation semiconductor substrate |
| JPH02238663A (en) * | 1989-03-10 | 1990-09-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0362511A (en) * | 1989-07-31 | 1991-03-18 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1990
- 1990-02-28 JP JP2045778A patent/JPH0795505B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5013155A (en) * | 1973-06-06 | 1975-02-12 | ||
| JPS6050970A (en) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | Semiconductor pressure converter |
| JPS615544A (en) * | 1984-06-19 | 1986-01-11 | Toshiba Corp | Manufacture of semiconductor device |
| JPH01232244A (en) * | 1988-03-12 | 1989-09-18 | Fujitsu Ltd | Inspecting method for stuck soi substrate |
| JPH01302740A (en) * | 1988-05-30 | 1989-12-06 | Toshiba Corp | Dielectric isolation semiconductor substrate |
| JPH02238663A (en) * | 1989-03-10 | 1990-09-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0362511A (en) * | 1989-07-31 | 1991-03-18 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183477A (en) * | 1993-12-22 | 1995-07-21 | Nec Corp | Manufacture of semiconductor substrate |
| JPH1126336A (en) * | 1997-07-08 | 1999-01-29 | Sumitomo Metal Ind Ltd | Laminated semiconductor substrate and method of manufacturing the same |
| JP2006156770A (en) * | 2004-11-30 | 2006-06-15 | Shin Etsu Handotai Co Ltd | Direct bonding wafer manufacturing method and direct bonding wafer |
| CN110024080A (en) * | 2016-12-19 | 2019-07-16 | 信越半导体株式会社 | The manufacturing method of SOI wafer |
| CN110024080B (en) * | 2016-12-19 | 2023-05-02 | 信越半导体株式会社 | Method for manufacturing SOI wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0795505B2 (en) | 1995-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100668160B1 (en) | Manufacturing method of SOI wafer and SOI wafer manufactured by this method | |
| JP3900741B2 (en) | Manufacturing method of SOI wafer | |
| JP2856030B2 (en) | Method for manufacturing bonded wafer | |
| US5071785A (en) | Method for preparing a substrate for forming semiconductor devices by bonding warped wafers | |
| US5395788A (en) | Method of producing semiconductor substrate | |
| JP5188672B2 (en) | Manufacturing method of composite substrate | |
| EP0444943B1 (en) | A method of manufacturing a bonded wafer | |
| JPH01315159A (en) | Dielectric-isolation semiconductor substrate and its manufacture | |
| JPH0719738B2 (en) | Bonded wafer and manufacturing method thereof | |
| CN101675499B (en) | Soi substrate manufacturing method and soi substrate | |
| WO2004051715A1 (en) | Method for manufacturing soi wafer | |
| JPH03250617A (en) | Manufacture of bonded wafer | |
| TW201826402A (en) | Method for smoothing the surface of a semiconductor substrate on an insulator | |
| JP3921823B2 (en) | Manufacturing method of SOI wafer and SOI wafer | |
| JP3030545B2 (en) | Manufacturing method of bonded wafer | |
| JP2699359B2 (en) | Semiconductor substrate manufacturing method | |
| JPH0680624B2 (en) | Method for manufacturing bonded wafer | |
| JP2003068593A (en) | Semiconductor laminated substrate and method of manufacturing the same | |
| JPH05275300A (en) | Method of joining semiconductor wafers | |
| JPH11345954A (en) | Semiconductor substrate and its manufacture | |
| CN112259675B (en) | Film bonding body with patterns, preparation method and electronic device | |
| JP2609198B2 (en) | Semiconductor substrate manufacturing method | |
| JP3635885B2 (en) | Method for evaluating crystal defects in SOI substrate | |
| JP4092874B2 (en) | Manufacturing method of SOI wafer and SOI wafer | |
| JP3518083B2 (en) | Substrate manufacturing method |