JPH03250890A - Detection circuit for nonstandard signal - Google Patents

Abstract

PURPOSE:To surely detect a nonstandard signal by detecting respectively distortion of a time axis of a short range such as one line by means of an inter-line difference signal of a subcarrier signal and distortion of a time axis of a long range such as one frame by means of an inter-frame difference signal of the subcarrier signal. CONSTITUTION:The circuit is provided with an input terminal IN, an APC circuit 10, a clock generating circuit 11, an A/D converter circuit 12, delay circuits 13, 23, adder circuits 14, 24, coring circuits 15, 25, band pass filter circuits 16, 26, absolute value circuits 17, 27, integration circuits 18, 28, comparator circuits 19, 29, a reference value latch circuit 30, a discrimination circuit 31 and an output terminal OUT. Then the distortion of a time axis of a short range such as one line is detected by means of an inter-line difference signal of a subcarrier signal and the distortion of a time axis of a long range such as one frame is detected by means of an inter-frame difference signal of the subcarrier signal respectively. Thus, the detection accuracy of the nonstandard signal is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a non-standard signal detection circuit installed in a television receiver.

(Prior art) For television signals of the NTSC standard system or similar systems, various three-dimensional image quality improvement processes are performed using the correlation between adjacent lines and the correlation between adjacent frames caused by inherent frequency interleaving. will be held.

On the other hand, with the recent diversification of video information sources, non-NTSC signals unrelated to frequency interleaving, such as video signals of home game consoles, are used as input video signals to television receivers.
Video signals are becoming more and more mixed. Also, like the playback signal of a home VTR, it originally had a frequency interleaving relationship, but due to fluctuations in the tape running speed during recording/playback, etc., the time axis becomes distorted, and as a result, the frequency interleaving relationship changes. Some have been lost and become non-standard signals. In this way, video signals that do not have a frequency interleaving relationship from the beginning and those that lose such a relationship midway through are collectively referred to as non-standard signals.

The three-dimensional image quality improvement process described above is based on the premise that the processing target is a standard signal, and if the same image quality improvement process is applied to a non-standard signal, the image quality will actually deteriorate.

For this reason, a non-standard signal detection circuit is added to constantly monitor whether the video signal to be processed is a standard signal or a non-standard signal, and to stop the image quality improvement process if it is a non-standard signal.

Conventionally, as a detection circuit for such non-standard signals, the second
As shown in the figure, a color subcarrier (subcarrier signal) Fsc phase-synchronized with a color burst signal is converted into a digital signal by an A/D conversion circuit 31, and whether or not the phase is inverted between adjacent lines is determined. There is a line delay circuit 32, an addition circuit 33, an integration circuit 34, a reference value holding circuit 35, and a comparison circuit 36 for determining whether or not the signal is a standard signal.

As shown in FIG. 3, the other detection circuit uses a V counter 41 to count the clock signal 4fsc phase-synchronized with the color burst signal to generate a vertical synchronizing pulse p, which is combined with the actual composite video signal. In some cases, whether or not the signal is a standard signal is detected by determining whether the phase difference with the vertical synchronizing pulse Vp extracted from the signal is within a permissible range using the phase comparator circuit 42.

(Problem to be Solved by the Invention) Among the conventional non-standard signal detection circuits described above, those that determine whether the phase of a color burst signal is inverted between adjacent lines do not detect signals reproduced from a VTR or the like. It may fail to be detected as a standard signal. This is because distortion in the time axis due to tape running jitter may remain within an allowable range in a short range such as between adjacent lines. In general, distortions in the time axis between adjacent lines are irregularly accumulated over one frame, resulting in large distortions in the time axis, and image quality improvement processing that assumes phase reversal between adjacent frames actually reduces the image quality. It will deteriorate.

In addition, with a system that generates field pulses from a system clock phase-synchronized with the color burst signal and detects the phase difference with the actual field pulses, there is a risk of failing to detect short-range time axis distortions between adjacent lines. There is. This is because, although the time axis distortion caused by tape running jitter exceeds the allowable range in short ranges such as between adjacent lines, these distortions are accumulated over one field in a destructive manner, resulting in the l field. This is because the distortion of the time axis may remain within the permissible range.

(Means for Solving the Problems) A non-standard signal detection circuit according to the present invention includes an A/D conversion circuit that converts an analog subcarrier signal phase-synchronized with a color burst signal into a digital subcarrier signal, and The converted digital subcarrier signal is
A first adding circuit that generates an added value between adjacent lines while delaying the converted digital subcarrier signal by one frame, and a second adding circuit that generates an added value between adjacent frames while delaying the converted digital subcarrier signal by one frame. circuit and these first
．． A comparison that compares the added value generated by the second addition circuit with a predetermined reference value, and outputs a signal notifying that a non-standard signal has been detected if these added values exceed the reference value. It is equipped with a circuit.

That is, the non-standard signal detection circuit according to the present invention
Distortion in the time axis over a short range such as a line is detected by the difference signal between adjacent lines of the subcarrier signal, and distortion in the time axis over a long range such as 1 frame is detected by the difference signal between adjacent frames in the subcarrier signal. As a result, the detection accuracy of non-standard signals has been improved.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a non-standard signal detection circuit according to an embodiment of the present invention.

In the figure, IN is an input terminal for a video signal to be detected, 10 is an APC circuit, 11 is a clock generation circuit, 12 is an A/D conversion circuit, 13 is a 1-line delay circuit, 23 is a 1-frame delay circuit, 14.24 is an addition circuit, 15.25 is a coring circuit, 16.26 is a bandpass filter circuit, 17.27 is an absolute value circuit, 8.28 is an integration circuit, 19.29 is a comparison circuit, 20.30 is a reference value a holding circuit; 31 is a determination circuit;
OUT is an output terminal for the detection results.

The video signal on the input terminal IN is APC (automatic phase control)
The color burst signal that is supplied to the circuit 10 and superimposed on a predetermined portion thereof is extracted by a burst gate, amplified, and supplied to a phase-locked loop to generate a 3.58 MHz signal that is phase-synchronized with the side color burst signal. A subcarrier signal (color printing carrier wave signal) is generated. In the clock generation circuit 11, a clock signal CK having four times the frequency (4 fsc) of the subcarrier signal generated by the APC circuit 10 is generated, and distributed to each part of the detection circuit.

The subcarrier signal output from the APC circuit 10 is A
The /D conversion circuit 12 converts the signal into a digital signal in synchronization with the clock signal CK, and supplies the signal to one input terminal of the one-line delay circuit 13 and the adder circuit 14. The 1-line delay circuit 13 operates in synchronization with the clock signal CK.
It consists of an IFO, and the signal input here is delayed by one line and is supplied to the subsequent frame delay circuit 23, the other input terminal of the adder circuit 14, and one input terminal of the adder circuit 24. . The l-frame delay circuit 23 is composed of a FIFO that operates in synchronization with the clock signal CK,
The signal input here is delayed by one frame and then supplied to the other input terminal of the adder circuit 24.

Therefore, the adder circuit 14 outputs a difference signal between adjacent lines of digital subcarrier signals whose phase is synchronized with the color burst signal. Further, the adder circuit 24 outputs a difference signal between adjacent frames of the digital subcarrier signal that is phase-synchronized with the color burst signal.

If the video signal appearing at the input terminal IN is an NTSC standard signal, the phase of the subcarrier signal generated by the APC circuit 10 will be inverted between adjacent lines and also between adjacent frames.

In this case, the outputs of adder circuits 14 and 24 are both zero. On the other hand, if the video signal appearing at the input terminal IN is a non-standard signal, the phase relationship between adjacent lines and adjacent frames of the subcarrier signal generated by the APC circuit 10 is irregular. Therefore, the addition circuit 14
．． The output of 24 fluctuates irregularly.

The output of the adder circuit 14 is processed by a coring circuit 16 to remove low-level noise components, a bandpass filter circuit 16 to remove high-frequency noise components and DC components, and an absolute value circuit 17 to convert it into a non-polar signal. , is converted into a temporal average value over several to several tens of samples by an integrator circuit, and is supplied to one input terminal of a comparator circuit 19. The other input terminal of the comparison circuit 19 is supplied with the reference value being held in the reference value holding circuit 20 .

Similarly, the output of the adder circuit 24 is subjected to a coring circuit 26 to remove low-level noise components, and a bandpass filter circuit 26 to remove low-level noise components.
, high frequency noise components and DC components are removed, the absolute value circuit 27 converts it into a non-polar signal, the integrator circuit converts it into a temporal average value over several to tens of lines, and the comparison circuit 2
is supplied to one input terminal of 9. The other input terminal of the comparison circuit 29 is supplied with the reference value being held in the reference value holding circuit 30 .

Comparison circuit 19.29 compares the output of integration circuit 18.28 with the reference value held in reference value holding circuit 20.30, and if the former exceeds the latter, a detection signal indicating the appearance of a non-standard signal is determined. It is output to the circuit 30. The determination circuit 30 receives the output from the comparison circuits 19 and 29, determines the level of the non-standard signal, and outputs the result to the output terminal UT. That is, when only the interframe detection of the comparator circuit 30 becomes significant, a detection signal indicating the appearance of an interframe non-standard signal is output.

Further, when the outputs of the comparison circuits 19 and 29 are both significant, a detection signal indicating the appearance of a non-standard signal between frames and between lines is outputted to the output terminal OUT.

The configuration in which the APC circuit is installed in the non-standard signal detection circuit has been exemplified above. However, instead of installing this Apc circuit, an AP installed in the color signal reproducing circuit
It is also possible to adopt a configuration in which the subcarrier signal is supplied from the C circuit.

Similarly, the clock generation circuit may be configured to receive a clock signal generated elsewhere in the TV receiver instead of being installed in the non-standard signal detection circuit. Note that this clock signal may be created based on the horizontal frequency instead of the subcarrier signal.

Furthermore, although a configuration has been exemplified in which the absolute value of the added value is compared with a non-polar reference value, a configuration may also be adopted in which the added value is compared with a reference value of the corresponding polarity for each positive or negative polarity.

Alternatively, the integration circuit for the absolute value of the added value may be removed, and when the same judgment result is outputted a predetermined number of times consecutively from the judgment circuit, the judgment result may be determined to be significant.

(Effects of the Invention) As explained in detail above, in the non-standard signal detection circuit according to the present invention, distortion in the time axis of a short range of about one line is detected by the difference signal between adjacent lines of the subcarrier signal, and by the difference signal between adjacent lines of the subcarrier signal. Since distortion in the time axis over a long range such as a frame is detected using the difference signal between adjacent frames of the subcarrier signal, an effect is achieved in that non-standard signals can be reliably detected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a non-standard signal detection circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing the configuration of a non-standard signal detection circuit according to the prior art. be. IN...Input terminal for video signal to be detected, IO...
・APC circuit, 11... Clock generation circuit, 12...
・A/D conversion circuit, 13...L line delay circuit, 23
... l frame delay circuit, 14.24 ... power supply circuit, 15.25 ... coring circuit, 16.26 ...
Bandpass filter circuit, 17.27... Absolute value circuit, 18
．． 28... Integrating circuit, 19.29... Comparing circuit, 2
0°30... Reference value holding circuit, 31... Judgment circuit,
OUT...Detection signal output terminal.

Claims (1)

[Claims] A for converting an analog subcarrier signal phase-synchronized with a color burst signal into a digital subcarrier signal.
/D conversion circuit; a first addition circuit that generates a sum value between adjacent lines while delaying the converted digital subcarrier signal by one line; a second addition circuit that generates an addition value between adjacent frames with a delay of 10 minutes, and a comparison of the addition values generated by the first and second addition circuits with a predetermined reference value, and these addition values are determined as the reference value. 1. A non-standard signal detection circuit, comprising: a comparison circuit that outputs a signal indicating detection of a non-standard signal when the value exceeds a value.